JPS58184759A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58184759A
JPS58184759A JP6830682A JP6830682A JPS58184759A JP S58184759 A JPS58184759 A JP S58184759A JP 6830682 A JP6830682 A JP 6830682A JP 6830682 A JP6830682 A JP 6830682A JP S58184759 A JPS58184759 A JP S58184759A
Authority
JP
Japan
Prior art keywords
film
semiconductor film
island
semiconductor
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6830682A
Other languages
Japanese (ja)
Inventor
Kenji Maeguchi
前口 賢二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6830682A priority Critical patent/JPS58184759A/en
Publication of JPS58184759A publication Critical patent/JPS58184759A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

PURPOSE:To improve the dielectric breakdown withstand voltage of a gate oxide film at the end part of its island-formed semiconductor film by a method wherein a sufficiently long oxide film is formed around the island-formed semiconductor film located on an insulated substrate without performing a high temperature oxidization treatment for a long period. CONSTITUTION:The first semiconductor film and an oxidization-resistive film are coated on the insulated substrate 1 successively, and an island-formed semiconductor film 23, having an oxidization-resistive film pattern 22 on the upper surface, is formed by performing a patterning on the above-mentioned films. The second semiconductor film is deposited on the whole surface. The second semiconductor film 25 is left on the side face of the film 23 or on the surface of the substrate 21 which is exposed on the side face of the film 23. An oxide film 26 is formed around the film 23. As a result, the dielectric breakdown withstand voltage of the gate oxide film at the end part of the film 23 can be improved.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は絶縁基板上に素子を形成した構造の半導体装置
の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device having a structure in which elements are formed on an insulating substrate.

し発明の技内的背景とその間m点〕 この檜の半44&装置、例えばS 08 (5ilic
onon 5apphire )に代表される半導体装
置はシリコン基板を用いたバルク半導体装置に比べて配
線と基数間、拡散層と基板間等の浮遊gilが小キく、
かつ素子間の分離が完全であるので、高速動作、凋蛤厩
を実現できるという利点を有する。
The technical background of the invention and m points in between] This cypress half 44 & device, for example S 08 (5ilic
Compared to bulk semiconductor devices using silicon substrates, semiconductor devices typified by 5apphire (onon 5apphire) have smaller stray gils between wiring and bases, between diffusion layers and substrates, etc.
In addition, since the isolation between the elements is perfect, it has the advantage of realizing high-speed operation and rapid operation.

ところで、上記SOS傅造の半導体装置は従来、次のよ
うな方法により製造されている。壜ず、サファイア基数
1上のp−型の単結晶シリコン−を気相成長させ、これ
を異方性エツチング法を用いてパターニングして断面が
台形状をなす島状のシリ・ン膜2を形成する(第1 u
%示)つづいて、p−型のシリコン腺2上にゲート酸化
l1II3を介して例えば碩#ドープ多結晶シリコンか
らなるゲートIIl極4を形成し、このゲート醒憔4を
マスクとしてn型不純物をp−型シリコン11$lJに
ドーピングしてn4型のソース、ドレイン領域5.6を
形成する。次いで、全面にOMD−8i01fi7を堆
積、ソース、ドレイン領域5.6に対応する該5i01
膜7の一部にコシタクトホールS、Sを開孔し、AI!
膜を全面に魚肴した後、これをバターニングしてソース
、ドレインの電極9.IQを形成してMOS)ランジス
メを製造する(第1図tb+図示)。
Incidentally, the semiconductor device manufactured by SOS Fuzo is conventionally manufactured by the following method. P-type single crystal silicon on a sapphire base of 1 is grown in a vapor phase, and then patterned using an anisotropic etching method to form an island-shaped silicon film 2 with a trapezoidal cross section. form (first u
Next, a gate IIl pole 4 made of, for example, red-doped polycrystalline silicon is formed on the p-type silicon gland 2 via a gate oxide l1II3, and using this gate oxidation layer 4 as a mask, an n-type impurity is added. P-type silicon 11$lJ is doped to form n4 type source and drain regions 5.6. Next, OMD-8i01fi7 is deposited on the entire surface, and the 5i01 corresponding to the source and drain regions 5.6 is
Koshitact holes S and S are opened in a part of the membrane 7, and AI!
After coating the entire surface of the film, it is buttered to form source and drain electrodes 9. IQ is formed to produce a MOS (MOS) plunger (as shown in FIG. 1, tb+).

上記方法によれば量率な工程で島状のシリコン膜2を分
離できるが、次のような種々の欠点シ□。
According to the above method, the island-shaped silicon film 2 can be separated in a quantitative process, but there are various drawbacks as follows.

を有する。第1の欠点は島状のシリコン膜2 m1面に
発生する奇生M08トランジスタの効果である。これは
、島状のシリコン−2表面の(100)面方位からなる
MOS)ランジスタと並列に形成される一面の(111
、)面方位をもつMOS)ランジスタが(100)向よ
りも多くのS iS r OH界fIie位をもっこと
に起因する。この奇生MO8トランジスメ効釆によって
、漏れ′4流の増加や信頼性の低下を招<、$2O欠点
は島状のシリコンHz側面に成長されたゲ上にゲート酸
化$3となる熱酸化f1411が一様に成長せず、サフ
ァイア基板1界面近傍で薄くなることに起因する。こう
した原因は孤立した島状のシリコン膜2端部のサファイ
ア基板1界面での敞#欠乏によるものと思われる。
has. The first drawback is the effect of an anomalous M08 transistor generated on the island-shaped silicon film 2m1 surface. This is a (111
,) This is due to the fact that the MOS) transistor with plane orientation has more S iS r OH fields fIie orientation than the (100) orientation. This strange MO8 transistor effect causes an increase in leakage current and a decrease in reliability. This is due to the fact that the sapphire substrate 1 does not grow uniformly and becomes thin near the interface of the sapphire substrate 1. This is thought to be due to the lack of # at the interface of the sapphire substrate 1 at the end of the isolated island-like silicon film 2.

−万、別のSOS構造のMOS)ランジスタの製造とし
て次のような遺択敵化による分離技術′t−通用した方
法が知られている。まず、サファイア1檄1にp−型単
結晶シリコン膜を気相成長させ、このシリコン−上に酸
化膜及び耐鐘化性のシリコン窒化族を形成した後、素子
分離領域となるシリコン窒化族及び酸化膜を順次バター
ニングしてシリコン窒化膜パターン12及び酸イヒ躾パ
ターン13を夫々形成する。つづいて、シリコン窒化膜
パターン12を耐鍍化性マヌクとして高温酸素雰囲気中
で熱処理してフィールド酸化i1$1(素子分離領域)
14を形成して島状のシリコン$15を作る(83図(
a1図示)。次いで、シリコン窒化膜パターン12及び
酸化膜パターン13を除去した後、前述した方法と同様
に島状のシリコンgisにM08トランジスタを造る(
第3図(b)図示)。
- 10,000, Another method for manufacturing a MOS transistor with an SOS structure is known, which is a separation technique using selective enemy formation as follows. First, a p-type single-crystal silicon film is vapor-phase grown on a sapphire substrate, and after forming an oxide film and a silicon nitride film with resistance to heat on the silicon, the silicon nitride film, which will become an element isolation region, and The oxide film is sequentially patterned to form a silicon nitride film pattern 12 and an oxide film pattern 13, respectively. Subsequently, the silicon nitride film pattern 12 is heat-treated in a high temperature oxygen atmosphere to make it resistant to corrosion, and field oxidation i1 (element isolation region) is performed.
14 to make an island-shaped silicon $15 (Fig. 83 (
a1 shown). Next, after removing the silicon nitride film pattern 12 and the oxide film pattern 13, an M08 transistor is fabricated on the island-shaped silicon GIS in the same manner as described above.
(Illustrated in FIG. 3(b)).

上記方法によれば前述したゲート酸化膜O絶縁破壊耐圧
の低下を改善できるものの、次のような欠点を有する。
Although the above-mentioned method can improve the above-mentioned decrease in dielectric breakdown voltage of the gate oxide film O, it has the following drawbacks.

■ 厚いフィールド販化誤14を形成するのに高温で長
時間の熱処理を必要とするため、サファイア1嶺1から
のAjのオートドーピング等によりシリコン膜15とサ
ファイア基板1界向に多量の界面4荷が生じ、漏れ電流
の増大を招く、特に、鳳チャンネルMO&)ランジスタ
を島状のシリコン護15に形成した場合、ソース、ドレ
イン領域5.6がゲート電li4への電圧の印加に関係
なく前記界面を通って導通する、いわゆるバックチャン
ネル効果を生じる。
■ Because it requires heat treatment at high temperature and for a long time to form a thick field solder 14, a large amount of interface 4 is formed in the direction between the silicon film 15 and the sapphire substrate 1 due to auto-doping of Aj from the sapphire ridge 1. In particular, when a transistor is formed on the island-shaped silicon barrier 15, the source and drain regions 5.6 are exposed to the above voltage regardless of the voltage applied to the gate voltage li4. Conducting through the interface, a so-called back channel effect occurs.

■ フィールド酸化膜14の形成後、シリコン窒化膜パ
ターン12下、特に厚いフィールド酸化膜14近傍で強
い応力が発生し、シリコン麟15中に結晶欠陥を誘起す
る。このため、デバイス特性の劣化、特に漏れamの増
加を招く。
(2) After the field oxide film 14 is formed, strong stress is generated under the silicon nitride film pattern 12, especially in the vicinity of the thick field oxide film 14, inducing crystal defects in the silicon layer 15. This causes deterioration of device characteristics, particularly an increase in leakage am.

■ 厚いフィールド酸化11414の形成時、シ啼コン
窒化躾パターン12下への横方向から酸化が進行し、素
子寸法が細小する。これはマスク寸法上、余裕をとる必
要が生じ、ひいては素子寸法、素子間寸法の微細化の障
害となる。
(2) When forming the thick field oxide 11414, the oxidation progresses from the lateral direction below the silicon nitride pattern 12, and the device size becomes smaller. This requires a margin in mask dimensions, which in turn becomes an obstacle to miniaturization of element dimensions and inter-element dimensions.

〔発明の目的〕[Purpose of the invention]

本発明は高温、長時間の熱酸化処理を施膚ずに島状の半
導体膜端部でのグー)ト酸化鵬の絶縁11 破壊耐圧を改善した半導体装置の製造方法を提供しよう
とするものである。
The present invention aims to provide a method for manufacturing a semiconductor device that improves the breakdown voltage of the insulation at the end of an island-shaped semiconductor film without performing a high-temperature, long-term thermal oxidation treatment. be.

し発明の概要〕 本発明は絶縁基板上に第lの半導体膜及び耐酸化性膜を
順次被覆する工程と、これらの膜をパターニングして上
面に耐酸化性膜パターンを有する島状半導体膜を形成す
る工程と、この島状半導体膜の側面もしくは1411面
と産出した絶縁基板面に第2の半導体yst残存させる
工程と、残存した第2の半導体膜を鹸化して前記島状半
導体膜の周囲に酸化膜を形成する工程とにより、高温、
長時間の熱酸化処理を施さずに島状半導体膜端部でのゲ
ート酸化膜の絶縁破壊耐圧を改善することを青子とする
[Summary of the Invention] The present invention includes a step of sequentially coating an insulating substrate with a first semiconductor film and an oxidation-resistant film, and patterning these films to form an island-shaped semiconductor film having an oxidation-resistant film pattern on the upper surface. a step of leaving a second semiconductor yst on the side surface or 1411 plane of this island-like semiconductor film and the surface of the produced insulating substrate; and a step of saponifying the remaining second semiconductor film to form a layer around the island-like semiconductor film. By forming an oxide film on the
Aoko aims to improve the dielectric breakdown voltage of the gate oxide film at the end of the island-shaped semiconductor film without performing long-term thermal oxidation treatment.

〔発明の実施例〕[Embodiments of the invention]

次に1本発明fnチャンネルMO8LSIの製造に適用
した例について区画を参照して説明する。
Next, an example in which the present invention is applied to manufacturing an fn channel MO8LSI will be described with reference to sections.

実施例1 (1)  まず、絶縁基&、□′1.、例えばサファイ
ア基板21上にp−型の単結晶シリコン膜(第1の半導
体膜)を気相成長させ、爽に該シリコン膜上にシリコン
菫化躾を堆積した。つづいてシリコン窒化膿をOF、+
H,ガスのりアクティライオ/エツチング法(RIg法
)を用いたフォトエツチング技術によりパターニングし
て複数のシリコン窒化膜パターン22・・・管形成した
後、更にOCZffiガスの几IE法を用いたフォトエ
ツチングM術によりシリコン映をパターニングして複数
の@面が略圭直な島状シリコン1sj!・・・を形成し
た(第4図ta)図示)。
Example 1 (1) First, an insulating group &, □′1. For example, a p-type single crystal silicon film (first semiconductor film) was grown in a vapor phase on a sapphire substrate 21, and a silicon oxide film was then deposited on the silicon film. Next, apply silicon nitride pus, +
After forming a plurality of silicon nitride film patterns 22...tubes by patterning using a photoetching technique using a gas paste activating/etching method (RIg method), photoetching is further performed using an OCZffi gas IE method. An island-shaped silicon 1sj is created by patterning the silicon film using M technique and has multiple @ planes that are almost straight! ... was formed (as shown in Figure 4, ta)).

(if)  次いで、全面に薄いアンドープ多結晶シリ
コンS(第20半祷体摸)24を堆積した(II4図t
b+図示)。つづいて、基板21主面に対して生直な方
向にエツチングが進行する0 01mFmガスを用い友
RIEに・より多結晶シリコン膜24をそのS*程夏エ
ツチングした。この時、第4図(c)K不す如(、島状
シリコンllL[23・・・側面に多結晶シリコン膜2
5が残存した。ひきつづき、商諷酸票雰囲気中で熱処理
を施して残存多結晶シリコン躾25・・・を全て酸化し
、島状シリコン護23・・・周囲に酸化膜26・・・を
形成した(第4図(d)図示)。なお、この工程におい
て、島状シリコンflJ23・・・上面は耐酸化性のシ
リコンV化膜パターン22・・・で握われているため、
酸化されるのを阻止できた。
(if) Next, a thin undoped polycrystalline silicon S (20th half-body) 24 was deposited on the entire surface (Fig. t of II4).
b+Illustrated). Subsequently, the polycrystalline silicon film 24 was etched by RIE using 0.01 mFm gas, which etches in a direction perpendicular to the main surface of the substrate 21, to the extent of S*. At this time, as shown in FIG.
5 remained. Subsequently, heat treatment was performed in a commercial acid atmosphere to completely oxidize the remaining polycrystalline silicon layer 25, and an oxide film 26 was formed around the island-like silicon layer 23 (Fig. 4). (d) As shown). In this step, since the upper surface of the island-shaped silicon flJ23 is held by the oxidation-resistant silicon V film pattern 22,
It was able to prevent it from being oxidized.

(…) 次いで、シリコン窒化腺パL−ン22・・・を
除去した後、島状シリコン膜23・・・表面に熱酸化膜
を成長させ、更に全面に砒累ドープ多結晶シリコン護を
堆積した。つづいて、砒累ドープ多結晶シリコン躾をパ
ターニングしてゲート4懐27・・・を形成し、これを
マスクとして熱酸化膜を選択エツチングしてゲート酸化
1112B・・・を形成した後、ゲート′離慣27・・
・をマスクとしてn型不純物、例えば砒素をp−型の島
状シーリコン映23・・・にイオン注入し、活性化して
ソース、ドレイン領域となるn4型領域29・・・を形
成した。
(...) Next, after removing the silicon nitride gland pattern 22..., a thermal oxide film is grown on the surface of the island-like silicon film 23..., and an arsenic-doped polycrystalline silicon film is further deposited on the entire surface. did. Next, the arsenic-doped polycrystalline silicon film is patterned to form gates 4 and 27, and using this as a mask, the thermal oxide film is selectively etched to form gate oxide 1112B. Riju 27...
Using . as a mask, n-type impurities, such as arsenic, were ion-implanted into the p-type silicon islands 23, and activated to form n4-type regions 29, which become source and drain regions.

ひきつづき、全面4C0VI)−8i O! !l! 
30 k堆積し、コンタクトホール31・・・を開孔し
た後、全面にムt*+島着し、これをパターニングして
ソース、ドレイン等の取出し人1t1i2?l1412
・・・を形成してnチャンネルMo5LSI&製造した
(第4図te1図ボ)。
Continuing, the entire surface 4C0VI)-8i O! ! l!
After depositing 30K and opening contact holes 31..., Mt*+ islands are deposited on the entire surface, and this is patterned to take out sources, drains, etc. 1t1i2? l1412
... was formed to produce an n-channel Mo5LSI (Figure 4, te1, box).

しかして、本発明によれば上面に耐酸化性Oシリコン窒
化膜パターン22・・・を有する島状シリコン膜23・
・・側面に多結晶シリコンH2s・・・を残存させ、こ
の残存多結晶シリコyyzs・・・を熱酸化するため、
島状シリコン#23・・・IJIを酸化させることなく
、単時間の熱酸化処理で島状シリコン膜23・・・の@
−周囲に十分厚い酸化膜26・・・を形成できる。即−
ち、酸化に要する時間は、残存チ結晶シリコン躾25・
・・の厚さによって決定されるが、該多結晶シリコン@
XS・・・の1+4さは酸化後の酸化膜26・・・がM
O8I、8Iの動作電圧Vこ十分耐えられれば良(、数
百を以上あれは十分であるので、酸化時間は従来の選択
敲化法に比べて大巾に短縮できる。例えば、500Ie
の残存多結晶シリコン躾25・・・を酸化するのに要す
る時間は950℃、の温度条件の場合、僅か20分間程
度であ: 4式選択酸化法に比べると、1桁以上短縮で
きる。500 Ie(D残存多結晶シリコン朕25・・
・の酸化後の鍍化誤麟厚tff 10001ealiト
ナiJ、今4(7)L8Iで0ゲ−一ト酸化膜の膜厚が
5001e以下であること考えると、該ゲート酸化膜の
絶縁破壊耐圧を十分前記酸化膜26・・・で同上できる
According to the present invention, the island-like silicon film 23 having the oxidation-resistant O-silicon nitride film pattern 22 on the upper surface.
...In order to leave polycrystalline silicon H2s... on the side surface and thermally oxidize this remaining polycrystalline silicon yyzs...
Island-shaped silicon #23... without oxidizing IJI, island-shaped silicon film 23... is processed by thermal oxidation treatment for one hour.
- A sufficiently thick oxide film 26 can be formed around the periphery. Immediately
The time required for oxidation is approximately 25.
It is determined by the thickness of the polycrystalline silicon@
1+4 of XS... is the oxide film 26 after oxidation is M
It is sufficient to withstand the operating voltage V of O8I, 8I (a few hundred or more is sufficient, so the oxidation time can be greatly shortened compared to the conventional selective polishing method. For example, 500Ie
The time required to oxidize the remaining polycrystalline silicon oxide 25 is only about 20 minutes at a temperature of 950° C., which can be shortened by more than an order of magnitude compared to the 4-type selective oxidation method. 500 Ie (D residual polycrystalline silicon 25...
・Considering that the film thickness of the gate oxide film is 5001e or less in 10001eali Tona iJ, now 4 (7) L8I, the dielectric breakdown voltage of the gate oxide film is The same can be achieved with the oxide film 26.

上述の如く、熱酸化時間を大巾に塩動できるため、サフ
ァイア基板21からのA/のオートドーピングを抑制で
き、ひいてはサファイア基板21と島状シリコン族23
・・・との界面の劣化等に伴なうバックチャンネル効果
を有効に防止できる。また、島状シリコン膜23・・・
は酸化膜26・・・の形成後においても初紬寸法が確保
されるため、高密度のMO8LSIの製造が可能となる
。更に、シリコン窒化膜パターン22・・・端部下への
酸化がほとんど進行しないため選択酸化法で間融となっ
ている応力による結晶欠陥の発生は起こらず、リークを
流の少ない高性能のMO8LSIを得ることができる。
As mentioned above, since the thermal oxidation time can be changed over a wide range, autodoping of A/ from the sapphire substrate 21 can be suppressed, and as a result, the sapphire substrate 21 and the island-like silicon group 23
It is possible to effectively prevent back channel effects caused by deterioration of the interface with... In addition, the island-like silicon film 23...
Since the initial dimensions are ensured even after the oxide film 26 is formed, it is possible to manufacture a high-density MO8LSI. Furthermore, since oxidation hardly progresses under the silicon nitride film pattern 22...edge, crystal defects due to stress that are melted by the selective oxidation method do not occur, and high-performance MO8LSI with low leakage current can be realized. Obtainable.

その他、シリコン腺fi’RIEg↓リサファイ7基板
21而に対して略垂直にエレチングすれば、(100)
面方位の11面を有する島状シリコン膜23・・・を形
成でき、その結果884−8in界面準位を低ドできる
In addition, if the silicon gland fi'RIEg↓resify 7 substrate 21 is etched approximately perpendicularly, (100)
An island-like silicon film 23 having 11 planes can be formed, and as a result, the 884-8in interface level can be lowered.

なお、上記実施例1においては残存多結晶シリコン膜2
5・・・のみを暖化して酸化$26・・・を形成したが
、第5−図に示す如く島状シリコン族23・・・114
11thiの一部も酸化されるよう熱酸化処理を施して
酸化flp26’ ・・・を形成してもよい。
Note that in the first embodiment, the remaining polycrystalline silicon film 2
5... was heated to form oxidized $26..., but as shown in Figure 5, the island-like silicon group 23...114
Oxidized flp26' may be formed by performing thermal oxidation treatment so that a part of 11thi is also oxidized.

また、第6図(a)に示す如くアンドープ多結晶シリコ
ン膜に代ってボロンドープ多結晶シリコン映33を全面
に堆積した後、これを凰工罵によりエツチングして島状
シリコン−2J・・・@面にボロンドープ多結晶シリコ
ン展を残存され。
Further, as shown in FIG. 6(a), instead of the undoped polycrystalline silicon film, a boron-doped polycrystalline silicon film 33 is deposited over the entire surface, and then this is etched by etching to form an island-like silicon-2J film. The boron-doped polycrystalline silicon remains on the @ surface.

これを熱酸化処理して島状シリコンWI!23・・・周
囲に酸化膜26・・・を形成すると共にボロンを島状シ
リコン候−23・・・側面に拡散してp′型領領域34
・・を形成してもよい、このようにボロンドープ多結晶
シリコン映を用いれば、ソース、ドレイン間のチャンネ
ルカットとして機能するp0型饋域34・・・を形成で
きると共に、酸化速度が述くなることによる一層の熱酸
化時間の短縮を図ることができる。
This is then thermally oxidized to create island-shaped silicon WI! 23 Forms an oxide film 26 around the silicon island and diffuses boron into the side surface of the silicon island 23 to form a p' type region 34
By using a boron-doped polycrystalline silicon film in this way, it is possible to form a p0 type region 34 that functions as a channel cut between the source and drain, and the oxidation rate can be determined. As a result, the thermal oxidation time can be further shortened.

−に、第7図(a)に示す如く予め島状シリコン映23
・・・の1141J面に薄い酸化膜35・・・を形成し
た後、全面にアンド−1多結晶シリコン膜24を堆積す
る(第7図(b)図示)方法を採用してもよい。
-, as shown in FIG. 7(a), the island-shaped silicon film 23 is
It is also possible to adopt a method of forming a thin oxide film 35 on the 1141J plane of .

その他、全曲に多結晶シリコン族を堆積し、これを熱酸
化して酸化膜に変換した後、該酸化膜ftRIB法にて
エツチングして島状シリコン膜の側面8囲に酸化膜を残
存させてもよい。
In addition, a polycrystalline silicon group was deposited on all songs, and this was thermally oxidized to convert it into an oxide film, and then the oxide film was etched using the ftRIB method, leaving an oxide film around the side surfaces 8 of the island-shaped silicon film. Good too.

実施例2 (1)実施例1と同様に土工1にシリコン窒化膜パター
722・・・を有する島状シリコン換23・・・が形成
されたサファイア基板21の全面に多結晶シリコン#2
4を堆積した(第8図神)図示)。
Example 2 (1) Similar to Example 1, polycrystalline silicon #2 is applied to the entire surface of the sapphire substrate 21 on which the island-shaped silicon layer 23 with the silicon nitride film pattern 722 is formed on the earthwork 1.
4 (as shown in Figure 8).

つづいて、全面にフォトレジスト膜を壁布した。この時
、第8図(blに示す如く島状シリコン1換23・・・
側聞の段差部や島状シリコン膜23゜23間の距晦の短
い部分には厚いフォトレジスト膜36mが、突出したシ
リコン窒化膜パターン22・・・に対応する多結−シリ
コン麟24部分の上には薄いフォトレジスト1lis6
bが、夫々甲布された(第8図(b)図示)。ひきつづ
き、フォトレジスト膜を例えばO,プラズマにより徐々
にエツチングして突出した多結晶シリコン康24部分の
表面が藤出するまで行なった。この結果、島状シリコン
膜23,21間に7オトレジスト護36が残存した(第
8図(C)図示)。
Next, a photoresist film was applied to the entire surface. At this time, as shown in FIG.
A thick photoresist film 36m is applied to the side steps and the short distance between the island-shaped silicon films 23, 23, and the polycrystalline silicon film 24 corresponding to the protruding silicon nitride film patterns 22... Thin photoresist 1lis6 on top
b were covered with upper cloth (as shown in FIG. 8(b)). Subsequently, the photoresist film was gradually etched using, for example, O plasma until the surface of the protruding polycrystalline silicon layer 24 was exposed. As a result, a seven-layer photoresist layer 36 remained between the island-like silicon films 23 and 21 (as shown in FIG. 8C).

till  次いで、残存フォトレジスト膜36をマス
クとして、多結晶シリコン膜24を連択エツチングして
、島状シリコンfj23周囲と膝部したサファイア基板
上に多結晶シリコン膜31を残存させた後、残存フォト
レジスト$36f除去した(第8図1d)図示)。つづ
いて、残存多結晶シリコン膜37を高温酸巣雰囲気中で
熱処理して島状シリコンp!!2J・・・周囲と露出し
たサファイア基板21上に酸化@SSを形成した(第8
図(・)図示)。        11′(Ill  
次いで、!Il+!施例1と同様、シリコン窒化膜パタ
ーン22・・・を除去し、島状シリコン−21・・・に
ゲート酸化膜2や・・・を介してゲート電極27・・・
を形成し、n4″型領域29・・・、0VD−810、
膜80.コンタクトホール31・・・、人l配置ssλ
・・・を形成してnチャンネルM OS L 8Xを製
造した(第8図(f)図示)。こうして製造されたMO
8L8Iは実施例1と同様な効果を有するものであった
Next, using the remaining photoresist film 36 as a mask, the polycrystalline silicon film 24 is selectively etched to leave the polycrystalline silicon film 31 around the island-shaped silicon fj 23 and on the knee portion of the sapphire substrate. The resist $36f was removed (as shown in FIG. 8, 1d)). Subsequently, the remaining polycrystalline silicon film 37 is heat-treated in a high-temperature acidic atmosphere to obtain island-like silicon p! ! 2J... Oxidized @SS was formed on the sapphire substrate 21 exposed to the surroundings (8th
Figure (・) Illustrated). 11'(Ill
Next,! Il+! As in Example 1, the silicon nitride film patterns 22... are removed, and the gate electrodes 27... are formed on the silicon islands 21 via the gate oxide films 2 and...
, n4″ type region 29..., 0VD-810,
Membrane 80. Contact hole 31..., person arrangement ssλ
... was formed to produce an n-channel MOS L 8X (as shown in FIG. 8(f)). MO produced in this way
8L8I had the same effect as Example 1.

実施例3 (:)マず、サファイア基IPj21上にp−型の単結
晶シリコン膜を気相成長し、このシリコン膜上にシリコ
ン窒化膜及びリン珪化ガラス1I(P8G膜lを順次堆
積した。つづいて、P2O膜とシリコンV化編をa)’
;4+H,ガスのRIBを用いたフォトエツチング技術
により順次パターエン/L、てpsogパターン39・
・・、シリコン窒化膜パターン22・・・を形成し、更
に藤出したシリコン膜をCC6ガスのRIB法を用いた
フォトイt エツチング技術により□・・パターニングして島状シリ
コン!i1!23・・・を形成した(′s9図(a)図
示)。
Example 3 (:) First, a p-type single crystal silicon film was grown in vapor phase on the sapphire base IPj21, and a silicon nitride film and a phosphorus silicide glass 1I (P8G film 1) were sequentially deposited on this silicon film. Next, the P2O film and silicon V conversion part a)'
; 4+H, pattern en/L, psog pattern 39.
. . . A silicon nitride film pattern 22 . . . is formed, and the exposed silicon film is then patterned by photo-etching technology using the RIB method using CC6 gas to form island-shaped silicon! i1!23... was formed (as shown in Figure 's9 (a)).

(II)  次いで、全面にアンドープ多結晶シリコン
膜24を堆積した後窒素雰囲気にて熱処理を施した。こ
の時、第9図(b)に示す如(P80I!パターン39
・・・からりンがその周囲多結晶シリコン@j(部分に
拡散され、リンドープ多結晶シリコン11!領域40が
形成された。つづいて、シンドープ多結晶シリコンがア
ンドープ多結晶シリコンよりエツチングレートが約2倍
以上大暑いことを利用してOF4+H,ガスのプラズマ
エツチングによりP8G躾パターンS9・・・周囲のリ
ンドーグ多結晶シリコン領域4Qを選択的!(エツチン
グ除去して島状シリコン膜23・・・yRliIと鉢出
したサファイア基板21上にアンドープ多結晶シリコン
膜41を残存させた(第911(c)図示)。ひきつづ
き、PSG#パターン39・・・を除去した後、残存多
結晶シリコンs!41をAi温酸素雰井気中で熱処理し
て島状シリコン31135・・・周囲と非出したサファ
イア基板21上に酸化膜42を形成した(第9図(d)
図示)。
(II) Next, an undoped polycrystalline silicon film 24 was deposited on the entire surface and then heat treated in a nitrogen atmosphere. At this time, as shown in FIG. 9(b) (P80I! Pattern 39
... Phosphorus is diffused into the surrounding polycrystalline silicon @j (phosphorus-doped polycrystalline silicon 11! region 40).Subsequently, the etching rate of the phosphorus-doped polycrystalline silicon is lower than that of the undoped polycrystalline silicon. Taking advantage of the fact that it is more than twice as hot, OF4+H and gas plasma etching selectively removes the P8G pattern S9...surrounding Lindor polycrystalline silicon region 4Q! An undoped polycrystalline silicon film 41 was left on the exposed sapphire substrate 21 (as shown in Figure 911(c)).Subsequently, after removing the PSG# patterns 39..., the remaining polycrystalline silicon s!41 was removed. An oxide film 42 was formed on the sapphire substrate 21 which was exposed to the surroundings of silicon island 31135 by heat treatment in a hot oxygen atmosphere (FIG. 9(d)).
(Illustrated).

(+i+)  次いで、実り例1と同様、シリコン窒化
膜パターン22・・・を除去し、島状シリコンylxs
・・・上にゲート酸化膜2r・・・を介してゲート電極
2I・・・を形成し、更に♂型領域22・・・0VD−
8’i0@腰?6、コンタクトホール31・・・、At
妃Wij32・・・を形成してnチャンネルM<、+8
LSIを製造した(第9図+り図示)。こうしてp遺さ
れたMO8L8Iは実施例1と同様な効果を有するもの
であった。
(+i+) Next, as in Example 1, the silicon nitride film pattern 22... is removed, and the island-shaped silicon ylxs
. . . A gate electrode 2I . . . is formed thereon via a gate oxide film 2r .
8'i0@waist? 6. Contact hole 31..., At
Form Wij32... and n channel M<, +8
An LSI was manufactured (as shown in Figure 9). The MO8L8I thus left behind had the same effects as in Example 1.

なお、上記実施例2,3においては実施例1の変形例(
第5図〜第7図)と同様に島状シリコンil!倶面の一
部にまで酸化したり、p型領域を島状シリコン膜l11
1面に形成したり、予め島状シリコ784214面に酸
化膜を形成したりしてもよい。多結晶シリコン膜(第2
の半導体1i1りの代りに非晶質シリコン展を用いても
よい。
In addition, in the above-mentioned Examples 2 and 3, a modification of Example 1 (
5 to 7), island-shaped silicon il! Oxidize even a part of the surface, or replace the p-type region with an island-like silicon film l11.
It may be formed on one surface, or an oxide film may be formed on the 784214 surface of the silicon island in advance. Polycrystalline silicon film (second
Amorphous silicon may be used instead of the semiconductor 1i1.

上記実施例1〜3はnチャンネルMO8LSIに適用し
た例について説明したが、pチャンネルMO8LSI 
、0M08LS I等にも同様に適用できる。
Embodiments 1 to 3 described above are examples applied to n-channel MO8LSI, but p-channel MO8LSI
, 0M08LSI, etc.

〔発明の効果〕〔Effect of the invention〕

以上詳述した如く、本発明によれば高温、長時間の熱酸
化処理を施さずに、絶縁基板上の島状半導体躾の周囲に
充分な厚さの酸化膜を形成でき、もって島状半導体膜端
部でのゲージ酸化膜の絶縁破壊耐圧を改善できると共に
絶縁1仮と島状半導体膜の界面での劣化によるリーク電
流の発生を抑制でき、更に高密度化を達成で龜る等顕著
な効果を有する半導体装置の製造方法を提供できる。
As described in detail above, according to the present invention, it is possible to form an oxide film of sufficient thickness around the island-shaped semiconductor layer on the insulating substrate without performing high-temperature, long-term thermal oxidation treatment, and thereby It is possible to improve the dielectric breakdown voltage of the gauge oxide film at the edge of the film, suppress the occurrence of leakage current due to deterioration at the interface between the insulator 1 temporary and the island-like semiconductor film, and achieve remarkable results such as speeding up the achievement of higher density. It is possible to provide an effective method for manufacturing a semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(al 、 tb)は従来法による空気絶縁によ
り分離された。チャンネルMOf9)ランジスタO製造
玉程を示す断面図、第2図は第1図<aJ 、 (b)
の製造法−による問題点を説明するための断面図、腑3
図fa) * tb)F′i従来の遇択敵化法により分
離されたnチャンネルMOSトランジスタの製造工程を
示す1trthI図、第4図(a) 〜(e) tri
本発明の実施例1におけるnチャンネルMO8L8Iの
製造工程を示す断面図、第5図、−16:1.、図(1
) * (b)及び第7図(a) e cb)は実施例
1の変形例を示す断面編、第8図fal〜(f)は本覚
明の実施例2におけるnチャンネルMO8L8Iの製造
1徊を示す新画園、wc9図(al〜(clは本発明の
実施例3におけるnチャンネルMO8L8Iの製造工程
を示す断面図である。 21・・・サファイア基板、22・・・シリコン窒化膜
パターン、23・・・p−型の島状シリコン膜、24・
・・多結晶シリコン膜、2M、37.41・・・残存多
結晶シリコン膜、26.26’  、3B・−42・・
・厚い酸化膜、27・・・ゲート電極、28・・・ゲー
ト酸化膜、29・・・♂種領域、32・・・A/配線、
36・・・残存フォトレジスト腰、39・・・PEG展
パターン。 出厭入代理人 弁坂士 鈴 江 武 彦:′:
Figure 1 (al, tb) was separated by conventional air insulation. Channel MOf9) Cross-sectional view showing the manufacturing process of transistor O, Fig. 2 is Fig. 1<aJ, (b)
A cross-sectional diagram to explain the problems caused by the manufacturing method of
Fig.fa) *tb)F'i Fig. 4 (a) to (e) tri
Cross-sectional view showing the manufacturing process of n-channel MO8L8I in Example 1 of the present invention, FIG. 5, -16:1. , Figure (1
) *(b) and FIGS. 7(a) e cb) are cross-sections showing a modification of Example 1, and FIGS. Shingaen, wc9 (al~(cl) is a sectional view showing the manufacturing process of n-channel MO8L8I in Example 3 of the present invention. 21...Sapphire substrate, 22...Silicon nitride film pattern , 23...p-type island silicon film, 24.
...Polycrystalline silicon film, 2M, 37.41...Remaining polycrystalline silicon film, 26.26', 3B-42...
・Thick oxide film, 27... Gate electrode, 28... Gate oxide film, 29... Male seed region, 32... A/wiring,
36...Residual photoresist waist, 39...PEG exhibition pattern. Transfer agent Bensakashi Suzue Takehiko:′:

Claims (4)

【特許請求の範囲】[Claims] (1)  絶縁基砂上に第1の半導体膜及び1m酸化性
膜を順次被覆する工程と、これらの躾をパターニングし
て上面に耐酸化性膜パターンを有1する島状半導体膜を
形成する工程と、この島状半導体表の一1面もしくは@
面と露出した絶縁基数面に第2の半導体膜を残存させる
ニーと、残存した第2の半導体膜を酸化して前記島状半
導体膜の周囲に酸化膜を形成する工程とを具備したこと
を特徴とする半導体装置の製造方法。
(1) A step of sequentially coating the first semiconductor film and a 1 m oxidizing film on the insulating base sand, and a step of patterning these layers to form an island-shaped semiconductor film having an oxidation-resistant film pattern on the upper surface. And one side of this island-shaped semiconductor surface or @
a second semiconductor film remaining on the surface and the exposed insulating radix surface; and a step of oxidizing the remaining second semiconductor film to form an oxide film around the island-shaped semiconductor film. A method for manufacturing a featured semiconductor device.
(2)  島状半導体膜の側面もしくFi情面と露出し
た絶縁411!2表(3)に第2の半導体膜を残存させ
る1朽を、全面に第2の半導体膜を被覆した後この半導
体膜奢りアクティブイオンエツチングもしくはイオンビ
ームエツチングなど〇六方性エツチングを施すことによ
り行なうことを特徴とする特M虜求の範囲第1項記載の
半導体装置の製造方法。
(2) After covering the entire surface with the second semiconductor film, leave the second semiconductor film on the side surface of the island-shaped semiconductor film or the exposed insulation 411!2 table (3). A method for manufacturing a semiconductor device according to item 1, characterized in that the semiconductor film is etched by hexagonal etching such as active ion etching or ion beam etching.
(3)  島状半導体膜の側面と延出した絶縁基板表面
に第2の半導体膜を残存させる工程を、耐酸化性膜パタ
ーンを含む全面に第2の半導体−を被覆し、更に有機樹
脂膜を耐酸化性膜パターン上の領域が他の領域より膜厚
が薄くなるように豐布し、この有機樹脂膜を前記耐酸化
性℃パターンに対応する第2の半導体膜部分が延出する
まで除去した後、残存した有機樹脂膜をマスクとして第
2の半導体膜をエツチングすることにより行なうことを
特徴とする請求 製造方法。
(3) The step of leaving the second semiconductor film on the side surface of the island-shaped semiconductor film and the extended surface of the insulating substrate is performed by coating the entire surface including the oxidation-resistant film pattern with the second semiconductor, and then coating the second semiconductor film with an organic resin film. The area on the oxidation-resistant film pattern is thinner than other areas, and this organic resin film is applied until the second semiconductor film portion corresponding to the oxidation-resistant ℃ pattern extends. 1. A manufacturing method according to claim 1, wherein the second semiconductor film is etched using the remaining organic resin film as a mask after removal.
(4)  島状半導体膜の側面と延出した絶縁基板表面
に第2の半導体族を残存させる工程を、島状半導体膜の
耐酸化性腺パターン上に不純物含有被膜パターンを形成
し、この被膜パターンを含む全面に第2の半導体膜を被
覆し、熱処理を施して被膜パターン中の不純物を該パタ
ーン尚辺の第2の半導体膜に拡散させた壷不純物が拡散
さ扛た第2の半導体膜部分を選択的にエツチングするこ
とにより行なうことを特徴とする特IFF請求の軛囲第
1項記載の半導体装置の製造方法。
(4) The step of leaving the second semiconductor group on the side surface of the island-shaped semiconductor film and the extended surface of the insulating substrate is performed by forming an impurity-containing film pattern on the oxidation-resistant gland pattern of the island-like semiconductor film, and forming the film pattern A second semiconductor film portion in which the impurities have been diffused; A method for manufacturing a semiconductor device according to item 1 of the IFF claim, characterized in that the method is carried out by selectively etching.
JP6830682A 1982-04-23 1982-04-23 Manufacture of semiconductor device Pending JPS58184759A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6830682A JPS58184759A (en) 1982-04-23 1982-04-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6830682A JPS58184759A (en) 1982-04-23 1982-04-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58184759A true JPS58184759A (en) 1983-10-28

Family

ID=13369972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6830682A Pending JPS58184759A (en) 1982-04-23 1982-04-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58184759A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63237569A (en) * 1987-03-26 1988-10-04 Nec Corp Manufacture of mis type semiconductor device
JPS63237574A (en) * 1987-03-26 1988-10-04 Nec Corp Manufacture of mis semiconductor device
JPH02187069A (en) * 1988-11-10 1990-07-23 Texas Instr Inc <Ti> Transistor having radiation resistance and manufacture thereof
US5012311A (en) * 1986-02-07 1991-04-30 Fujitsu Limited Semiconductor thin film device with thick insulator at gate edge

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5012311A (en) * 1986-02-07 1991-04-30 Fujitsu Limited Semiconductor thin film device with thick insulator at gate edge
JPS63237569A (en) * 1987-03-26 1988-10-04 Nec Corp Manufacture of mis type semiconductor device
JPS63237574A (en) * 1987-03-26 1988-10-04 Nec Corp Manufacture of mis semiconductor device
JPH02187069A (en) * 1988-11-10 1990-07-23 Texas Instr Inc <Ti> Transistor having radiation resistance and manufacture thereof

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