JPH0878629A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0878629A JPH0878629A JP21440294A JP21440294A JPH0878629A JP H0878629 A JPH0878629 A JP H0878629A JP 21440294 A JP21440294 A JP 21440294A JP 21440294 A JP21440294 A JP 21440294A JP H0878629 A JPH0878629 A JP H0878629A
- Authority
- JP
- Japan
- Prior art keywords
- diode
- conductivity type
- substrate
- region
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000002344 surface layer Substances 0.000 claims abstract description 11
- 230000015556 catabolic process Effects 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 5
- 230000006378 damage Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】
【目的】Ｎ形基板に集積されたＩＣを静電破壊より保護
するため、基板内の二つのダイオードと基板上の抵抗と
により構成した保護回路で、マイナスサージ時に抵抗の
下の絶縁膜が絶縁破壊してＥＳＤ耐量が低下する問題を
解決する。
【構成】多結晶シリコン抵抗層直下のＮ基板表面層に、
ダイオードのＰ領域より高不純物濃度のＰウエルを形成
する。このＰウエルとＮ基板との間に形成されるダイオ
ードは、保護回路のダイオードより逆耐圧が高いので、
サージがこのダイオードへ抜けることがなく、抵抗と基
板の短絡が防止される。
(57) [Abstract] [Purpose] A protection circuit composed of two diodes in the board and a resistance on the board to protect the IC integrated on the N-type board from electrostatic damage. This solves the problem that the lower insulating film is dielectrically broken down and the ESD resistance is lowered. [Structure] The N substrate surface layer immediately below the polycrystalline silicon resistance layer,
A P well having a higher impurity concentration than the P region of the diode is formed. Since the diode formed between the P well and the N substrate has a higher reverse breakdown voltage than the diode of the protection circuit,
Surge does not escape to this diode and short circuit between resistor and substrate is prevented.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ダイオードおよび抵抗
よりなる入力端子の静電破壊 (ＥＤＳ) 保護回路を有す
る半導体集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having an input terminal electrostatic breakdown (EDS) protection circuit consisting of a diode and a resistor.
【０００２】[0002]
【従来の技術】Ｂ１−ＣＭＯＳ−ＩＣあるいはＣＭＯＳ
−ＩＣの入力保護回路として、図２に示すように、集積
回路２１の入力端子２２に対し、電源２３側およびＧＮ
Ｄ２４側にそれぞれダイオード２５、２６を接続し、さ
らにサージのパワーを軽減するための抵抗２７を回路２
１との間に挿入する。例えばＮ形基板を用いる場合、図
３に示すように、図３に示すように、基板１にＰ+ 領域
２を形成して第一ダイオード２５とし、Ｐウエル３とそ
の中にさらにＮ+ 領域４を形成して第二ダイオード２６
とする。抵抗２７は基板１の表面上の絶縁膜５の上の多
結晶シリコン層６により形成する。B1-CMOS-IC or CMOS
As an input protection circuit for the IC, as shown in FIG. 2, the power supply 23 side and the GN are connected to the input terminal 22 of the integrated circuit 21.
The diodes 25 and 26 are connected to the D24 side, respectively, and the resistor 27 for reducing the power of the surge is further connected to the circuit 2
Insert between 1 and. For example, when using the N-type substrate, as shown in FIG. 3, as shown in FIG. 3, a first diode 25 to form a P + region 2 in the substrate 1, further N + region therein and P well 3 Forming a second diode 26
And The resistor 27 is formed by the polycrystalline silicon layer 6 on the insulating film 5 on the surface of the substrate 1.
【０００３】[0003]
【発明が解決しようとする課題】図３に示す従来のＥＳ
Ｄ保護回路では、入力端子２２にプラスのサージが印加
されたときには、Ｎ基板１とＰ+ 領域２との間に形成さ
れる第一ダイオード２５が順方向になるため、この第一
ダイオードを通じて電流が流れ、サージが吸収される。
しかし、マイナスのサージが印加されたときには、印加
電圧はＰウエル３をＮ基板との間に形成される第三ダイ
オード２７ならびに第一ダイオード２５の逆耐圧以上と
なるため、Ｐウエル３とＮ+ 領域４との間に形成される
順方向の第二ダイオード２６の径路のほかに第一ダイオ
ード２５の径路により多少はサージが吸収される。その
一方、Ｎ基板１と多結晶シリコン層６との間に絶縁膜５
の図に符号７で示すような絶縁破壊がおき、入力端子２
２と基板１が短絡する破壊モードとなる。このため、プ
ラスサージ印加時にはＥＳＤ耐量は４００Ｖとなり、抵
抗が２７がオープン状態になるのに対し、マイナスサー
ジ印加時には−３００Ｖ程度で電源短絡状態になってし
まう。[Problems to be Solved by the Invention] The conventional ES shown in FIG.
In the D protection circuit, when a positive surge is applied to the input terminal 22, the first diode 25 formed between the N substrate 1 and the P + region 2 is in the forward direction, so that the current flows through this first diode. Flows and the surge is absorbed.
However, when a negative surge is applied, the applied voltage is equal to or larger than the reverse breakdown voltage of the third diode 27 and the first diode 25 is formed between the N substrate P well 3, P-well 3 and the N + Some surge is absorbed by the path of the first diode 25 in addition to the path of the second diode 26 in the forward direction formed between the area 4 and the region 4. On the other hand, the insulating film 5 is formed between the N substrate 1 and the polycrystalline silicon layer 6.
Of the input terminal 2
2 becomes a destruction mode in which the substrate 1 and the substrate 1 are short-circuited. Therefore, when the positive surge is applied, the ESD tolerance is 400 V, and the resistance 27 is open, whereas when the negative surge is applied, the power supply is short-circuited at about -300 V.
【０００４】本発明の目的は、上記の問題を解決し、サ
ージの極性に関係なく同等のＥＳＤ耐量を有する半導体
集積回路装置を提供することにある。An object of the present invention is to solve the above problems and to provide a semiconductor integrated circuit device having an equivalent ESD withstand level regardless of the polarity of surge.
【０００５】[0005]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、第一導電形の半導体基板に集積された
回路とその入力端子との間に、前記第一導電形の基板と
その表面層の第二導電形領域との間に形成される第一ダ
イオードと、前記基板の表面層の第二導電形領域とその
領域の表面層の第一導電形領域との間に形成される第二
ダイオードと、基板表面と絶縁膜を介する高抵抗率材料
層により形成される抵抗とよりなり、ダイオードの一つ
が電源側に、他のダイオードが大地側に接続される静電
破壊保護回路を有する半導体集積回路装置において、抵
抗を形成する高抵抗率材料層の直下の基板表面層に、第
一ダイオードの第二導電形領域より高不純物濃度の第二
導電形領域が設けられたものとする高抵抗率材料が多結
晶シリコンであることが良い。また第一導電形がＮ形、
第二導電形がＰ形であることが特に有効である。In order to achieve the above-mentioned object, the present invention provides a substrate of the first conductivity type between a circuit integrated on a semiconductor substrate of the first conductivity type and its input terminal. And a first diode formed between the second conductivity type region of the surface layer and the second conductivity type region of the surface layer of the substrate and the first conductivity type region of the surface layer of the region. Electrostatic discharge protection, in which one of the diodes is connected to the power supply side and the other diode is connected to the ground side. A semiconductor integrated circuit device having a circuit, in which a second conductivity type region having a higher impurity concentration than the second conductivity type region of the first diode is provided in a substrate surface layer immediately below a high resistivity material layer forming a resistance. The high resistivity material to be used is polycrystalline silicon Door is good. The first conductivity type is N type,
It is particularly effective that the second conductivity type is P type.
【０００６】[0006]
【作用】抵抗を形成する高抵抗率材料と基板の間の絶縁
膜が絶縁破壊しても、その直下に第二導電形領域が形成
されており、しかもその不純物濃度が第一ダイオードを
形成する第二導電形領域の不純物濃度より高いため、抵
抗直下のダイオードの方が第一ダイオードより逆耐圧が
高い。この抵抗直下のダイオードの領域は電位的に独立
しており、第一導電形の基板と第二導電形領域との間に
形成されるダイオードに対して逆方向のサージが印加さ
れた場合にも、サージは第一ダイオードおよび第二ダイ
オードから抜けていき、極性が反射のサージ印加時の同
等の静電破壊耐量になる。[Effect] Even if the insulating film between the high-resistivity material forming the resistor and the substrate undergoes dielectric breakdown, the second conductivity type region is formed immediately below the region and the impurity concentration thereof forms the first diode. Since the impurity concentration of the second conductivity type region is higher than that of the second conductivity type region, the diode directly below the resistance has a higher reverse breakdown voltage than the first diode. The region of the diode directly under the resistance is independent in terms of potential, and even when a reverse surge is applied to the diode formed between the substrate of the first conductivity type and the region of the second conductivity type. , The surge escapes from the first diode and the second diode, and has the same electrostatic breakdown withstanding capability when the surge with the polarity of reflection is applied.
【０００７】[0007]
【実施例】図１は本発明の一実施例の半導体集積回路装
置のＥＳＤ保護回路部を概念的に示し、図２、図３と共
通の部分には同一の符号が付されている。この場合は、
多結晶シリコン抵抗層６下の図示しない絶縁膜下のＮ基
板１の表面層に抵抗層６の直下部分をカバーするように
Ｐウエル８が形成されている。このＰウエル８の不純物
濃度はＰ+ 領域２の不純物濃度より高く、Ｐウエル８と
Ｎ基板１との間に形成されるダイオード２８の逆耐圧
は、第一ダイオード２５および第三ダイオード２７の逆
耐圧より高い。従って、入力端子２２にマイナスサージ
が印加されたときに、サージはダイオード２５およびダ
イオード２６から抜けていく。マイナスの高電圧が印加
された場合、最後には保護回路のダイオードが破壊する
が、もしくは抵抗がオープン状態になるか、サージが多
結晶シリコン抵抗層６直下に抜けることはなく、静電破
壊耐量はプラスサージの場合と同等に引き上げることが
できる。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 conceptually shows an ESD protection circuit portion of a semiconductor integrated circuit device according to an embodiment of the present invention, and portions common to FIGS. 2 and 3 are designated by the same reference numerals. in this case,
A P well 8 is formed in the surface layer of the N substrate 1 below the insulating film (not shown) under the polycrystalline silicon resistance layer 6 so as to cover the portion directly below the resistance layer 6. The impurity concentration of the P well 8 is higher than that of the P + region 2, and the reverse breakdown voltage of the diode 28 formed between the P well 8 and the N substrate 1 is the reverse of that of the first diode 25 and the third diode 27. Higher than pressure resistance. Therefore, when a negative surge is applied to the input terminal 22, the surge escapes from the diode 25 and the diode 26. When a negative high voltage is applied, the diode of the protection circuit is destroyed at the end, or the resistance does not open or the surge does not escape directly under the polycrystalline silicon resistance layer 6 and the electrostatic breakdown resistance Can be raised to the same level as for positive surges.
【０００８】[0008]
【発明の効果】本発明によれば、ダイオードと抵抗とか
らなる入力保護回路の抵抗直下の基板表面層に逆導電形
領域を形成することにより、抵抗直下の絶縁膜の絶縁破
壊により入力端子と基板が短絡されることがなくなり、
両極性のサージに対し、同等のＥＳＤ耐量をもつ保護回
路で保護された半導体集積回路装置を得ることができ
る。According to the present invention, the opposite conductivity type region is formed in the substrate surface layer directly below the resistance of the input protection circuit consisting of the diode and the resistor, so that the insulation film directly below the resistance causes the dielectric breakdown and the input terminal and The board is no longer shorted,
It is possible to obtain a semiconductor integrated circuit device protected by a protection circuit having an equivalent ESD withstand capability against bipolar surges.
【図１】本発明の一実施例の半導体集積回路装置におけ
るＥＳＤ保護回路部の概念的断面図FIG. 1 is a conceptual sectional view of an ESD protection circuit section in a semiconductor integrated circuit device according to an embodiment of the present invention.
【図２】ＥＳＤ保護回路の一例の回路図FIG. 2 is a circuit diagram of an example of an ESD protection circuit.
【図３】従来の半導体集積回路装置におけるＥＳＤ保護
回路部の概念的断面図FIG. 3 is a conceptual sectional view of an ESD protection circuit section in a conventional semiconductor integrated circuit device.
１ Ｎ基板 ２ Ｐ+ 領域 ３ Ｐウエル ４ Ｎ+ 領域 ６ 多結晶シリコン抵抗層 ２１ 集積回路 ２２ 入力端子 ２５ 第一ダイオード ２６ 第二ダイオードDESCRIPTION OF SYMBOLS 1 N substrate 2 P + area 3 P well 4 N + area 6 Polycrystalline silicon resistance layer 21 Integrated circuit 22 Input terminal 25 First diode 26 Second diode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 // Ｈ０１Ｌ 23/60 Ｈ０１Ｌ 27/06 ３１１ Ａ 23/56 Ｂ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location // H01L 23/60 H01L 27/06 311 A 23/56 B
Claims (3)
とその入力端子との間に、前記第一導電形の基板とその
表面層の第二導電形領域との間に形成された第一ダイオ
ードと、前記基板の表面層の第二導電形領域とその領域
の表面層の第一導電形領域との間に形成された第二ダイ
オードと、前記基板表面と絶縁膜を介する高抵抗率材料
層により形成される抵抗とよりなり、ダイオードの一つ
が電源側に、他のダイオードが大地側に接続される静電
破壊保護回路を有するものにおいて、抵抗を形成する高
抵抗率材料層の直下の基板表面層に、第一ダイオードの
第二導電形領域より高不純物濃度の第二導電形領域が設
けられたことを特徴とする半導体集積回路装置。1. A circuit formed on a semiconductor substrate of a first conductivity type and an input terminal thereof, and formed between the substrate of the first conductivity type and a second conductivity type region of a surface layer thereof. A first diode, a second diode formed between a second conductivity type region of the surface layer of the substrate and a first conductivity type region of the surface layer of the region, and a high resistance through the substrate surface and an insulating film. Of a high resistivity material layer that forms a resistor in an electrostatic breakdown protection circuit in which one of the diodes is connected to the power supply side and the other diode is connected to the ground side. 1. A semiconductor integrated circuit device, wherein a second conductivity type region having an impurity concentration higher than that of the second conductivity type region of the first diode is provided on a substrate surface layer immediately below.
項１記載の半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein the high resistivity material is polycrystalline silicon.
る請求項１あるいは２記載の半導体集積回路装置。3. The semiconductor integrated circuit device according to claim 1, wherein the first conductivity type is N type and the second conductivity type is P type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21440294A JPH0878629A (en) | 1994-09-08 | 1994-09-08 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21440294A JPH0878629A (en) | 1994-09-08 | 1994-09-08 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0878629A true JPH0878629A (en) | 1996-03-22 |
Family
ID=16655204
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21440294A Pending JPH0878629A (en) | 1994-09-08 | 1994-09-08 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0878629A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011046981A (en) * | 2009-08-25 | 2011-03-10 | Nisshin Steel Co Ltd | Method for manufacturing stainless steel sheet having excellent coating film adhesiveness |
| JP2012033933A (en) * | 2010-07-30 | 2012-02-16 | Semikron Elektronik Gmbh & Co Kg | Submodule and power semiconductor module |
| JP2012037637A (en) * | 2010-08-05 | 2012-02-23 | Seiko Epson Corp | Integrated circuit device, electro-optical device, and electronic appliance |
| CN106298872A (en) * | 2015-06-25 | 2017-01-04 | 北大方正集团有限公司 | A kind of power device knot terminal and preparation method thereof |
-
1994
- 1994-09-08 JP JP21440294A patent/JPH0878629A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011046981A (en) * | 2009-08-25 | 2011-03-10 | Nisshin Steel Co Ltd | Method for manufacturing stainless steel sheet having excellent coating film adhesiveness |
| JP2012033933A (en) * | 2010-07-30 | 2012-02-16 | Semikron Elektronik Gmbh & Co Kg | Submodule and power semiconductor module |
| JP2012037637A (en) * | 2010-08-05 | 2012-02-23 | Seiko Epson Corp | Integrated circuit device, electro-optical device, and electronic appliance |
| CN106298872A (en) * | 2015-06-25 | 2017-01-04 | 北大方正集团有限公司 | A kind of power device knot terminal and preparation method thereof |
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