JPH0878629A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To prevent short-circuit between an input terminal and a substrate due to a failure of an insulation film immediately below a resistor by forming a reverse conductive region on a surface layer of a substrate immediately below a resistor in an input protection circuit consisting of a diode and a resistor. CONSTITUTION: A P-well 8 is formed so as to cover a portion immediately below a resistance layer 6 on a surface layer of an N substrate 1 below the polycrystal silicon resistance layer 6. Impurity concentration of the P-well 8 is higher than the impurity concentration of P+ region 2, and the peak inverse voltage of a diode 28 formed between P-well 8 and N substrate 1 is higher than the peak inverse voltage between first and third diodes 25 and 27. Therefore, the surge is removed from the diodes 25 and 26 when a minus surge is applied to an input terminal 22. When a minus high voltage is applied, a diode in a protection circuit is finally destroyed, but the resistor is not opened and the surge does not fall down directly to the polycrystal silicon resistance layer 6, thereby preventing the short-circuit between the input terminal 22 and substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having an input terminal electrostatic breakdown (EDS) protection circuit consisting of a diode and a resistor.

[0002]

B1-CMOS-IC or CMOS
As an input protection circuit for the IC, as shown in FIG. 2, the power supply 23 side and the GN are connected to the input terminal 22 of the integrated circuit 21.
The diodes 25 and 26 are connected to the D24 side, respectively, and the resistor 27 for reducing the power of the surge is further connected to the circuit 2
Insert between 1 and. For example, when using the N-type substrate, as shown in FIG. 3, as shown in FIG. 3, a first diode 25 to form a P ⁺ region 2 in the substrate 1, further N ⁺ region therein and P well 3 Forming a second diode 26
And The resistor 27 is formed by the polycrystalline silicon layer 6 on the insulating film 5 on the surface of the substrate 1.

[0003]

[Problems to be Solved by the Invention] The conventional ES shown in FIG.
In the D protection circuit, when a positive surge is applied to the input terminal 22, the first diode 25 formed between the N substrate 1 and the P ⁺ region 2 is in the forward direction, so that the current flows through this first diode. Flows and the surge is absorbed.
However, when a negative surge is applied, the applied voltage is equal to or larger than the reverse breakdown voltage of the third diode 27 and the first diode 25 is formed between the N substrate P well 3, P-well 3 and the N ⁺ Some surge is absorbed by the path of the first diode 25 in addition to the path of the second diode 26 in the forward direction formed between the area 4 and the region 4. On the other hand, the insulating film 5 is formed between the N substrate 1 and the polycrystalline silicon layer 6.
Of the input terminal 2
2 becomes a destruction mode in which the substrate 1 and the substrate 1 are short-circuited. Therefore, when the positive surge is applied, the ESD tolerance is 400 V, and the resistance 27 is open, whereas when the negative surge is applied, the power supply is short-circuited at about -300 V.

An object of the present invention is to solve the above problems and to provide a semiconductor integrated circuit device having an equivalent ESD withstand level regardless of the polarity of surge.

[0005]

In order to achieve the above-mentioned object, the present invention provides a substrate of the first conductivity type between a circuit integrated on a semiconductor substrate of the first conductivity type and its input terminal. And a first diode formed between the second conductivity type region of the surface layer and the second conductivity type region of the surface layer of the substrate and the first conductivity type region of the surface layer of the region. Electrostatic discharge protection, in which one of the diodes is connected to the power supply side and the other diode is connected to the ground side. A semiconductor integrated circuit device having a circuit, in which a second conductivity type region having a higher impurity concentration than the second conductivity type region of the first diode is provided in a substrate surface layer immediately below a high resistivity material layer forming a resistance. The high resistivity material to be used is polycrystalline silicon Door is good. The first conductivity type is N type,
It is particularly effective that the second conductivity type is P type.

[0006]

[Effect] Even if the insulating film between the high-resistivity material forming the resistor and the substrate undergoes dielectric breakdown, the second conductivity type region is formed immediately below the region and the impurity concentration thereof forms the first diode. Since the impurity concentration of the second conductivity type region is higher than that of the second conductivity type region, the diode directly below the resistance has a higher reverse breakdown voltage than the first diode. The region of the diode directly under the resistance is independent in terms of potential, and even when a reverse surge is applied to the diode formed between the substrate of the first conductivity type and the region of the second conductivity type. , The surge escapes from the first diode and the second diode, and has the same electrostatic breakdown withstanding capability when the surge with the polarity of reflection is applied.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 conceptually shows an ESD protection circuit portion of a semiconductor integrated circuit device according to an embodiment of the present invention, and portions common to FIGS. 2 and 3 are designated by the same reference numerals. in this case,
A P well 8 is formed in the surface layer of the N substrate 1 below the insulating film (not shown) under the polycrystalline silicon resistance layer 6 so as to cover the portion directly below the resistance layer 6. The impurity concentration of the P well 8 is higher than that of the P ⁺ region 2, and the reverse breakdown voltage of the diode 28 formed between the P well 8 and the N substrate 1 is the reverse of that of the first diode 25 and the third diode 27. Higher than pressure resistance. Therefore, when a negative surge is applied to the input terminal 22, the surge escapes from the diode 25 and the diode 26. When a negative high voltage is applied, the diode of the protection circuit is destroyed at the end, or the resistance does not open or the surge does not escape directly under the polycrystalline silicon resistance layer 6 and the electrostatic breakdown resistance Can be raised to the same level as for positive surges.

[0008]

According to the present invention, the opposite conductivity type region is formed in the substrate surface layer directly below the resistance of the input protection circuit consisting of the diode and the resistor, so that the insulation film directly below the resistance causes the dielectric breakdown and the input terminal and The board is no longer shorted,
It is possible to obtain a semiconductor integrated circuit device protected by a protection circuit having an equivalent ESD withstand capability against bipolar surges.

[Brief description of drawings]

FIG. 1 is a conceptual sectional view of an ESD protection circuit section in a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of an ESD protection circuit.

FIG. 3 is a conceptual sectional view of an ESD protection circuit section in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N substrate 2 P ⁺ area 3 P well 4 N ⁺ area 6 Polycrystalline silicon resistance layer 21 Integrated circuit 22 Input terminal 25 First diode 26 Second diode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location // H01L 23/60 H01L 27/06 311 A 23/56 B

Claims (3)

[Claims] 1. A circuit formed on a semiconductor substrate of a first conductivity type and an input terminal thereof, and formed between the substrate of the first conductivity type and a second conductivity type region of a surface layer thereof. A first diode, a second diode formed between a second conductivity type region of the surface layer of the substrate and a first conductivity type region of the surface layer of the region, and a high resistance through the substrate surface and an insulating film. Of a high resistivity material layer that forms a resistor in an electrostatic breakdown protection circuit in which one of the diodes is connected to the power supply side and the other diode is connected to the ground side. 1. A semiconductor integrated circuit device, wherein a second conductivity type region having an impurity concentration higher than that of the second conductivity type region of the first diode is provided on a substrate surface layer immediately below. 2. The semiconductor integrated circuit device according to claim 1, wherein the high resistivity material is polycrystalline silicon. 3. The semiconductor integrated circuit device according to claim 1, wherein the first conductivity type is N type and the second conductivity type is P type.