JPH07302876A - Protective circuit against electrostatic breakdown - Google Patents
Protective circuit against electrostatic breakdownInfo
- Publication number
- JPH07302876A JPH07302876A JP9598794A JP9598794A JPH07302876A JP H07302876 A JPH07302876 A JP H07302876A JP 9598794 A JP9598794 A JP 9598794A JP 9598794 A JP9598794 A JP 9598794A JP H07302876 A JPH07302876 A JP H07302876A
- Authority
- JP
- Japan
- Prior art keywords
- zener diode
- circuit
- semiconductor substrate
- potential terminal
- electrostatic breakdown
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、静電荷の蓄積により生
ずる過電圧パルスに基づく破壊から内部回路を保護する
働きをする静電破壊保護回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic breakdown protection circuit which functions to protect an internal circuit from breakdown due to an overvoltage pulse generated by accumulation of electrostatic charges.
【0002】[0002]
【従来の技術】MOSLSIあるいはMOSVSIなど
のMOS集積回路においては、トランジスタの駆動能力
の低下を避けるためには、大規模な保護回路は入れられ
ない。そのため、たまった静電荷によるトランジスタの
定格電圧を越えるような過大電圧パルスに対して逃げ道
となる迂回路を提供する必要がある。図2は、かかる状
況を満たすための保護回路を示す。すなわち、MOSト
ランジスタ11、12を含む内部回路10の内部電位端
子1と入力電位端子2との間に抵抗21が挿入され、こ
の抵抗により入力電位端子2に入った過大電圧パルスが
内部回路1に伝播するのを遅らせる。その間に電荷をM
OSトランジスタ22を通して逃がす。さらにトランジ
スタ22で吸収しきれなかったパルスをMOSトランジ
スタ23で逃がすという作用で内部回路の静電破壊の保
護をしている。MOSトランジスタ22は、静電荷によ
る過電圧を逃がす機能のほかに、入力端子2から内部電
位端子1に流れる電流を定電流にするための機能をも
つ。このMOSトランジスタ22、MOSトランジスタ
23の代わりに、それぞれ半導体基体内に集積された同
一のツエナ電圧をもつツェナダイオードを用い、そのツ
エナ電圧を超える過大電圧パルスを逃がすこともでき
る。2. Description of the Related Art In a MOS integrated circuit such as MOSLSI or MOSVSI, a large-scale protection circuit cannot be provided in order to avoid deterioration of the driving capability of transistors. Therefore, it is necessary to provide a detour path that serves as an escape route for an excessive voltage pulse that exceeds the rated voltage of the transistor due to accumulated electrostatic charges. FIG. 2 shows a protection circuit for satisfying such a situation. That is, the resistor 21 is inserted between the internal potential terminal 1 and the input potential terminal 2 of the internal circuit 10 including the MOS transistors 11 and 12, and the excessive voltage pulse that has entered the input potential terminal 2 is applied to the internal circuit 1 by this resistor. Delay the propagation. In the meantime, charge M
It escapes through the OS transistor 22. Further, the MOS transistor 23 allows the pulse which could not be absorbed by the transistor 22 to escape, thereby protecting the internal circuit from electrostatic breakdown. The MOS transistor 22 has a function of making the current flowing from the input terminal 2 to the internal potential terminal 1 a constant current, in addition to the function of releasing an overvoltage due to electrostatic charge. Instead of the MOS transistor 22 and the MOS transistor 23, a Zener diode having the same Zener voltage integrated in the semiconductor substrate may be used to release an overvoltage pulse exceeding the Zener voltage.
【0003】[0003]
【発明が解決しようとする課題】しかし、図2のような
保護回路を設けても、なお静電破壊が起こることがあ
る。本発明の目的は、この問題を解決し、さらに静電破
壊耐量を向上させることができるが、チップを大きくす
ることのない静電破壊保護回路を提供することにある。However, even if the protection circuit as shown in FIG. 2 is provided, electrostatic breakdown may still occur. An object of the present invention is to provide an electrostatic breakdown protection circuit which can solve this problem and further improve the electrostatic breakdown withstand capability, but does not increase the size of the chip.
【0004】[0004]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の静電破壊保護回路は、入力電位端子と内
部回路電位端子とを接続する回路とアースとの間に、半
導体基体内に集積されたツエナダイオードを含む過電圧
吸収回路と、半導体基体上に絶縁膜を介して形成された
ツエナダイオードを含む過電圧吸収回路が並列に接続さ
れたものとする。半導体基体内のツエナダイオードは一
方向のみのツエナダイオードであり、半導体基体上のツ
エナダイオードはそれぞれ複数の双方向のツエナダイオ
ードが交互に直列に接続されたものであることが有効で
ある。半導体基体上のツエナダイオードが、基体上に絶
縁膜を介して形成した多結晶シリコンのp領域とn領域
とを交互に隣接させてなることが良い。In order to achieve the above object, an electrostatic breakdown protection circuit of the present invention comprises a semiconductor substrate between a circuit connecting an input potential terminal and an internal circuit potential terminal and a ground. It is assumed that an overvoltage absorption circuit including a Zener diode integrated in the body and an overvoltage absorption circuit including a Zener diode formed on a semiconductor substrate via an insulating film are connected in parallel. It is effective that the zener diode in the semiconductor substrate is a zener diode in only one direction, and the zener diode on the semiconductor substrate is a plurality of bidirectional zener diodes alternately connected in series. It is preferable that the Zener diode on the semiconductor substrate has alternating p and n regions of polycrystalline silicon formed on the substrate via an insulating film.
【0005】[0005]
【作用】図1は本発明の保護回路を示し、図2と共通の
部分には同一の符号が付されている。内部電位端子1と
入力電位端子2とを接続する回路には、従来の保護回路
同様に抵抗21をはさんで静電荷による過大電圧パルス
を地電位へ逃がす回路が設けられるが、抵抗21の前段
には、半導体基体に拡散によって形成されたツエナダイ
オード3からなる回路と、半導体基体上に絶縁膜を介し
て形成される双方向の複数のツエナダイオード4を直列
接続した回路が並列に設けられている。双方向のツエナ
ダイオードを直列接続することにより、一方の方向のツ
エナダイオードに高い逆電圧が印加されたときに順方向
のツエナダイオードで電圧降下が生ずるため、破壊しに
くくなる。このように二つの過大電圧パルス吸収回路が
並列に接続されていることにより、電荷は分割して吸収
され、一方の吸収回路が破壊しても他方が働くため、信
頼性が高くなる。そして、一方を基体上、他方を基体内
に形成することにより、基体寸法を大きくすることがな
い。FIG. 1 shows a protection circuit of the present invention, and the same parts as those in FIG. 2 are designated by the same reference numerals. A circuit for connecting the internal potential terminal 1 and the input potential terminal 2 is provided with a circuit for escaping an excessive voltage pulse due to electrostatic charge to the ground potential across the resistor 21 like the conventional protection circuit. Is provided in parallel with a circuit including a Zener diode 3 formed by diffusion on a semiconductor substrate and a circuit in which a plurality of bidirectional Zener diodes 4 formed on the semiconductor substrate via an insulating film are connected in series. There is. By connecting the bidirectional Zener diodes in series, a voltage drop occurs in the forward Zener diode when a high reverse voltage is applied to the Zener diode in one direction, so that the Zener diode is not easily destroyed. Since the two overvoltage pulse absorption circuits are connected in parallel in this manner, the charge is divided and absorbed, and even if one of the absorption circuits is broken, the other works, so that the reliability is increased. By forming one on the base and the other in the base, the size of the base is not increased.
【0006】[0006]
【実施例】図3は、本発明の一実施例の保護回路、すな
わち静電破壊耐量向上回路5を用いた回路を示し、図
1、図2と共通の部分には同一の符号が付されている。
ツエナダイオード3およびツエナダイオード23は、シ
リコンチップ内に拡散により不純物を導入して形成した
もので40Vのツエナ電圧を持つが、ツエナダイオード
4は、シリコンチップ上に酸化膜を介して形成した多結
晶シリコン層に2種類の不純物を導入してp領域とn領
域を交互に基板面に平行な面内に隣接して形成すること
により、複数の双方向のツエナダイオードを交互に直列
接続させたものである。基体上にツエナダイオードのた
めの多結晶シリコン層は、パッド部の下に形成するの
で、チップ面積は大きくならない。この回路5を、電源
電圧端子6に接続されたデプレッション型NチャネルM
OSFET7よりなる定電流回路と、抵抗8とコンデン
サ9よりなるフィルタ回路との接続点に接続することに
より、入力電位端子2と内部電位端子1の間にフィルタ
回路を介して接続される。これにより、入力電位端子2
に静電気が蓄積されることにより入る過大電圧のパルス
は、抵抗21の作用により内部回路への伝播を遅らせ、
その間に電荷が拡散ツエナダイオード3および多結晶シ
リコンツエナダイオード4に分割され、高い耐量を維持
させている。これらのツエナダイオードで吸収されなか
ったパルスは、拡散ツエナダイオード23でアースへ逃
がす仕組みとなっている。FIG. 3 shows a protection circuit according to an embodiment of the present invention, that is, a circuit using an electrostatic breakdown withstand voltage improving circuit 5. The same parts as those in FIGS. 1 and 2 are designated by the same reference numerals. ing.
The Zener diode 3 and the Zener diode 23 are formed by introducing impurities into a silicon chip by diffusion and have a Zener voltage of 40 V. The Zener diode 4 is a polycrystal formed on a silicon chip via an oxide film. A plurality of bidirectional Zener diodes are alternately connected in series by introducing two kinds of impurities into a silicon layer to alternately form p regions and n regions in a plane parallel to the substrate surface. Is. Since the polycrystalline silicon layer for the Zener diode is formed under the pad portion on the substrate, the chip area is not increased. This circuit 5 is connected to the power supply voltage terminal 6 and is a depletion type N channel M
By connecting to the connection point of the constant current circuit composed of the OSFET 7 and the filter circuit composed of the resistor 8 and the capacitor 9, the input potential terminal 2 and the internal potential terminal 1 are connected via the filter circuit. As a result, the input potential terminal 2
An excessive voltage pulse that is generated due to the accumulation of static electricity in the circuit delays the propagation to the internal circuit due to the action of the resistor 21,
During that time, the electric charge is divided into the diffusion Zener diode 3 and the polycrystalline silicon Zener diode 4 to maintain a high withstand voltage. The pulse which is not absorbed by these Zener diodes is escaped to the ground by the diffusion Zener diode 23.
【0007】[0007]
【発明の効果】本発明によれば、基板内のツエナダイオ
ードからなる過電圧吸収回路と基板上のツエナダイオー
ドからなる過電圧吸収回路を並列に組み込むことによ
り、静電破壊耐量が向上するが、半導体基板面積を大き
くすることがない。According to the present invention, the electrostatic breakdown withstand capability is improved by incorporating an overvoltage absorption circuit composed of a zener diode in the substrate and an overvoltage absorption circuit composed of a zener diode on the substrate in parallel. Does not increase the area.
【図1】本発明の実施例の静電破壊保護回路の基本的構
成を示す回路図FIG. 1 is a circuit diagram showing a basic configuration of an electrostatic breakdown protection circuit according to an embodiment of the present invention.
【図2】従来の静電破壊保護回路の回路図FIG. 2 is a circuit diagram of a conventional electrostatic breakdown protection circuit.
【図3】本発明の実施例の静電破壊保護回路の使用例を
示す回路図FIG. 3 is a circuit diagram showing a usage example of an electrostatic breakdown protection circuit according to an embodiment of the present invention.
1 内部電位端子 2 入力電位端子 3 基板内ツエナダイオード 4 基板上ツエナダイオード 5 静電破壊耐量向上回路 1 Internal potential terminal 2 Input potential terminal 3 In-board Zener diode 4 On-board Zener diode 5 Electrostatic breakdown withstanding circuit
Claims (3)
する回路とアースとの間に、半導体基体内に集積された
ツエナダイオードを含む過電圧吸収回路と、半導体基体
上に絶縁膜を介して形成されたツエナダイオードを含む
過電圧吸収回路が並列に接続されたことを特徴とする静
電破壊保護回路。1. An overvoltage absorption circuit including a Zener diode integrated in a semiconductor substrate between a circuit connecting an input potential terminal and an internal circuit potential terminal and a ground, and an insulating film on the semiconductor substrate. An electrostatic breakdown protection circuit characterized in that an overvoltage absorption circuit including a formed Zener diode is connected in parallel.
のみのツエナダイオードであり、半導体基体上のツエナ
ダイオードはそれぞれ複数の双方向のツエナダイオード
が交互に直列に接続されたものである請求項1記載の静
電破壊保護回路。2. The zener diode in the semiconductor substrate is a zener diode in only one direction, and the zener diode on the semiconductor substrate is formed by alternately connecting a plurality of bidirectional zener diodes in series. The electrostatic discharge protection circuit described.
上に絶縁膜を介して形成した多結晶シリコンのp領域と
n領域とを交互に隣接させてなる請求項2記載の静電破
壊保護回路。3. The electrostatic breakdown protection circuit according to claim 2, wherein the Zener diode on the semiconductor substrate comprises alternating p and n regions of polycrystalline silicon formed on the substrate via an insulating film. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9598794A JPH07302876A (en) | 1994-05-10 | 1994-05-10 | Protective circuit against electrostatic breakdown |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9598794A JPH07302876A (en) | 1994-05-10 | 1994-05-10 | Protective circuit against electrostatic breakdown |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07302876A true JPH07302876A (en) | 1995-11-14 |
Family
ID=14152492
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9598794A Pending JPH07302876A (en) | 1994-05-10 | 1994-05-10 | Protective circuit against electrostatic breakdown |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07302876A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998010457A1 (en) * | 1996-09-04 | 1998-03-12 | Micron Technology,Inc. | Matrix addressable display with electrostatic discharge protection |
DE19903028B4 (en) * | 1998-01-27 | 2006-12-21 | Fuji Electric Co., Ltd., Kawasaki | MOS semiconductor device |
JP2017017092A (en) * | 2015-06-29 | 2017-01-19 | アンリツ株式会社 | ESD protection circuit |
-
1994
- 1994-05-10 JP JP9598794A patent/JPH07302876A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998010457A1 (en) * | 1996-09-04 | 1998-03-12 | Micron Technology,Inc. | Matrix addressable display with electrostatic discharge protection |
US5844370A (en) * | 1996-09-04 | 1998-12-01 | Micron Technology, Inc. | Matrix addressable display with electrostatic discharge protection |
US6266034B1 (en) | 1996-09-04 | 2001-07-24 | Micron Technology, Inc. | Matrix addressable display with electrostatic discharge protection |
US6356250B1 (en) | 1996-09-04 | 2002-03-12 | Micron Technology, Inc. | Matrix addressable display with electrostatic discharge protection |
DE19903028B4 (en) * | 1998-01-27 | 2006-12-21 | Fuji Electric Co., Ltd., Kawasaki | MOS semiconductor device |
JP2017017092A (en) * | 2015-06-29 | 2017-01-19 | アンリツ株式会社 | ESD protection circuit |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5159518A (en) | Input protection circuit for CMOS devices | |
US5077591A (en) | Electrostatic discharge protection for semiconductor input devices | |
JP3009614B2 (en) | Electrostatic discharge protection circuit for integrated circuits, electrostatic discharge protection device, and method for protecting against electrostatic discharge | |
US5615073A (en) | Electrostatic discharge protection apparatus | |
US5166089A (en) | Method of making electrostatic discharge protection for semiconductor input devices | |
CA2177150A1 (en) | Electrostatic discharge protection circuit | |
US20080013233A1 (en) | Electrostatic breakdown protection circuit | |
US20040207020A1 (en) | CMOS silicon-control-rectifier (SCR) structure for electrostatic discharge (ESD) protection | |
JPS6248901B2 (en) | ||
JPH0666402B2 (en) | Input protection circuit for semiconductor integrated circuit device | |
US5945714A (en) | Lateral silicon-controlled rectifier for electrostatic discharge protection | |
US4972247A (en) | High energy event protection for semiconductor devices | |
KR960009159A (en) | Semiconductor devices | |
JP2906749B2 (en) | Gate protection device for semiconductor device | |
JPH07302876A (en) | Protective circuit against electrostatic breakdown | |
US6288884B1 (en) | MOS buffer immun to ESD damage | |
JPH06236965A (en) | Semiconductor device | |
JPH07263633A (en) | Static electricity-proof discharge protector of semiconductor device | |
EP0903828A1 (en) | Improved device for the protection of an integrated circuit against electrostatic discharges | |
JPS5834958A (en) | Input protection device | |
JPS5815277A (en) | Input protecting circuit | |
JPH10223843A (en) | Protective circuit of semiconductor device | |
JPS60115253A (en) | Semiconductor integrated circuit device | |
JPS59104171A (en) | Semiconductor device | |
JPH0878629A (en) | Semiconductor integrated circuit device |