JPS6248901B2 - - Google Patents
Info
- Publication number
- JPS6248901B2 JPS6248901B2 JP54019836A JP1983679A JPS6248901B2 JP S6248901 B2 JPS6248901 B2 JP S6248901B2 JP 54019836 A JP54019836 A JP 54019836A JP 1983679 A JP1983679 A JP 1983679A JP S6248901 B2 JPS6248901 B2 JP S6248901B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- terminal
- conductivity type
- integrated circuit
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 36
- 230000002265 prevention Effects 0.000 claims description 28
- 230000015556 catabolic process Effects 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 8
- 230000006378 damage Effects 0.000 description 15
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
この発明は静電破壊防止素子に関し、主として
半導体集積回路における静電破壊を防止するため
の保護装置を対象とする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrostatic damage prevention element, and is primarily directed to a protection device for preventing electrostatic damage in a semiconductor integrated circuit.
半導体集積回路（IC）の静電破壊を防止する
手段として、従来より第１図ａに示すように入力
側に内部回路と直列に抵抗Ｒを接続し、浮遊容量
Ｃと抵抗の時定数によりサージパルスの波形を滑
らかにし急激なサージパルスが内部回路１０に入
らないようにする方法、又は第１図ｂに示すよう
に内部回路の入力側に並列にサージパルスで降伏
するダイオードＤを接続することによりサージパ
ルスを吸収する方法がある。 As a means of preventing electrostatic damage in semiconductor integrated circuits (ICs), a resistor R is conventionally connected in series with the internal circuit on the input side as shown in Figure 1a, and surges are prevented by the stray capacitance C and the time constant of the resistor. A method of smoothing the pulse waveform to prevent sudden surge pulses from entering the internal circuit 10, or connecting a diode D that breaks down at surge pulses in parallel to the input side of the internal circuit as shown in Figure 1b. There is a method to absorb surge pulses.
しかしこれらの手段における抵抗やダイオード
を半導体基体内のpn接合で形成した場合、逆方
向に大きいサージパルス電圧でそれ自体が破壊さ
れることになり、例えば100V以上の耐圧を有す
るICには適用できない。 However, if the resistor or diode in these methods is formed by a p-n junction within the semiconductor substrate, it will be destroyed by a large surge pulse voltage in the opposite direction, so it cannot be applied to ICs with a withstand voltage of 100 V or more, for example. .
そこで静電破壊電圧レベルを向上させた他の手
段としてバイポーラICにおけるトランジスタを
利用したものが本願出願人により前に提案されて
いる。これは第２図，第２Ａ図に示すように、ｐ
型シリコン半導体基板１上に形成されたｎエピタ
キシヤル層２の表面にベース拡散層を利用した
n+抵抗５とを形成し、抵抗の一端に設けた電極
７を端子（パツド）８に接続するとともに、n+
抵抗の他端でｐ領域のpn接合の一部を電極９に
より短絡し、この電極を内部回路１０に接続した
もので、入力又は出力端子８を介して上記電極と
半導体基体の間にサージパルス電圧が加わつた場
合に上記n+埋込層、ｐ領域及びn+抵抗の一部が
トランジスタ（サイリスタ）として動作しサージ
パルスを吸収するように構成されたものである。 Therefore, as another means for improving the electrostatic breakdown voltage level, the applicant has previously proposed a method using transistors in a bipolar IC. As shown in Figures 2 and 2A, this means that p
A base diffusion layer is used on the surface of an n epitaxial layer 2 formed on a type silicon semiconductor substrate 1.
An electrode 7 provided at one end of the resistor is connected to a terminal (pad) 8, and an n + resistor 5 is formed.
At the other end of the resistor, a part of the pn junction in the p region is short-circuited by an electrode 9, and this electrode is connected to an internal circuit 10, and a surge pulse is generated between the electrode and the semiconductor substrate via the input or output terminal 8. When a voltage is applied, the n + buried layer, p region, and part of the n + resistor operate as a transistor (thyristor) to absorb surge pulses.
このような静電破壊防止素子においては、通常
の場合、信号はパツド８からn+抵抗５中を通
り、電極９を経て回路の入力側１０へ送られる。
ところで例えば逆方向（負極性）サージパルスが
端子から入りこんだ場合、サージ電流がn+抵抗
５を通る際に電圧降下を生じ同じn+層５で場所
により電位が異なるのに対し、ｐ領域３の電位は
n+層の最高電位と等しいマイナス電位となる。
そのことから電極７の近傍におけるn+層５とｐ
層３との間のpn接合部に順方向バイアスが加わ
る。同時に上記サージパルスによりｎエピタキシ
ヤル層２とｐ層との間に逆方向バイアスが加わ
る。負極性サージパルスが加わたことにより発生
する上記バイアス電圧により破壊防止素子が電極
７近傍のpn接合でn+層５をエミツタとするnpnト
ランジスタT1として動作することになり、これ
にｐ層３，n+埋込層６及びp-基板１とで構成さ
れるpnpトランジスタT2動作が結合してサイリス
タとして動作し、同図の矢印Ａのように電流が流
れこれによつてサージパルスを吸収でき、入力回
路１０にサージが入ることがない。この場合pn
接合の降伏にもとづく保護動作を伴わないので破
壊防止素子自体が破壊されることがない。 In such an electrostatic breakdown protection element, the signal is normally passed from the pad 8 through the n + resistor 5 and sent via the electrode 9 to the input side 10 of the circuit.
By the way, for example, when a reverse direction (negative polarity) surge pulse enters from the terminal, a voltage drop occurs when the surge current passes through the n + resistor 5, and the potential differs depending on the location in the same n + layer 5, whereas the p-region 3 The potential of
It becomes a negative potential equal to the highest potential of the n + layer.
Therefore, the n + layer 5 and the p layer near the electrode 7
The pn junction with layer 3 is forward biased. At the same time, the surge pulse applies a reverse bias between the n epitaxial layer 2 and the p layer. Due to the bias voltage generated by applying the negative surge pulse, the breakdown prevention element operates as an npn transistor T1 with the n + layer 5 as an emitter at the pn junction near the electrode 7, and the p-layer 3 , n + buried layer 6 and p - substrate 1 combine to operate as a thyristor, and a current flows as shown by arrow A in the figure, thereby absorbing surge pulses. This prevents surges from entering the input circuit 10. In this case pn
Since there is no protective action based on bond breakdown, the destruction prevention element itself will not be destroyed.
同様に順方向サージパルスが端子から入りこん
だ場合にも抵抗において電圧降下し、電極７近傍
のpn接合にこの場合逆方向バイアスが加わり、
一方ｎエピタキシヤル層とｐ層との間に順方向バ
イアスが加わる。したがつて電極７近傍でこの場
合はｎエピタキシヤル層をエミツタとするnpnト
ランジスタとして動作し、サージパルスを吸収す
る。 Similarly, when a forward surge pulse enters from the terminal, a voltage drop occurs across the resistor, and a reverse bias is applied to the pn junction near electrode 7.
On the other hand, a forward bias is applied between the n epitaxial layer and the p layer. Therefore, in this case, near the electrode 7, it operates as an npn transistor with the n epitaxial layer as an emitter, and absorbs surge pulses.
しかしながらこのような静電破壊防止素子にお
いてはその内部抵抗によりその動作開始の電流が
決まるために対グランド，対ＶCCの内部インピー
ダンスが高く、電流の流れにくい個所に対応する
端子に接続された静電破壊防止素子にあつては内
部抵抗を高くする必要がある。すなわち電流が流
れにくい個所では高電圧のために回路の途中でブ
レークダウンを起こすことになる。このように電
流の流れにくい個所によつて適切な抵抗値をもつ
破壊防止素子をつくることは設計上困難である。 However, in such an electrostatic discharge prevention device, the current at which it starts operating is determined by its internal resistance, so the internal impedance to ground and to V CC is high, and the static In the case of an electric breakdown prevention element, it is necessary to increase the internal resistance. In other words, in places where it is difficult for current to flow, the high voltage will cause a breakdown in the middle of the circuit. In this way, it is difficult to create a destruction prevention element with an appropriate resistance value due to the locations where it is difficult for current to flow.
本発明は上記した点を考慮してなされたもので
あり、その一つの目的は前に提起した静電破壊防
止素子が動作しにくい個所でも動作ができ、破壊
レベルの向上を図ることであり、他の目的は一つ
の半導体チツプ内に入力端子の電流の流れの状況
に応じて適切な静電破壊防止素子をそなえた半導
体装置を提供することにある。 The present invention has been made in consideration of the above-mentioned points, and one of its purposes is to improve the level of damage by allowing it to operate even in locations where it is difficult for the electrostatic damage prevention element proposed above to work. Another object of the present invention is to provide a semiconductor device in which a single semiconductor chip is provided with an appropriate electrostatic breakdown prevention element depending on the state of current flow at an input terminal.
上記目的を達するためのこの発明の一つの実施
形態は、例えば第３図，第３Ａ図に示すように、
p-型半導体基体１上にn-エピタキシヤル層２を
形成し、このn-層２をｐアイソレーシヨン層１
１とのpn接合により他領域と電気的に分離する
とともに、このn-層２の表面にベース拡散によ
りｐ領域３を形成し、このｐ領域表面にエミツタ
拡散によるn+領域４を形成してこのn+領域表面
に形成した電極１２を端子（パツド）８及び内部
回路１０に接続して成り、入力端子を介して上記
電極１２下の半導体領域にサージパルス電圧が加
わつた状態でこの半導体領域がサイリスタの一部
として動作しサージパルスを吸収するようにした
ものである。 One embodiment of the present invention for achieving the above object is, for example, as shown in FIGS. 3 and 3A,
An n - epitaxial layer 2 is formed on a p - type semiconductor substrate 1, and this n - layer 2 is used as a p isolation layer 1.
It is electrically isolated from other regions by a pn junction with 1, and a p region 3 is formed on the surface of this n - layer 2 by base diffusion, and an n + region 4 is formed on the surface of this p region by emitter diffusion. An electrode 12 formed on the surface of this n + region is connected to a terminal (pad) 8 and an internal circuit 10, and when a surge pulse voltage is applied to the semiconductor region under the electrode 12 via the input terminal, the semiconductor region operates as part of a thyristor to absorb surge pulses.
このような静電破壊防止素子において、パツド
に対し逆方向（負極性）のサージパルスが入りこ
んだ場合、同図に示すようにp+基板１，n+埋込
層６を含むn-エピタキシヤル層２，ベース拡散
ｐ領域３及びエミツタ拡散n+領域４とサイリス
タが構成され、基板１と入力端子８との間が導通
して矢印Ｂ方向に電流が流れ、破壊を防止する。
このような破壊防止動作は従来の抵抗を具えた静
電破壊防止素子（第２図）と同様であるが、抵抗
がないために電流制限がなく、前に提起した防止
素子が動作しにくく、電流の流れにくい回路に接
続された場合でもオン動作し、静電破壊防止レベ
ルを向上できる本願発明者の実験によれば、例え
ば破壊防止素子に抵抗を入れた場合400Vで破壊
された個所で抵抗を入れない本発明による破壊防
止素子を使用した場合1000Vまで耐えることが確
認された。 In such an electrostatic breakdown prevention element, when a surge pulse in the opposite direction (negative polarity) enters the pad, the n - epitaxial layer including the p + substrate 1 and the n + buried layer 6 is damaged as shown in the figure. A thyristor is constituted by the layer 2, the base diffusion p region 3, and the emitter diffusion n + region 4, and conduction occurs between the substrate 1 and the input terminal 8, and a current flows in the direction of arrow B, thereby preventing destruction.
This type of destruction prevention operation is similar to that of a conventional electrostatic damage prevention element equipped with a resistor (Figure 2), but since there is no resistance, there is no current limit, and the previously proposed prevention element is difficult to operate. It turns on even when connected to a circuit where current does not flow easily, improving the electrostatic damage prevention level.According to the inventor's experiments, for example, if a resistor is inserted into the destruction prevention element, the resistance will be removed at the point destroyed by 400V. It was confirmed that when using the anti-destruction element according to the present invention, which does not contain voltage, it can withstand up to 1000V.
本発明の他の実施形態は、第４図を参照し、一
つの半導体基体（チツプ）１３上にIC内部回路
１０を形成し、１つの端子１４に対して静電破壊
防止素子１５を接続し、他の入力端子１６に対し
静電破壊防止素子１７を接続する。このうち入力
端子に対応する回路は内部インピーダンスが高く
電流が流れにくいものとする。各静電破壊防止素
子はnpn素子すなわちサイリスタをもつて示す。
電流の流れ易い回路に対応する入力端子１４の静
電破壊防止素子１５にあつては、入力端子側の
pn接合の少なくとも一部を短絡するとともに端
子１４と内部回路１０との間に抵抗Ｒを介在させ
たもので、すなわち、既述の第２図，第２Ａ図に
対応するものである。又、電流の流れにくい回路
に対応する入力端子１６の静電破壊防止素子１６
にあつては、pn接合を短絡することなく、入力
端子と内部回路とは直結されており、又抵抗を有
しないもので、すなわち既述の第３図，第３Ａ図
に対応するものである。 In another embodiment of the present invention, referring to FIG. 4, an IC internal circuit 10 is formed on one semiconductor substrate (chip) 13, and an electrostatic breakdown prevention element 15 is connected to one terminal 14. , the electrostatic breakdown prevention element 17 is connected to the other input terminal 16. Among these circuits, the circuit corresponding to the input terminal has a high internal impedance and it is difficult for current to flow therein. Each electrostatic breakdown prevention element is shown with an npn element, ie, a thyristor.
For the electrostatic breakdown prevention element 15 of the input terminal 14 that corresponds to a circuit where current easily flows, the input terminal side
At least a part of the pn junction is short-circuited and a resistor R is interposed between the terminal 14 and the internal circuit 10, that is, it corresponds to the previously described FIGS. 2 and 2A. In addition, the electrostatic damage prevention element 16 of the input terminal 16 corresponding to a circuit in which current does not easily flow
In this case, the input terminal and the internal circuit are directly connected without shorting the pn junction, and there is no resistance, that is, it corresponds to the above-mentioned Figures 3 and 3A. .
以上述べた本発明によれば、抵抗を有しない静
電防止素子にあつては電流制限を考慮することな
く素子の設計が容易であり、このような素子と従
来の抵抗を有する素子とを組合せることによつ
て、複雑な電流系路を有する集積回路であつても
これに対応し、静電破壊防止レベルを向上するこ
とができる。 According to the present invention described above, it is easy to design an antistatic element without resistance without considering current limitation, and it is possible to combine such an element with a conventional element having resistance. By doing so, it is possible to cope with even an integrated circuit having a complicated current path, and to improve the level of prevention of electrostatic damage.
第１図ａ，ｂは従来の一般的静電破壊手段を示
す回路図、第２図は本願出願人により前に提起さ
れた静電破壊防止素子の構造を示す平面図、第２
Ａ図は第２図のＡ−Ａ視断面図である。第３図は
本発明による静電破壊防止素子の平面図、第３Ａ
図は第３図のＡ−Ａ視断面図である。第４図は一
つの半導体チツプ上に異なる静電破壊防止素子を
配置する本発明の他の実施例を示す説明図であ
る。
１……p-半導体基体、２……n-エピタキシヤ
ル半導体層、３……ｐ半導体領域、４……n+半
導体領域、５……n+半導体領域（抵抗）、６……
n+埋込層、７……端子側電極、８……端子（パ
ツド）、９……内部回路側電極、１０……内部回
路、１１…ｐアイソレーシヨン層、１２……電
極、１３……半導体チツプ、１４……端子、１５
……静電破壊防止素子、１６……端子、１７……
静電破壊防止素子。
Figures 1a and b are circuit diagrams showing conventional general electrostatic breakdown means, Figure 2 is a plan view showing the structure of an electrostatic breakdown prevention element previously proposed by the applicant;
FIG. A is a sectional view taken along the line AA in FIG. 2. Fig. 3 is a plan view of the electrostatic breakdown prevention element according to the present invention, Fig. 3A.
The figure is a sectional view taken along the line AA in FIG. 3. FIG. 4 is an explanatory diagram showing another embodiment of the present invention in which different electrostatic breakdown prevention elements are arranged on one semiconductor chip. 1... p - semiconductor substrate, 2... n - epitaxial semiconductor layer, 3... p semiconductor region, 4... n + semiconductor region, 5... n + semiconductor region (resistance), 6...
n + buried layer, 7... terminal side electrode, 8... terminal (pad), 9... internal circuit side electrode, 10... internal circuit, 11... p isolation layer, 12... electrode, 13... ...Semiconductor chip, 14...Terminal, 15
...Electrostatic breakdown prevention element, 16...Terminal, 17...
Electrostatic damage prevention element.
Claims (1)
形成される静電破壊防止素子であつて、この静電
破壊防止素子は第１導電型の半導体基体１と、基
体１の上に形成され定電位に固定された第２導電
型半導体層２と半導体層２の表面に形成された第
１導電型半導体領域３と、この第１導電型半導体
領域３の表面に形成された上記端子に電極を通し
て接続された第２導電型半導体領域４とから成
り、端子を介して上記電極下半導体領域にサージ
パルス電圧が加わつた状態で該領域がサイリスタ
の一部として動作し、サージパルスを吸収するよ
うに構成された半導体装置。 ２ 一つの半導体基体表面に形成された半導体集
積回路の複数の端子と基準電位点との間にそれぞ
れ独立して定電位に固定された半導体層表面にベ
ース，エミツタ拡散層を利用して形成された複数
の静電破壊防止素子であつて、上記端子を介して
上記ベース，エミツタ拡散層にサージパルス電圧
が加わつた状態で該拡散層がサイリスタの一部と
して動作し、サージパルスを吸収するようにそれ
ぞれ構成された半導体装置において、電流が流れ
易い回路に対応する端子の静電破壊防止素子にあ
つてはサイリスタの一部を構成する端子側のpn
接合の少なくとも一部を短絡するとともに端子と
集積回路との間に抵抗を介在させるものとし、電
流の流れにくい回路に対応する入力端子の静電破
壊防止素子にあつてはサイリスタの一部を構成す
るpn接合を短絡することなく、かつ入力端子と
集積回路とを直結してあることを特徴とする半導
体装置。[Claims] 1. An electrostatic breakdown prevention element formed between a terminal of a semiconductor integrated circuit and a reference potential point, which includes a semiconductor substrate 1 of a first conductivity type, and a substrate 1 of a first conductivity type. A second conductivity type semiconductor layer 2 formed on the semiconductor layer 1 and fixed at a constant potential, a first conductivity type semiconductor region 3 formed on the surface of the semiconductor layer 2, and a second conductivity type semiconductor region 3 formed on the surface of the first conductivity type semiconductor region 3. and a second conductive type semiconductor region 4 connected to the above-mentioned terminal through an electrode, and when a surge pulse voltage is applied to the semiconductor region under the electrode through the terminal, the region operates as a part of a thyristor, A semiconductor device configured to absorb surge pulses. 2 A semiconductor integrated circuit formed on the surface of a semiconductor substrate using base and emitter diffusion layers on the surface of a semiconductor layer each independently fixed at a constant potential between a plurality of terminals of a semiconductor integrated circuit formed on the surface of a single semiconductor substrate and a reference potential point. and a plurality of electrostatic breakdown prevention elements, wherein when a surge pulse voltage is applied to the base and emitter diffusion layers through the terminals, the diffusion layers operate as a part of a thyristor to absorb surge pulses. In a semiconductor device configured in each of
At least a part of the junction shall be short-circuited and a resistor shall be interposed between the terminal and the integrated circuit, and in the case of an electrostatic breakdown prevention element for an input terminal corresponding to a circuit in which current does not easily flow, it constitutes a part of a thyristor. A semiconductor device characterized in that an input terminal and an integrated circuit are directly connected without shorting a pn junction.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983679A JPS55113358A (en) | 1979-02-23 | 1979-02-23 | Semiconductor device |
| DE19792951421 DE2951421A1 (en) | 1979-02-23 | 1979-12-20 | Integrated semiconductor circuit - with input terminal protected against electrostatic breakdown by alternating films of opposite conductivity type |
| IT20126/80A IT1141374B (en) | 1979-02-23 | 1980-02-22 | SEMICONDUCTOR INTEGRATED CIRCUIT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983679A JPS55113358A (en) | 1979-02-23 | 1979-02-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55113358A JPS55113358A (en) | 1980-09-01 |
| JPS6248901B2 true JPS6248901B2 (en) | 1987-10-16 |
Family
ID=12010351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983679A Granted JPS55113358A (en) | 1979-02-23 | 1979-02-23 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS55113358A (en) |
| DE (1) | DE2951421A1 (en) |
| IT (1) | IT1141374B (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5696851A (en) * | 1979-12-27 | 1981-08-05 | Fujitsu Ltd | Static breakdown preventive element |
| GB2088634B (en) * | 1980-12-03 | 1984-08-15 | Rca Corp | Protection circuit for integrated circuit devices |
| US4595941A (en) * | 1980-12-03 | 1986-06-17 | Rca Corporation | Protection circuit for integrated circuit devices |
| IT1151504B (en) * | 1981-01-30 | 1986-12-24 | Rca Corp | PROTECTION CIRCUIT FOR INTEGRATED CIRCUIT DEVICES |
| JPS57139957A (en) * | 1981-02-24 | 1982-08-30 | Mitsubishi Electric Corp | Protective diode of semiconductor integrated circuit device |
| US4400711A (en) * | 1981-03-31 | 1983-08-23 | Rca Corporation | Integrated circuit protection device |
| US4567500A (en) * | 1981-12-01 | 1986-01-28 | Rca Corporation | Semiconductor structure for protecting integrated circuit devices |
| JPS58186959A (en) * | 1982-04-26 | 1983-11-01 | Nec Corp | Semiconductor device |
| JPS59702U (en) * | 1982-06-22 | 1984-01-06 | 三洋電機株式会社 | Extracted tablet confirmation device for tablet packaging machine |
| JPS5948951A (en) * | 1982-09-14 | 1984-03-21 | Toshiba Corp | Semiconductor protective device |
| US4484244A (en) * | 1982-09-22 | 1984-11-20 | Rca Corporation | Protection circuit for integrated circuit devices |
| JPS59200454A (en) * | 1983-04-27 | 1984-11-13 | Nec Corp | Electrostatic breakdown protective element |
| US4633283A (en) * | 1985-03-11 | 1986-12-30 | Rca Corporation | Circuit and structure for protecting integrated circuits from destructive transient voltages |
| JP2537836B2 (en) * | 1987-02-02 | 1996-09-25 | 松下電子工業株式会社 | Semiconductor protection device |
| DE3835569A1 (en) * | 1988-10-19 | 1990-05-03 | Telefunken Electronic Gmbh | Protective arrangement |
| DE59108436D1 (en) * | 1991-10-22 | 1997-02-06 | Itt Ind Gmbh Deutsche | Protection circuit for connection contacts of monolithically integrated circuits |
| US5440151A (en) * | 1993-04-09 | 1995-08-08 | Matra Mhs | Electrostatic discharge protection device for MOS integrated circuits |
-
1979
- 1979-02-23 JP JP1983679A patent/JPS55113358A/en active Granted
- 1979-12-20 DE DE19792951421 patent/DE2951421A1/en not_active Withdrawn
-
1980
- 1980-02-22 IT IT20126/80A patent/IT1141374B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| IT8020126A0 (en) | 1980-02-22 |
| JPS55113358A (en) | 1980-09-01 |
| DE2951421A1 (en) | 1980-09-04 |
| IT1141374B (en) | 1986-10-01 |
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