JPS59200454A - Electrostatic breakdown protective element - Google Patents
Electrostatic breakdown protective elementInfo
- Publication number
- JPS59200454A JPS59200454A JP7447483A JP7447483A JPS59200454A JP S59200454 A JPS59200454 A JP S59200454A JP 7447483 A JP7447483 A JP 7447483A JP 7447483 A JP7447483 A JP 7447483A JP S59200454 A JPS59200454 A JP S59200454A
- Authority
- JP
- Japan
- Prior art keywords
- region
- surge
- internal element
- diode
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001681 protective effect Effects 0.000 title abstract description 9
- 230000015556 catabolic process Effects 0.000 title description 2
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 abstract description 16
- 238000002955 isolation Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 229910052500 inorganic mineral Inorganic materials 0.000 description 1
- 239000011707 mineral Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は集積回路のサブストレート電位と端子間に加わ
る静電気あるいはサージ電圧＆一対する保護素子に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrostatic or surge voltage applied between a substrate potential and terminals of an integrated circuit and a pair of protection elements.
集積回路の検査工程あるいは組立工程等で加わる静電気
により、集積回路の内部素子が破壊することがある。従
来この対策として第１図の様に内部素子９と直列に保護
抵抗１０′を接続し内部素子９に流れるピーク電流を制
限するか、第２図の様に内部素子９に並列に保護ダイオ
ード１２′を接続し、内部素子９に加わる電圧を制限す
る方法が知られている。Static electricity applied during the testing or assembly process of integrated circuits may destroy internal elements of the integrated circuit. Conventionally, as a countermeasure against this problem, a protective resistor 10' is connected in series with the internal element 9 to limit the peak current flowing through the internal element 9 as shown in FIG. 1, or a protective diode 12 is connected in parallel to the internal element 9 as shown in FIG. A method is known in which the voltage applied to the internal element 9 is limited by connecting .
しかし、第１図の保護抵抗１０′による方法では集積回
路の動作を損う程度の抵抗値が必要な場合や、内部素子
９が酸化膜コンデンサのように電界で破壊する素子に対
しては保護効果がない欠点を有する。However, the method using the protective resistor 10' shown in Fig. 1 does not provide protection when a resistance value that is high enough to impair the operation of the integrated circuit is required, or when the internal element 9 is destroyed by an electric field, such as an oxide film capacitor. It has the disadvantage of being ineffective.
また第２図の保護ダイオード１２′による方法では保賎
ダイオード１２’が順方向で動作する場合は保護効果は
充分認められるが、逆方向に対しては内部素子の耐圧が
保護ダイオード１２′の耐圧に比べ著しく低い場合は保
護効果がない欠点を有する。In addition, in the method using the protection diode 12' shown in Fig. 2, the protection effect is sufficient when the protection diode 12' operates in the forward direction, but in the reverse direction, the withstand voltage of the internal elements is higher than the withstand voltage of the protection diode 12'. If it is significantly lower than that, there is a drawback that there is no protective effect.
またこの欠点を解消するために保護ダイオード１２′の
プビークダウン電圧を回路動作を損わない範囲で低くす
る構成をとると、保護ダイオード１２′自体の破壊耐量
が問題になシ破壊耐量確保のため接合面積が増大し、接
合容量や、リーク電流によシ集積回路の機能を損う場合
や、高い動作電圧の端子については保護効果が不充分と
いう欠点を有する０
本発明は保護ダイオードによるこの様な欠点を改良した
もので、保護ダイオードが逆方向となるサージに対して
は電流制限回路を追加して、内部素子の電流を制限する
ものである。In addition, in order to eliminate this drawback, if a configuration is adopted in which the peak-down voltage of the protection diode 12' is lowered within a range that does not impair the circuit operation, the breakdown resistance of the protection diode 12' itself becomes a problem. The present invention has the disadvantage that the area increases, and the function of the integrated circuit is impaired due to junction capacitance and leakage current, and that the protection effect is insufficient for terminals with high operating voltage. This is an improvement on the shortcomings, and a current limiting circuit is added to limit the current of internal elements in case of a surge where the protective diode is in the opposite direction.
次に図面を参照して本発明をよシ詳細に説明する。第３
図は本発明の保護素子の動作を説明する等価回路である
。第３図において、集積回路の端子に正のサージが加わ
った場合はサージ電流による抵抗１０の電圧降下分によ
シ、トランジスタ１１を動作させて、サージを吸収し内
部素子９を流れる電流を制限する。また負のサージが加
わった場合は、第２図と同様にダイオード１２の順方向
で内部素子９に加わる電圧を制限する。Next, the present invention will be explained in more detail with reference to the drawings. Third
The figure is an equivalent circuit explaining the operation of the protection element of the present invention. In FIG. 3, when a positive surge is applied to the terminal of the integrated circuit, the transistor 11 is operated to absorb the surge and limit the current flowing through the internal element 9 by the voltage drop across the resistor 10 due to the surge current. do. Further, when a negative surge is applied, the voltage applied to the internal element 9 is limited in the forward direction of the diode 12 as in FIG. 2.
本発明においては端子に正のサージが加わった場合の保
護素子の動作を第３図の抵抗１０の抵抗によシ設定して
いるため保護素子の耐圧を低く設定する必要がなく、高
い動作電圧の端子に適用しても保護効果は変らない。In the present invention, the operation of the protection element when a positive surge is applied to the terminal is set to the resistance of the resistor 10 in Figure 3, so there is no need to set the withstand voltage of the protection element low, and the operating voltage is high. The protective effect does not change even if applied to the terminal.
また集積回路に加わるサージパルスは数百ボルトとされ
ているが、第１図の保護回路では数６ボルトのサージに
対し保護抵抗１０′（よシピーク電流値を制限する必要
があるのに対し、第３図の保護抵抗１０は１ボルト穆度
の電圧降下で保護回路を動作させるので、抵抗値を低く
設定することができる。Furthermore, the surge pulse applied to an integrated circuit is said to be several hundred volts, but in the protection circuit shown in Fig. 1, a protective resistor 10' is required (to limit the peak current value) against a surge of several 6 volts. Since the protection resistor 10 shown in FIG. 3 operates the protection circuit with a voltage drop of 1 volt, the resistance value can be set low.
第４図は本発明の一実施例による保護素子の構成を示す
図で、第４図において１はＰ型半導体基板１および、構
成素子を分離するために避択的に拡散されたＰ型絶縁領
域、２は半導体基板１′上に形成され独立に分離された
Ｎ型エピタキシャル領域、３はエピタキシャル領域２の
表面に選択的に形成されたＰ型拡散領域でＮＰＮ）ラン
ジスタのベース拡散工程で形成できる。４はエピタキシ
ャル領域２および拡散領域３に選択的に形成されたＮ形
拡散領域で、このＮ形拡散領域４とエピタキシャル領域
２とのそれぞれの一部はＰ形拡散領域３によシ分離され
ている。また、このＮ形拡散領域４はＮＰＮトランジス
タのエミッタ拡散工種で形成される。５は半導体表面を
保護する絶縁膜、６は集積回路の外部端子に接続する配
線と、Ｐ形拡散領域３およびＮ形鉱散領域４の一端とを
接続する電極、７は集積回路の内部素子に接続する配線
と、Ｎ形拡散領域４の他端を接続する電極、８は集積回
路の基板１′に電位を与えるための電極部であシ、通常
集積回路のグランド端子に接続されている。FIG. 4 is a diagram showing the structure of a protection element according to an embodiment of the present invention. In FIG. Region 2 is an N-type epitaxial region formed on the semiconductor substrate 1' and separated independently, and 3 is a P-type diffusion region selectively formed on the surface of the epitaxial region 2, which is formed in the base diffusion process of an NPN transistor. can. Reference numeral 4 denotes an N-type diffusion region selectively formed in the epitaxial region 2 and the diffusion region 3, and a portion of each of the N-type diffusion region 4 and the epitaxial region 2 is separated by the P-type diffusion region 3. There is. Further, this N type diffusion region 4 is formed by an emitter diffusion process of an NPN transistor. 5 is an insulating film that protects the semiconductor surface; 6 is an electrode that connects a wiring that connects to an external terminal of the integrated circuit; and one end of the P-type diffusion region 3 and the N-type mineral dispersion region 4; and 7 is an internal element of the integrated circuit. and an electrode connecting the other end of the N-type diffusion region 4. 8 is an electrode section for applying a potential to the substrate 1' of the integrated circuit, and is usually connected to the ground terminal of the integrated circuit. .
Ｎ形拡散領域４のｔ極６，７間で、第３図の抵抗１０を
構成し、絶縁分離領域１とエピタキシャル領域２とのＰ
Ｎ接合によシ第３図のダイオード１２を構成し、各領域
３，２．１をそれぞれエミッタ、ベース、コレクターと
するＰＮＰ ）ランジスタ１１を構成している。またエ
ピタキシャル領域２によシ絶縁分離領域１とＰ形拡散領
域３との一部を分離することにより、保護動作時のＰＮ
Ｐトランジスタのベースバイアスを深くできる様に構成
したものである。The resistor 10 shown in FIG. 3 is formed between the t-poles 6 and 7 of the N-type diffusion region 4, and the
The N-junction constitutes the diode 12 shown in FIG. 3, and constitutes a PNP transistor 11 in which each region 3, 2.1 serves as an emitter, a base, and a collector, respectively. In addition, by separating a part of the insulation isolation region 1 and the P-type diffusion region 3 by the epitaxial region 2, it is possible to
The structure is such that the base bias of the P transistor can be made deep.
以上説明した様に本発明により、集積回路のサブストレ
ート電位（電源のマイナス電位）と任意の端子に加わる
正、負両方向のサージに対し、集積回路の機能を損うこ
となく、内部の素子を保護することができる。As explained above, according to the present invention, internal elements can be protected against surges in both positive and negative directions applied to the substrate potential (minus potential of the power supply) of an integrated circuit and any terminal without impairing the functions of the integrated circuit. can be protected.
第１図および第２図は従来の保護素子の例を示す回路図
、第３図は本発明の保護素子の等価回路、第４図は本発
明の一実施例を示す断面図を表わす。
１・・・・・・Ｐ型絶縁分離領域、２・・・・・・Ｎ型
エピタキシャル領域、３・・・・・・Ｐ型拡散領域、４
・・・・・・Ｎ型拡散領域、５・・・・・・絶縁膜、６
・・・・・・外部端子に接続される配線、７・・・・・
・内部回路に接続される配線、８・・・・・・基板に電
位を与える配線、９・・・・・・内部素子、１０ 、１
０’・・・・・・抵抗、１１・・・・・・ＰＮＰトラン
ジスタ、１２・・・・・・ダイオード。1 and 2 are circuit diagrams showing examples of conventional protection elements, FIG. 3 is an equivalent circuit of the protection element of the present invention, and FIG. 4 is a sectional view showing an embodiment of the present invention. 1... P-type insulation isolation region, 2... N-type epitaxial region, 3... P-type diffusion region, 4
...N-type diffusion region, 5...Insulating film, 6
...Wiring connected to external terminals, 7...
・Wiring connected to the internal circuit, 8...Wiring giving potential to the board, 9...Internal element, 10, 1
0'...Resistor, 11...PNP transistor, 12...Diode.
Claims (1)
１の半導体領域と、該第１の半導体領域内に形成された
第２導伝型の第２の半導体領域とこれら第１および第２
の半導体領域のそれぞれの一部に重複して形成された第
１導伝型の第３の半導体領域とを含み、前記第２および
第３の半導体領域のＰＮ接合を賎絡して一方の端子とし
、前記第１の半導体領域内の前記第３の半導体領域の部
分を他方の端子とすることを特徴とする静電破壊保護素
子。a first semiconductor region of a second conductivity type formed on a semiconductor substrate of a first conductivity type; a second semiconductor region of a second conductivity type formed within the first semiconductor region; 1st and 2nd
a third semiconductor region of the first conductivity type formed overlappingly with a portion of each of the semiconductor regions, and connecting the PN junctions of the second and third semiconductor regions to form one terminal. An electrostatic discharge protection element, characterized in that the third semiconductor region within the first semiconductor region is the other terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7447483A JPS59200454A (en) | 1983-04-27 | 1983-04-27 | Electrostatic breakdown protective element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7447483A JPS59200454A (en) | 1983-04-27 | 1983-04-27 | Electrostatic breakdown protective element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59200454A true JPS59200454A (en) | 1984-11-13 |
| JPH0468785B2 JPH0468785B2 (en) | 1992-11-04 |
Family
ID=13548288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7447483A Granted JPS59200454A (en) | 1983-04-27 | 1983-04-27 | Electrostatic breakdown protective element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59200454A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01290251A (en) * | 1988-05-18 | 1989-11-22 | Sanyo Electric Co Ltd | Electrostatic breakdown preventing device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49114380A (en) * | 1973-02-28 | 1974-10-31 | ||
| JPS55113358A (en) * | 1979-02-23 | 1980-09-01 | Hitachi Ltd | Semiconductor device |
-
1983
- 1983-04-27 JP JP7447483A patent/JPS59200454A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49114380A (en) * | 1973-02-28 | 1974-10-31 | ||
| JPS55113358A (en) * | 1979-02-23 | 1980-09-01 | Hitachi Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01290251A (en) * | 1988-05-18 | 1989-11-22 | Sanyo Electric Co Ltd | Electrostatic breakdown preventing device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0468785B2 (en) | 1992-11-04 |
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