JPS61274343A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61274343A JPS61274343A JP60115686A JP11568685A JPS61274343A JP S61274343 A JPS61274343 A JP S61274343A JP 60115686 A JP60115686 A JP 60115686A JP 11568685 A JP11568685 A JP 11568685A JP S61274343 A JPS61274343 A JP S61274343A
- Authority
- JP
- Japan
- Prior art keywords
- type
- semiconductor substrate
- pad portion
- substrate
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置、特に外部への配線のためにパッド
部を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a pad portion for wiring to the outside.
一般に半導体装置は外部への配線のためにパッド部を有
する。従来用いられている通常のパッド部の構成を第５
図に示す。半導体基板１の上に絶縁膜２を介してパッド
部３が設けられている。この上に保護膜４が形成され、
パッド部３の上の保護膜はボンディングのために除去さ
れている。Generally, a semiconductor device has a pad portion for wiring to the outside. The structure of the conventionally used normal pad part is the fifth one.
As shown in the figure. A pad portion 3 is provided on a semiconductor substrate 1 with an insulating film 2 interposed therebetween. A protective film 4 is formed on this,
The protective film on the pad portion 3 is removed for bonding.
パッド部３にはワイヤボンディング等のボンディングが
行われるが、このボンディング工程は一般にパッド部３
に圧力をかけて行うため、この衝撃で絶縁膜２にクラッ
ク等が発生し、その結果パッド部３と半導体基板１とが
電気的にショートしリーク電流が流れるという事故の起
る可能性がある。Bonding such as wire bonding is performed on the pad portion 3, but this bonding process is generally performed on the pad portion 3.
Since pressure is applied to the insulating film 2, this impact may cause cracks, etc. in the insulating film 2, resulting in an electrical short circuit between the pad portion 3 and the semiconductor substrate 1, which may cause an accident in which a leakage current flows. .
そこで、このようなリーク電流の発生を防止するため、
第６肉に示すように半導体基板１の表層に基板とは逆導
電型の不純物拡散層を設ける構造が提案されている。即
ち、半導体基板１がＮ型であれば、その表層のパッド部
直下にＰ＋不純物領域５を設けるのである。このような
構造については特開昭５８−３９０２４号公報に詳述さ
れているので、ここでは簡単な説明だけを行う。一般に
パッド部３に接続されている半導体装置の入出力段は第
７図に示すようにＣＭＯＳトランジスタ１１〜１４で構
成される。図の一点鎖線で囲った部分が半導体装置の内
部であり、パッド部３を介して外部端子０１ＪＴと入出
力が行われる。ここでＶ ＝ＯＶ、ＶＤＤ＝５Ｖとす
れば、パッド部３のＳ
電圧レベルは常に０〜５■となる。ここで第６図に示す
構成において、Ｐ＋不純物領域５と半導体基板１とのＰ
Ｎ接合をダイオード６と考えれば第８図のようになる。Therefore, in order to prevent the occurrence of such leakage current,
As shown in the sixth figure, a structure has been proposed in which an impurity diffusion layer of a conductivity type opposite to that of the substrate is provided on the surface layer of the semiconductor substrate 1. That is, if the semiconductor substrate 1 is of N type, the P+ impurity region 5 is provided directly under the pad portion of its surface layer. Since such a structure is described in detail in Japanese Patent Laid-Open No. 58-39024, only a brief explanation will be given here. Generally, the input/output stage of the semiconductor device connected to the pad portion 3 is composed of CMOS transistors 11 to 14 as shown in FIG. The part surrounded by the dashed line in the figure is the inside of the semiconductor device, and input/output is performed via the pad section 3 to the external terminal 01JT. Here, if V=OV and VDD=5V, the S voltage level of the pad section 3 will always be 0 to 5. Here, in the configuration shown in FIG. 6, the P+ impurity region 5 and the semiconductor substrate 1 are
If the N junction is considered as a diode 6, the result will be as shown in FIG.
半導体基板１はＶ ＯＯ１即ち５■であり、パッド部３
の電圧レベルは前述のようにＯ〜５■であるため、半導
体基板１とパッド部３との間には、常にパッド部３側が
負極性（または等しい）となる関係がある。即ち電１１
１７が第８図に示す方向に接続されていると考えればよ
い。The semiconductor substrate 1 has VOO1, that is, 5■, and the pad portion 3
Since the voltage level is O to 5■ as described above, there is a relationship between the semiconductor substrate 1 and the pad portion 3 such that the pad portion 3 side always has negative (or equal) polarity. That is, electricity 11
17 are connected in the direction shown in FIG.
ここでダイオード６の向きに着目すれば、電源７に対し
て逆方向となる。従ってボンディング工程で絶縁膜２に
クラックが生じ、パッド部３と不純物領域５とが麿通し
たとしても、リーク電流は流れない。If we pay attention to the direction of the diode 6 here, it will be in the opposite direction to the power supply 7. Therefore, even if a crack occurs in the insulating film 2 during the bonding process and the pad portion 3 and the impurity region 5 pass through each other, no leakage current will flow.
従来の装置では、第８図に示すようにパッド部３の電位
が半導体基板１の電位より決して高くはならない場合に
は、有効にリーク電流の発生を防止することができるが
、第９図に示すようにパッド部３の電位が半導体基板１
の電位より高くなった場合、即ち電源７の極性が変わっ
た場合には、ダイオード６に対して電ＷＡ７が順方向電
流を流すため、リーク電流の発生を防止することができ
ない。第７図に示したような０ＭＯ８構成による入出力
段回路では、前述のように常にパッド部３の電位が半導
体基板１の電位より低いか等しくなるため問題はないが
、近年オーブンドレイン型の入出力段回路を用いる半導
体装置もあられれ、パッド部３の電位が半導体基板１の
電位より高くなる場合もありうる。このように従来の装
置では、このような入出力段回路を用いる回路構成の場
合には、リーク電流の発生を防止することができないと
いう欠点があった。In the conventional device, when the potential of the pad section 3 never becomes higher than the potential of the semiconductor substrate 1, as shown in FIG. 8, the occurrence of leakage current can be effectively prevented. As shown, the potential of the pad portion 3 is lower than that of the semiconductor substrate 1.
If the potential becomes higher than that of , that is, if the polarity of the power supply 7 changes, the electric current WA7 causes a forward current to flow through the diode 6, making it impossible to prevent leakage current from occurring. In the input/output stage circuit with the 0MO8 configuration shown in FIG. 7, there is no problem because the potential of the pad portion 3 is always lower than or equal to the potential of the semiconductor substrate 1 as described above, but in recent years, oven drain type input There may also be a semiconductor device using an output stage circuit, and the potential of the pad portion 3 may be higher than the potential of the semiconductor substrate 1. As described above, in the case of a circuit configuration using such an input/output stage circuit, the conventional device has the disadvantage that it is not possible to prevent the occurrence of leakage current.
そこで本発明は入出力段回路にオープンドレイン型回路
を用いた場合でも、リーク電流の発生を防止しうる半導
体装置を提供することを目的とする。SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device that can prevent leakage current from occurring even when an open drain type circuit is used for the input/output stage circuit.
本発明の特徴は半導体装置において、第１の導電型の半
導体基板の表面上に絶縁膜を介して導°電性のパッド部
を形成し、このパッド部に対応する基板の表層に第２の
導電型の不純物領域を形成し、この第２の導電型の不純
物領域の内側表層に第１の導電型の不純物領域を形成し
、パッド部の電位が半導体基板の電位より高くなるオー
プンドレイン型の入出力段回路を用いた場合でも、リー
ク電流の発生を防止しつるようにした点にある。A feature of the present invention is that in a semiconductor device, a conductive pad portion is formed on the surface of a first conductivity type semiconductor substrate via an insulating film, and a second conductive pad portion is formed on the surface layer of the substrate corresponding to the pad portion. A conductivity type impurity region is formed, a first conductivity type impurity region is formed in the inner surface layer of the second conductivity type impurity region, and the potential of the pad portion is higher than the potential of the semiconductor substrate. Even when an input/output stage circuit is used, the leakage current can be prevented and the suspension can be maintained.
（発明の実施例）
以下本発明を図示する実施例に基づいて説明する。第１
図は本発明に係る半導体装置のパッド部の構成図である
。半導体基板１の上に絶縁１１２を介してパッド部３が
設けられている。この上に保護＃！４が形成され、パッ
ド部３の上の保護膜はボンディングのために除去されて
いる。半導体基板１の表層のパッド部３の下の領域には
基板とは逆導電型の不純物拡散層、即ち、Ｎ型の基板に
対してはＰ型の不純物を拡散したＰ型ウェル５１が設け
られ、更にこのＰ型ウェル５１の内側表層には基板と同
じ導電型の不純物領域、即ちＮ＋不純物領域５２が設け
られている。Ｐ型の半導体基板１′を用いた場合には、
第２図に示すようにＮ型ウェル５１′とＰ＋不純物領域
５２′とが設けられる。このように二層の不純物領域を
設けることによるＰＮ接合によって２つのダイオード６
１゜６２あるいは６１’ 、６２’が形成される。(Embodiments of the Invention) The present invention will be described below based on illustrated embodiments. 1st
The figure is a configuration diagram of a pad portion of a semiconductor device according to the present invention. A pad section 3 is provided on the semiconductor substrate 1 with an insulator 112 interposed therebetween. #protection on this! 4 is formed, and the protective film on the pad portion 3 is removed for bonding. In a region below the pad portion 3 on the surface layer of the semiconductor substrate 1, an impurity diffusion layer having a conductivity type opposite to that of the substrate is provided, that is, a P-type well 51 in which P-type impurities are diffused for an N-type substrate is provided. Furthermore, an impurity region of the same conductivity type as the substrate, that is, an N+ impurity region 52 is provided in the inner surface layer of this P-type well 51. When a P-type semiconductor substrate 1' is used,
As shown in FIG. 2, an N type well 51' and a P+ impurity region 52' are provided. Two diodes 6 are formed by the PN junction by providing two layers of impurity regions in this way.
1°62 or 61', 62' are formed.
ここでオーブンドレイン型の入出力段回路の動作につい
て考える。第３図はＰチャネルオープンドレイン端子付
近の回路図、第４図はＮチャネルオーブンドレイン端子
付近の回路図である。どちらも一点鎖線で囲った部分が
半導体装置の内部であり、パッド部３を介して外部端子
ＯＵＴと入出力が行われる。第３図に示す回路はＭＯＳ
トランジスタ１１．１２．１５で構成され、パッド部３
は抵抗１７を介して電源Ｖｓ８２に接続されている。Let us now consider the operation of the oven-drain type input/output stage circuit. FIG. 3 is a circuit diagram near the P channel open drain terminal, and FIG. 4 is a circuit diagram near the N channel open drain terminal. In both cases, the portion surrounded by the dashed line is the inside of the semiconductor device, and input/output is performed via the pad portion 3 with the external terminal OUT. The circuit shown in Figure 3 is a MOS
Consisting of transistors 11, 12, and 15, pad portion 3
is connected to the power supply Vs82 via the resistor 17.
ここでＶ８３２＜Ｖ３Ｓｉであり、例えばＶＳＳ１＝０
■、Ｖ □Ｑ＝ ５ Ｖとすれば、Ｖ３３２＝ ５Ｖ
となる。従ってパッド部３の電圧レベルは一５Ｖ〜＋５
Ｖの間の値となる。半導体基板の電位はｖＤＯ１即ち５
ｖであるから、この回路では半導体基板１とパッド部３
との間には、常にパッド部３側が負極性（または等しい
）となる関係がある。ところが第４図に示す回路はＭＯ
Ｓトランジスタ１１゜１２．１６で構成され、パッド部
３は抵抗１８を介して電源■。ｏ２に接続されている。Here, V832<V3Si, for example, VSS1=0
■, V □ If Q = 5 V, V332 = 5 V
becomes. Therefore, the voltage level of pad section 3 is -5V to +5V.
The value is between V and V. The potential of the semiconductor substrate is vDO1, that is, 5
v, so in this circuit, the semiconductor substrate 1 and the pad portion 3
There is a relationship in which the pad portion 3 side always has negative (or equal) polarity. However, the circuit shown in Figure 4 is MO
It is composed of an S transistor 11°12.16, and the pad part 3 is connected to the power supply (2) through a resistor 18. connected to o2.
ここで■００２ 〉■００１であり、例えばｖ、＝ｏｖ
。Here ■002 > ■001, for example v, = ov
.
Ｖ９，１＝５Ｖとすれば、Ｖｏｏ２＝１０Ｖとなる。If V9,1=5V, Voo2=10V.
従ってパッド部３の電圧レベルはＯｖ〜１０ｖの間の値
となる。半導体基板の電位はＶ 即ち口０１１
５■であるから、この回路では半導体基板１とパッド部
３との間の極性は、回路動作によって°反転することに
なる。Therefore, the voltage level of the pad portion 3 is a value between Ov and 10V. Since the potential of the semiconductor substrate is V, that is, the polarity between the semiconductor substrate 1 and the pad portion 3 is reversed by the circuit operation.
ここで再び第１図あるいは第２図の構成をみると、どち
らの場合も２つのダイオードが逆の向きに直列接続され
た形となっている。従って絶縁膜２にボンディング工程
でクラックが生じたとしても、常にリーク電流の発生を
防止することができる。即ち、パッド部３の電位と半導
体基板１の電位とのどちらが高い場合でも、必ず一方の
ダイオードがリーク電流に対し逆方向接続となるのでリ
ーク電流は流れないのである。Looking again at the configuration of FIG. 1 or FIG. 2, in both cases, two diodes are connected in series in opposite directions. Therefore, even if cracks occur in the insulating film 2 during the bonding process, leakage current can always be prevented from occurring. That is, no matter which of the potentials of the pad portion 3 and the semiconductor substrate 1 is higher, one diode is always connected in the opposite direction to the leakage current, so that no leakage current flows.
なお本発明に係る装置は第６図に示す従来装置と同じ基
板面積で構成することができ、チップ面積を増大させる
ような欠点がない。従って従来装置と同様の高集積化を
行うことができる。また、二層の不純物領域ともに素子
形成領域のＣＭ＜）Ｓ形成工程と同じ工程で形成させる
ことができるため、製造工程のステップが増加する弊害
もない。Note that the device according to the present invention can be constructed with the same substrate area as the conventional device shown in FIG. 6, and does not have the disadvantage of increasing the chip area. Therefore, it is possible to achieve high integration similar to the conventional device. Further, since both the two-layer impurity regions can be formed in the same process as the CM<)S formation process in the element formation region, there is no problem of an increase in the number of steps in the manufacturing process.
以上のとおり本発明によれば、半導体装置において、パ
ッド部の下に導電性の異なる不純物領域を二Ｍ設けるよ
うにしたため、パッド部の電位が半導４に′−板の電位
より高くなるオープンドレイン型の入出力段回路を用い
た場合でも、リーク電流の発生を防止することができる
。As described above, according to the present invention, in the semiconductor device, 2M impurity regions with different conductivities are provided under the pad portion, so that the potential of the pad portion is higher than the potential of the semiconductor 4 plate. Even when a drain type input/output stage circuit is used, leakage current can be prevented from occurring.
第１図および第２図は本発明に係る半導体装置のパッド
部の構成図、第３図および第４図はオーブンドレイン型
の入出力段回路の回路図、第５図および第６図は従来の
半導体装置のパッド部の構成図、第７図は０ＭＯ８型の
入出力段＠路の回路図、第８図および第９図は第６図に
示す従来装置の動作説明図である。
１．１′・・・半導体基板、２・・・絶縁膜、３・・・
パッド部、４・・・保ＷＩｌｌ、 ５・・・Ｐ＋不純物
領域、５１・・・Ｐ型ウェル、５１′・・・Ｎ型ウェル
、５２・・・Ｎ＋不純物領域、５２′・・・Ｐ＋不純物
領域、６．６１゜６２．６１’ 、６２’・・・ダイオ
ード、７・・・電源、１１〜１６・・・ＭＯＳトランジ
スタ、１７．１８・・・抵抗。1 and 2 are configuration diagrams of a pad portion of a semiconductor device according to the present invention, FIGS. 3 and 4 are circuit diagrams of oven-drain type input/output stage circuits, and FIGS. 5 and 6 are conventional diagrams. FIG. 7 is a circuit diagram of an 0MO8 type input/output stage @ circuit, and FIGS. 8 and 9 are explanatory diagrams of the operation of the conventional device shown in FIG. 6. 1.1'...Semiconductor substrate, 2...Insulating film, 3...
Pad portion, 4... Hold WILL, 5... P+ impurity region, 51... P type well, 51'... N type well, 52... N+ impurity region, 52'... P+ impurity Area, 6.61°62.61', 62'... Diode, 7... Power supply, 11-16... MOS transistor, 17.18... Resistor.
Claims (1)
成される導電性のパッド部と、このパッド部に対応する
前記基板の表層に形成される第２の導電型の不純物領域
と、前記第２の導電型の不純物領域の内側表層に形成さ
れる第１の導電型の不純物領域とを具備し、前記パッド
部に対しボンディングが行われていることを特徴とする
半導体装置。a conductive pad portion formed on the surface of a semiconductor substrate of a first conductivity type via an insulating film; and an impurity region of a second conductivity type formed in a surface layer of the substrate corresponding to the pad portion. and a first conductivity type impurity region formed in an inner surface layer of the second conductivity type impurity region, and bonding is performed to the pad portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60115686A JPS61274343A (en) | 1985-05-29 | 1985-05-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60115686A JPS61274343A (en) | 1985-05-29 | 1985-05-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61274343A true JPS61274343A (en) | 1986-12-04 |
Family
ID=14668752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60115686A Pending JPS61274343A (en) | 1985-05-29 | 1985-05-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61274343A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0521558A2 (en) * | 1991-07-02 | 1993-01-07 | Koninklijke Philips Electronics N.V. | Semiconductor device with means for increasing the breakdown voltage of a pn-junction |
| KR101015535B1 (en) | 2008-10-30 | 2011-02-16 | 주식회사 동부하이텍 | semiconductor device |
-
1985
- 1985-05-29 JP JP60115686A patent/JPS61274343A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0521558A2 (en) * | 1991-07-02 | 1993-01-07 | Koninklijke Philips Electronics N.V. | Semiconductor device with means for increasing the breakdown voltage of a pn-junction |
| KR101015535B1 (en) | 2008-10-30 | 2011-02-16 | 주식회사 동부하이텍 | semiconductor device |
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