JPS61274343A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61274343A
JPS61274343A JP60115686A JP11568685A JPS61274343A JP S61274343 A JPS61274343 A JP S61274343A JP 60115686 A JP60115686 A JP 60115686A JP 11568685 A JP11568685 A JP 11568685A JP S61274343 A JPS61274343 A JP S61274343A
Authority
JP
Japan
Prior art keywords
type
semiconductor substrate
pad portion
substrate
impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60115686A
Other languages
Japanese (ja)
Inventor
Tadashi Maruyama
正 丸山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60115686A priority Critical patent/JPS61274343A/en
Publication of JPS61274343A publication Critical patent/JPS61274343A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]

Abstract

PURPOSE:To avoid generation of a leakage current even if an open drain type I/O circuit, with which the potential of a pad part is higher than the potential of a semiconductor substrate, is employed by providing two layers of impurity regions, whose respective conductive types are different from each other, under the pad part. CONSTITUTION:A pad part 3 is provided on a semiconductor substrate 1 with an insulation film 2 in between. A protection film 4 is formed over the surface and a part of the protection film 4, above the pad part 3, is removed for bonding. An impurity diffused layer with the conductive type opposite to the substrate, i.e. a P-type well 51 for the N-type substrate 1, is formed in the region of the surface of the semiconductor substrate 1 beneath the pad part 3. Further, an impurity diffused region with the conductive type same as the substrate, i.e. an N<+> type impurity region 52 is formed in the surface layer inside the P-type well 51. If a P-type semiconductor substrate 1' is employed, an N-type well 51' and a P<+> type impurity region 52' are formed. With a P-N junction formed by providing two impurity regions as described above, two diodes 61 and 62 or 61' and 62' are formed.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置、特に外部への配線のためにパッド
部を有する半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a pad portion for wiring to the outside.

〔発明の技術的背景〕[Technical background of the invention]

一般に半導体装置は外部への配線のためにパッド部を有
する。従来用いられている通常のパッド部の構成を第5
図に示す。半導体基板1の上に絶縁膜2を介してパッド
部3が設けられている。この上に保護膜4が形成され、
パッド部3の上の保護膜はボンディングのために除去さ
れている。
Generally, a semiconductor device has a pad portion for wiring to the outside. The structure of the conventionally used normal pad part is the fifth one.
As shown in the figure. A pad portion 3 is provided on a semiconductor substrate 1 with an insulating film 2 interposed therebetween. A protective film 4 is formed on this,
The protective film on the pad portion 3 is removed for bonding.

パッド部3にはワイヤボンディング等のボンディングが
行われるが、このボンディング工程は一般にパッド部3
に圧力をかけて行うため、この衝撃で絶縁膜2にクラッ
ク等が発生し、その結果パッド部3と半導体基板1とが
電気的にショートしリーク電流が流れるという事故の起
る可能性がある。
Bonding such as wire bonding is performed on the pad portion 3, but this bonding process is generally performed on the pad portion 3.
Since pressure is applied to the insulating film 2, this impact may cause cracks, etc. in the insulating film 2, resulting in an electrical short circuit between the pad portion 3 and the semiconductor substrate 1, which may cause an accident in which a leakage current flows. .

そこで、このようなリーク電流の発生を防止するため、
第6肉に示すように半導体基板1の表層に基板とは逆導
電型の不純物拡散層を設ける構造が提案されている。即
ち、半導体基板1がN型であれば、その表層のパッド部
直下にP+不純物領域5を設けるのである。このような
構造については特開昭58−39024号公報に詳述さ
れているので、ここでは簡単な説明だけを行う。一般に
パッド部3に接続されている半導体装置の入出力段は第
7図に示すようにCMOSトランジスタ11〜14で構
成される。図の一点鎖線で囲った部分が半導体装置の内
部であり、パッド部3を介して外部端子01JTと入出
力が行われる。ここでV  =OV、VDD=5Vとす
れば、パッド部3のS 電圧レベルは常に0〜5■となる。ここで第6図に示す
構成において、P+不純物領域5と半導体基板1とのP
N接合をダイオード6と考えれば第8図のようになる。
Therefore, in order to prevent the occurrence of such leakage current,
As shown in the sixth figure, a structure has been proposed in which an impurity diffusion layer of a conductivity type opposite to that of the substrate is provided on the surface layer of the semiconductor substrate 1. That is, if the semiconductor substrate 1 is of N type, the P+ impurity region 5 is provided directly under the pad portion of its surface layer. Since such a structure is described in detail in Japanese Patent Laid-Open No. 58-39024, only a brief explanation will be given here. Generally, the input/output stage of the semiconductor device connected to the pad portion 3 is composed of CMOS transistors 11 to 14 as shown in FIG. The part surrounded by the dashed line in the figure is the inside of the semiconductor device, and input/output is performed via the pad section 3 to the external terminal 01JT. Here, if V=OV and VDD=5V, the S voltage level of the pad section 3 will always be 0 to 5. Here, in the configuration shown in FIG. 6, the P+ impurity region 5 and the semiconductor substrate 1 are
If the N junction is considered as a diode 6, the result will be as shown in FIG.

半導体基板1はV OO1即ち5■であり、パッド部3
の電圧レベルは前述のようにO〜5■であるため、半導
体基板1とパッド部3との間には、常にパッド部3側が
負極性(または等しい)となる関係がある。即ち電11
17が第8図に示す方向に接続されていると考えればよ
い。
The semiconductor substrate 1 has VOO1, that is, 5■, and the pad portion 3
Since the voltage level is O to 5■ as described above, there is a relationship between the semiconductor substrate 1 and the pad portion 3 such that the pad portion 3 side always has negative (or equal) polarity. That is, electricity 11
17 are connected in the direction shown in FIG.

ここでダイオード6の向きに着目すれば、電源7に対し
て逆方向となる。従ってボンディング工程で絶縁膜2に
クラックが生じ、パッド部3と不純物領域5とが麿通し
たとしても、リーク電流は流れない。
If we pay attention to the direction of the diode 6 here, it will be in the opposite direction to the power supply 7. Therefore, even if a crack occurs in the insulating film 2 during the bonding process and the pad portion 3 and the impurity region 5 pass through each other, no leakage current will flow.

〔背景技術の問題点〕[Problems with background technology]

従来の装置では、第8図に示すようにパッド部3の電位
が半導体基板1の電位より決して高くはならない場合に
は、有効にリーク電流の発生を防止することができるが
、第9図に示すようにパッド部3の電位が半導体基板1
の電位より高くなった場合、即ち電源7の極性が変わっ
た場合には、ダイオード6に対して電WA7が順方向電
流を流すため、リーク電流の発生を防止することができ
ない。第7図に示したような0MO8構成による入出力
段回路では、前述のように常にパッド部3の電位が半導
体基板1の電位より低いか等しくなるため問題はないが
、近年オーブンドレイン型の入出力段回路を用いる半導
体装置もあられれ、パッド部3の電位が半導体基板1の
電位より高くなる場合もありうる。このように従来の装
置では、このような入出力段回路を用いる回路構成の場
合には、リーク電流の発生を防止することができないと
いう欠点があった。
In the conventional device, when the potential of the pad section 3 never becomes higher than the potential of the semiconductor substrate 1, as shown in FIG. 8, the occurrence of leakage current can be effectively prevented. As shown, the potential of the pad portion 3 is lower than that of the semiconductor substrate 1.
If the potential becomes higher than that of , that is, if the polarity of the power supply 7 changes, the electric current WA7 causes a forward current to flow through the diode 6, making it impossible to prevent leakage current from occurring. In the input/output stage circuit with the 0MO8 configuration shown in FIG. 7, there is no problem because the potential of the pad portion 3 is always lower than or equal to the potential of the semiconductor substrate 1 as described above, but in recent years, oven drain type input There may also be a semiconductor device using an output stage circuit, and the potential of the pad portion 3 may be higher than the potential of the semiconductor substrate 1. As described above, in the case of a circuit configuration using such an input/output stage circuit, the conventional device has the disadvantage that it is not possible to prevent the occurrence of leakage current.

〔発明の目的〕[Purpose of the invention]

そこで本発明は入出力段回路にオープンドレイン型回路
を用いた場合でも、リーク電流の発生を防止しうる半導
体装置を提供することを目的とする。
SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device that can prevent leakage current from occurring even when an open drain type circuit is used for the input/output stage circuit.

〔発明の概要〕[Summary of the invention]

本発明の特徴は半導体装置において、第1の導電型の半
導体基板の表面上に絶縁膜を介して導°電性のパッド部
を形成し、このパッド部に対応する基板の表層に第2の
導電型の不純物領域を形成し、この第2の導電型の不純
物領域の内側表層に第1の導電型の不純物領域を形成し
、パッド部の電位が半導体基板の電位より高くなるオー
プンドレイン型の入出力段回路を用いた場合でも、リー
ク電流の発生を防止しつるようにした点にある。
A feature of the present invention is that in a semiconductor device, a conductive pad portion is formed on the surface of a first conductivity type semiconductor substrate via an insulating film, and a second conductive pad portion is formed on the surface layer of the substrate corresponding to the pad portion. A conductivity type impurity region is formed, a first conductivity type impurity region is formed in the inner surface layer of the second conductivity type impurity region, and the potential of the pad portion is higher than the potential of the semiconductor substrate. Even when an input/output stage circuit is used, the leakage current can be prevented and the suspension can be maintained.

(発明の実施例) 以下本発明を図示する実施例に基づいて説明する。第1
図は本発明に係る半導体装置のパッド部の構成図である
。半導体基板1の上に絶縁112を介してパッド部3が
設けられている。この上に保護#!4が形成され、パッ
ド部3の上の保護膜はボンディングのために除去されて
いる。半導体基板1の表層のパッド部3の下の領域には
基板とは逆導電型の不純物拡散層、即ち、N型の基板に
対してはP型の不純物を拡散したP型ウェル51が設け
られ、更にこのP型ウェル51の内側表層には基板と同
じ導電型の不純物領域、即ちN+不純物領域52が設け
られている。P型の半導体基板1′を用いた場合には、
第2図に示すようにN型ウェル51′とP+不純物領域
52′とが設けられる。このように二層の不純物領域を
設けることによるPN接合によって2つのダイオード6
1゜62あるいは61’ 、62’が形成される。
(Embodiments of the Invention) The present invention will be described below based on illustrated embodiments. 1st
The figure is a configuration diagram of a pad portion of a semiconductor device according to the present invention. A pad section 3 is provided on the semiconductor substrate 1 with an insulator 112 interposed therebetween. #protection on this! 4 is formed, and the protective film on the pad portion 3 is removed for bonding. In a region below the pad portion 3 on the surface layer of the semiconductor substrate 1, an impurity diffusion layer having a conductivity type opposite to that of the substrate is provided, that is, a P-type well 51 in which P-type impurities are diffused for an N-type substrate is provided. Furthermore, an impurity region of the same conductivity type as the substrate, that is, an N+ impurity region 52 is provided in the inner surface layer of this P-type well 51. When a P-type semiconductor substrate 1' is used,
As shown in FIG. 2, an N type well 51' and a P+ impurity region 52' are provided. Two diodes 6 are formed by the PN junction by providing two layers of impurity regions in this way.
1°62 or 61', 62' are formed.

ここでオーブンドレイン型の入出力段回路の動作につい
て考える。第3図はPチャネルオープンドレイン端子付
近の回路図、第4図はNチャネルオーブンドレイン端子
付近の回路図である。どちらも一点鎖線で囲った部分が
半導体装置の内部であり、パッド部3を介して外部端子
OUTと入出力が行われる。第3図に示す回路はMOS
トランジスタ11.12.15で構成され、パッド部3
は抵抗17を介して電源Vs82に接続されている。
Let us now consider the operation of the oven-drain type input/output stage circuit. FIG. 3 is a circuit diagram near the P channel open drain terminal, and FIG. 4 is a circuit diagram near the N channel open drain terminal. In both cases, the portion surrounded by the dashed line is the inside of the semiconductor device, and input/output is performed via the pad portion 3 with the external terminal OUT. The circuit shown in Figure 3 is a MOS
Consisting of transistors 11, 12, and 15, pad portion 3
is connected to the power supply Vs82 via the resistor 17.

ここでV832<V3Siであり、例えばVSS1=0
■、V □Q= 5 Vとすれば、V332=  5V
となる。従ってパッド部3の電圧レベルは一5V〜+5
Vの間の値となる。半導体基板の電位はvDO1即ち5
vであるから、この回路では半導体基板1とパッド部3
との間には、常にパッド部3側が負極性(または等しい
)となる関係がある。ところが第4図に示す回路はMO
Sトランジスタ11゜12.16で構成され、パッド部
3は抵抗18を介して電源■。o2に接続されている。
Here, V832<V3Si, for example, VSS1=0
■, V □ If Q = 5 V, V332 = 5 V
becomes. Therefore, the voltage level of pad section 3 is -5V to +5V.
The value is between V and V. The potential of the semiconductor substrate is vDO1, that is, 5
v, so in this circuit, the semiconductor substrate 1 and the pad portion 3
There is a relationship in which the pad portion 3 side always has negative (or equal) polarity. However, the circuit shown in Figure 4 is MO
It is composed of an S transistor 11°12.16, and the pad part 3 is connected to the power supply (2) through a resistor 18. connected to o2.

ここで■002 〉■001であり、例えばv、=ov
Here ■002 > ■001, for example v, = ov
.

V9,1=5Vとすれば、Voo2=10Vとなる。If V9,1=5V, Voo2=10V.

従ってパッド部3の電圧レベルはOv〜10vの間の値
となる。半導体基板の電位はV   即ち口011 5■であるから、この回路では半導体基板1とパッド部
3との間の極性は、回路動作によって°反転することに
なる。
Therefore, the voltage level of the pad portion 3 is a value between Ov and 10V. Since the potential of the semiconductor substrate is V, that is, the polarity between the semiconductor substrate 1 and the pad portion 3 is reversed by the circuit operation.

ここで再び第1図あるいは第2図の構成をみると、どち
らの場合も2つのダイオードが逆の向きに直列接続され
た形となっている。従って絶縁膜2にボンディング工程
でクラックが生じたとしても、常にリーク電流の発生を
防止することができる。即ち、パッド部3の電位と半導
体基板1の電位とのどちらが高い場合でも、必ず一方の
ダイオードがリーク電流に対し逆方向接続となるのでリ
ーク電流は流れないのである。
Looking again at the configuration of FIG. 1 or FIG. 2, in both cases, two diodes are connected in series in opposite directions. Therefore, even if cracks occur in the insulating film 2 during the bonding process, leakage current can always be prevented from occurring. That is, no matter which of the potentials of the pad portion 3 and the semiconductor substrate 1 is higher, one diode is always connected in the opposite direction to the leakage current, so that no leakage current flows.

なお本発明に係る装置は第6図に示す従来装置と同じ基
板面積で構成することができ、チップ面積を増大させる
ような欠点がない。従って従来装置と同様の高集積化を
行うことができる。また、二層の不純物領域ともに素子
形成領域のCM<)S形成工程と同じ工程で形成させる
ことができるため、製造工程のステップが増加する弊害
もない。
Note that the device according to the present invention can be constructed with the same substrate area as the conventional device shown in FIG. 6, and does not have the disadvantage of increasing the chip area. Therefore, it is possible to achieve high integration similar to the conventional device. Further, since both the two-layer impurity regions can be formed in the same process as the CM<)S formation process in the element formation region, there is no problem of an increase in the number of steps in the manufacturing process.

〔発明の効果〕〔Effect of the invention〕

以上のとおり本発明によれば、半導体装置において、パ
ッド部の下に導電性の異なる不純物領域を二M設けるよ
うにしたため、パッド部の電位が半導4に′−板の電位
より高くなるオープンドレイン型の入出力段回路を用い
た場合でも、リーク電流の発生を防止することができる
As described above, according to the present invention, in the semiconductor device, 2M impurity regions with different conductivities are provided under the pad portion, so that the potential of the pad portion is higher than the potential of the semiconductor 4 plate. Even when a drain type input/output stage circuit is used, leakage current can be prevented from occurring.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は本発明に係る半導体装置のパッド
部の構成図、第3図および第4図はオーブンドレイン型
の入出力段回路の回路図、第5図および第6図は従来の
半導体装置のパッド部の構成図、第7図は0MO8型の
入出力段@路の回路図、第8図および第9図は第6図に
示す従来装置の動作説明図である。 1.1′・・・半導体基板、2・・・絶縁膜、3・・・
パッド部、4・・・保WIll、 5・・・P+不純物
領域、51・・・P型ウェル、51′・・・N型ウェル
、52・・・N+不純物領域、52′・・・P+不純物
領域、6.61゜62.61’ 、62’・・・ダイオ
ード、7・・・電源、11〜16・・・MOSトランジ
スタ、17.18・・・抵抗。
1 and 2 are configuration diagrams of a pad portion of a semiconductor device according to the present invention, FIGS. 3 and 4 are circuit diagrams of oven-drain type input/output stage circuits, and FIGS. 5 and 6 are conventional diagrams. FIG. 7 is a circuit diagram of an 0MO8 type input/output stage @ circuit, and FIGS. 8 and 9 are explanatory diagrams of the operation of the conventional device shown in FIG. 6. 1.1'...Semiconductor substrate, 2...Insulating film, 3...
Pad portion, 4... Hold WILL, 5... P+ impurity region, 51... P type well, 51'... N type well, 52... N+ impurity region, 52'... P+ impurity Area, 6.61°62.61', 62'... Diode, 7... Power supply, 11-16... MOS transistor, 17.18... Resistor.

Claims (1)

【特許請求の範囲】[Claims] 第1の導電型の半導体基板の表面上に絶縁膜を介して形
成される導電性のパッド部と、このパッド部に対応する
前記基板の表層に形成される第2の導電型の不純物領域
と、前記第2の導電型の不純物領域の内側表層に形成さ
れる第1の導電型の不純物領域とを具備し、前記パッド
部に対しボンディングが行われていることを特徴とする
半導体装置。
a conductive pad portion formed on the surface of a semiconductor substrate of a first conductivity type via an insulating film; and an impurity region of a second conductivity type formed in a surface layer of the substrate corresponding to the pad portion. and a first conductivity type impurity region formed in an inner surface layer of the second conductivity type impurity region, and bonding is performed to the pad portion.
JP60115686A 1985-05-29 1985-05-29 Semiconductor device Pending JPS61274343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60115686A JPS61274343A (en) 1985-05-29 1985-05-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60115686A JPS61274343A (en) 1985-05-29 1985-05-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61274343A true JPS61274343A (en) 1986-12-04

Family

ID=14668752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60115686A Pending JPS61274343A (en) 1985-05-29 1985-05-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61274343A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0521558A2 (en) * 1991-07-02 1993-01-07 Koninklijke Philips Electronics N.V. Semiconductor device with means for increasing the breakdown voltage of a pn-junction
KR101015535B1 (en) 2008-10-30 2011-02-16 주식회사 동부하이텍 semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0521558A2 (en) * 1991-07-02 1993-01-07 Koninklijke Philips Electronics N.V. Semiconductor device with means for increasing the breakdown voltage of a pn-junction
KR101015535B1 (en) 2008-10-30 2011-02-16 주식회사 동부하이텍 semiconductor device

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