JPS63136658A - Electrostatic breakdown preventive element - Google Patents

Electrostatic breakdown preventive element

Info

Publication number
JPS63136658A
JPS63136658A JP28173786A JP28173786A JPS63136658A JP S63136658 A JPS63136658 A JP S63136658A JP 28173786 A JP28173786 A JP 28173786A JP 28173786 A JP28173786 A JP 28173786A JP S63136658 A JPS63136658 A JP S63136658A
Authority
JP
Japan
Prior art keywords
base
diffused layer
emitter
layer
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28173786A
Other languages
Japanese (ja)
Inventor
Takashi Yamaguchi
貴士 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP28173786A priority Critical patent/JPS63136658A/en
Publication of JPS63136658A publication Critical patent/JPS63136658A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain an effective electrostatic breakdown preventing effect in a small area by forming a doughnut-shaped emitter n<+> type diffused layer at a part of a base p-type diffused layer of an npn transistor, and using a pinch resistor and a breakdown preventing resistor formed by a base diffused layer directly under the emitter diffused layer. CONSTITUTION:An n<-> type Si substrate (epitaxial layer) 1 which becomes the collector of an element is partly connected to a VCC potential. A p-type diffused layer 2 which becomes a base of the element, and a p<+> type diffused layer 3 which becomes an emitter of the element are provided, formed in a doughnut shape on the surface of the base, and part of the base p-type layer is exposed. A breakdown normally easily occurs at the peripheral corner of the base p-type diffused layer, but since the p-type diffused layer 2a directly under the emitter n<+> type diffused layer forms a pinch resistor (r), its rhos is high and its resistance value (r) becomes low. Accordingly, it can enhance the electrostatic breakdown preventing effect.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置において、トランジスタと抵抗を利
用した静電破壊防止技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique for preventing electrostatic discharge damage using transistors and resistors in semiconductor devices.

〔従来技術〕[Prior art]

ＩＣ，ＬＳＩにおける静電破壊防止技術につい゛ては、
たとえば日経マグロウヒル社１９８６年５月発行日経マ
イクロチバイセスｐ５３−５４に入力保護回路とし℃、
拡散抵抗と保護トランジスタ（ＭＯＳＦＥＴ）を組合せ
た回路が記載されている。Regarding electrostatic damage prevention technology for IC and LSI,
For example, an input protection circuit is added to the Nikkei Microchip Series p53-54 published by Nikkei McGraw-Hill in May 1986.
A circuit combining a diffused resistor and a protection transistor (MOSFET) is described.

本発明者はバイポーラＩＣに適用できる静電破壊防止技
術について検討した。第３図は公知とされた技術ではな
いが、本発明者により検討されたトランジスタのブレー
クダウン電圧（ＢＶＩＩＢ　）を利用した静電破壊防止
素子の一例を示す回路図である。The present inventor studied electrostatic damage prevention technology that can be applied to bipolar ICs. FIG. 3 is a circuit diagram showing an example of an electrostatic breakdown prevention element using the breakdown voltage (BVIIB) of a transistor, which was considered by the inventor of the present invention, although it is not a publicly known technique.

第４図は半導体基体の表面に形成された上記静電破壊防
止素子（ｎｐｎ　トランジスタ）、拡散抵抗を示す平面
図、第５図は同縦断面図である。１はコレクタとなるｎ
−型Ｓｉ基体（エピタキシャル層）でＶ。Ｃ電位に接続
される。２はベースｐ＋拡散抵抗でその一端はＡ２配線
を介し内部回路（ＩＣ）に接続される。３はエミッタｎ
＋拡散層でＡＡ配線を介し外端子（ＰＡＤ）に接続され
る。FIG. 4 is a plan view showing the electrostatic breakdown prevention element (NPN transistor) and the diffused resistor formed on the surface of the semiconductor substrate, and FIG. 5 is a longitudinal sectional view thereof. 1 is collector n
-V on type Si substrate (epitaxial layer). Connected to C potential. Reference numeral 2 denotes a base p+diffusion resistor, one end of which is connected to the internal circuit (IC) via the A2 wiring. 3 is emitter n
+ Connected to the external terminal (PAD) via the AA wiring in the diffusion layer.

このような静電破壊防止素子においては、外端子が←）
電位にあり−ｖｃｃからの電流はコレクタからペース抵
抗Ｒを経て内部回路に流れるが、ｖｃｃが高くなると、
トランジスタが動作して低い耐圧、小さいエネルギーで
ブレークダウンを起し静電破壊を防止できる。第７図は
小電流時（Ｉ）と、大電流時ＣＩ）の電流−電圧曲線を
示すものである。In such electrostatic damage prevention elements, the outer terminal is
The current from -vcc flows from the collector to the internal circuit via the pace resistor R, but as vcc rises,
The transistor operates and breaks down with low withstand voltage and low energy, preventing electrostatic damage. FIG. 7 shows current-voltage curves at a small current (I) and at a large current (CI).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した静電破壊防止手段においては、ペース抵抗Ｒは
高いはと有効であるがそのためにはペースｐ拡散の抵抗
長！を充分に長く形成しなければならない。しかし、一
方ではＩＣの集積化のためにペース抵抗の面積をむやみ
に太き（することはできない。In the above-mentioned electrostatic discharge prevention means, it is effective to have a high pace resistance R, but for this purpose, the resistance length of the diffusion of the pace P! must be formed sufficiently long. However, on the other hand, it is not possible to unnecessarily increase the area of the pace resistor in order to integrate the IC.

本発明は上記した点を考慮し℃なされたものであり、そ
の目的とするところは、少ない面積で破壊防止効果の大
きい静電破壊防止素子を提供することＫある。The present invention was developed in consideration of the above points, and an object thereof is to provide an electrostatic damage prevention element with a small area and a large destruction prevention effect.

本発明の前記ならびにそのほかの目的と新規な特徴は本
明細書の記述および添付図面からあきらかになろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔問題を解決するための手段〕[Means to solve the problem]

本願において開示される発明のうち代表的なものの概要
を簡単に説明丁れば下記のとおりである。A brief summary of typical inventions disclosed in this application is as follows.

すなわち、半導体基体の一生表面に内部回路を有し、上
記基体の一部に形成され、上記内部回路と外端子との間
に接続されたｎｐｎ）ランジスタと拡散抵抗とからなる
静電破壊防止用の半導体素子であり℃、上記ｎｐｎ　）
ランジスタのペース口拡散層の一部に中抜きのエミッタ
ｎ十拡散層が形成され、エミッタ拡散層直下のペース拡
散層により形成されるピンチ抵抗が上記拡散抵抗に用い
られるものである。That is, a semiconductor substrate has an internal circuit on its surface, and is formed on a part of the substrate and is connected between the internal circuit and an external terminal for preventing electrostatic damage, consisting of an NPN (npn) transistor and a diffused resistor. It is a semiconductor element of ℃, npn above)
A hollow emitter diffusion layer is formed in a part of the pace opening diffusion layer of the transistor, and a pinch resistor formed by the pace diffusion layer directly under the emitter diffusion layer is used as the diffusion resistor.

〔作用〕[Effect]

上記した手段によればピンチ抵抗を破壊防止の抵抗と用
いるために高抵抗が得られ小さい面積で有効な静電破壊
防止効果をもたせ、前記目的を達成できる。According to the above-mentioned means, since the pinch resistor is used as a resistance for preventing damage, a high resistance can be obtained, and an effective electrostatic damage prevention effect can be provided in a small area, thereby achieving the above object.

〔実施例〕〔Example〕

第１図は本発明の一実施例を示すものであって、ｎｐｎ
）ランジスタとピンチ抵抗とからなる静電破壊防止素子
の平面図であり、第２図はその縦断面図である。FIG. 1 shows an embodiment of the present invention, in which npn
) FIG. 2 is a plan view of an electrostatic breakdown prevention element consisting of a transistor and a pinch resistor, and FIG. 2 is a longitudinal sectional view thereof.

１は素子のコレクタとなるｎ−型Ｓｉ基体【エピタキシ
ャル層）であり、その一部はＶＣ６電位に接続される。Reference numeral 1 denotes an n-type Si substrate (epitaxial layer) which becomes the collector of the element, and a part of it is connected to the VC6 potential.

この基体の延長部分に図示されない内部回路（ＩＣ）が
形成される。An internal circuit (IC), not shown, is formed in the extended portion of this base.

２は素子のペースとなるｐ拡散層である。2 is a p-diffusion layer that serves as the base of the element.

３は素子のエミッタとなるｐ十拡散層であって、ペース
表面に中抜き状（ドーナツ状）に形成され、中央にベー
ス９層の一部が露出する。このエミッタｎ十拡散層と中
央のベース９層とを短絡するようにＡ！電極４が形成さ
れ、外端子（ＰＡＤ）と内部回路（ＩＣ）に人！配線に
より接続される。Reference numeral 3 denotes a p-type diffusion layer which serves as an emitter of the element, and is formed in a hollow shape (doughnut shape) on the surface of the paste, and a part of the base layer 9 is exposed at the center. A! so as to short-circuit this emitter n10 diffusion layer and the central base 9 layer. Electrode 4 is formed, and the external terminal (PAD) and internal circuit (IC) are connected! Connected by wiring.

５はコンタクト部である。5 is a contact portion.

このような静電破壊防止素子において、外端子（ＰＡＤ
　）に（−）パルスを印加した場合、ｎｐｎ）ランジス
タの耐圧ＢＶＣＥＲでブレークダウンし、この耐圧はｎ
ｐダイオードの耐圧ＢＶＣ８０より低いため、電流なり
ｃｃから供給しゃすくなり、内部回路を保護する。In such an electrostatic damage prevention element, the outer terminal (PAD
), the breakdown occurs at the withstand voltage BVCER of the npn) transistor, and this withstand voltage is n
Since the withstand voltage is lower than the P diode's breakdown voltage BVC80, it is easier to supply current or cc to protect the internal circuit.

通常、ブレークダウンはペースｐ拡散層の周辺角部で発
生しやすいが１本発明ではエミッタｎ＋拡散層の直下の
ｐ拡散層２ａはピンチ抵抗ｒを形成するためにρ８が高
（抵抗値ｒが高くなり、したがって第３図の保護回路を
形成することができる。したがって静電破壊防止効果が
高い。Normally, breakdown tends to occur at the peripheral corners of the pace p-diffusion layer, but in the present invention, the p-diffusion layer 2a directly under the emitter n+ diffusion layer has a high ρ8 (resistance value r) to form a pinch resistance r. Therefore, the protection circuit shown in Fig. 3 can be formed.Therefore, the effect of preventing electrostatic damage is high.

第６図は本発明による素子の初期ＣＩ）とブレークダウ
ン時（Ｉ）の電流−電圧曲線（降伏曲縁）を示すもので
ある。FIG. 6 shows the current-voltage curve (breakdown curve) at initial CI) and breakdown (I) of the device according to the present invention.

ベース拡散抵抗Ｒ−３００Ω、ピンチ抵抗ｒ−ＩＫΩと
した場合、下記のごと（なる。When the base diffusion resistance is R-300Ω and the pinch resistance r-IKΩ, the result is as follows.

このように本発明では同じペース面積でより低い電流で
降伏電圧を低下させることが０Ｔ能となる。Thus, in the present invention, the 0T capability is to lower the breakdown voltage with a lower current with the same pace area.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものでなく、その要旨を逸脱しない範囲で種々変更可能
である。Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.

本発明はリニア回路を有するＩＣ，ＬＳＩ一般に適用す
ることができ、とくに微細な素子形成に有効である。The present invention can be generally applied to ICs and LSIs having linear circuits, and is particularly effective in forming fine elements.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す静電破壊防止素子の平
面図。 第２図は第１図におけるＡ−Ａ視断面図である。 第３図は静電破壊防止素子の原理的構成を示す回路図で
ある。 第４図はこれまでの静電破壊防止素子の一例を示す平面
図、 第５図は第４図におけるＡ−Ａ視断面図である。 第６図及び第７図はブレークダウンの態様を示す１−Ｖ
曲線図であって、このうち、第６図は本発明の場合、第
７図は従来例である。 １・・・半導体基体、２・・・ペースｐ拡散層（抵抗）
、３・・・エミッタ拡散層、４・・・ＡＡ電極。 代理人　弁理士　　小　川　勝　男 第　　１　　図 ５−γソフト邪 第　　２　　図 第　　３　　図 （ｔ、Ｃ，） 第　　４　　図 、９FIG. 1 is a plan view of an electrostatic breakdown prevention element showing one embodiment of the present invention. FIG. 2 is a sectional view taken along the line AA in FIG. 1. FIG. 3 is a circuit diagram showing the basic structure of the electrostatic breakdown prevention element. FIG. 4 is a plan view showing an example of a conventional electrostatic breakdown prevention element, and FIG. 5 is a sectional view taken along line AA in FIG. 4. 6 and 7 are 1-V showing the breakdown mode.
These are curve diagrams, of which FIG. 6 is for the present invention and FIG. 7 is for the conventional example. 1... Semiconductor base, 2... Pace p diffusion layer (resistance)
, 3... Emitter diffusion layer, 4... AA electrode. Agent Patent Attorney Katsuo Ogawa No. 1 Figure 5 - Gamma Soft Evil No. 2 Figure 3 (t, C,) Figures 4, 9

Claims (1)

【特許請求の範囲】[Claims] １、半導体基体の一主表面に内部回路を有し、上記基体
の一部に形成され上記内部回路と外端子との間に接続さ
れたトランジスタと抵抗とからなる静電破壊防止用の半
導体素子であって、上記トランジスタのベース層の一部
に中抜きのエミッタ層が形成され、このエミッタ層直下
のベース層が上記抵抗に用いられていることを特徴とす
る静電破壊防止素子。２、上記エミッタ拡散層は中抜き
の部分でベース層と短絡し、基体の内部回路と外端子と
に接続されている特許請求の範囲第１項に記載の静電破
壊防止素子。1. A semiconductor element for preventing electrostatic damage, which has an internal circuit on one main surface of a semiconductor substrate, and includes a transistor and a resistor formed on a part of the substrate and connected between the internal circuit and an external terminal. An electrostatic breakdown prevention element characterized in that a hollow emitter layer is formed in a part of the base layer of the transistor, and the base layer directly under the emitter layer is used for the resistor. 2. The electrostatic breakdown prevention element according to claim 1, wherein the emitter diffusion layer is short-circuited to the base layer at the hollow portion and connected to the internal circuit of the base and the external terminal.
JP28173786A 1986-11-28 1986-11-28 Electrostatic breakdown preventive element Pending JPS63136658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28173786A JPS63136658A (en) 1986-11-28 1986-11-28 Electrostatic breakdown preventive element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28173786A JPS63136658A (en) 1986-11-28 1986-11-28 Electrostatic breakdown preventive element

Publications (1)

Publication Number Publication Date
JPS63136658A true JPS63136658A (en) 1988-06-08

Family

ID=17643280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28173786A Pending JPS63136658A (en) 1986-11-28 1986-11-28 Electrostatic breakdown preventive element

Country Status (1)

Country Link
JP (1) JPS63136658A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0234963A (en) * 1988-07-25 1990-02-05 Nec Corp Semiconductor integrated circuit
US5670819A (en) * 1993-11-15 1997-09-23 Kabushiki Kaisha Toshiba Semiconductor device with pad electrode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0234963A (en) * 1988-07-25 1990-02-05 Nec Corp Semiconductor integrated circuit
US5670819A (en) * 1993-11-15 1997-09-23 Kabushiki Kaisha Toshiba Semiconductor device with pad electrode

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