JPH02304964A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable potential difference between a diffusion layer and a well in each diffusion resistance to be equal for making equal the diffusion of a depletion layer and to enable resistance of each diffusion resistance to be held equally by forming each diffusion resistance at a plurality of wells which are provided independently at each semiconductor substrate. CONSTITUTION:A plurality of independent P wells 2A and 2B are formed at an N-type semiconductor substrate 1 and diffusion resistances 3 and 4 consisting of a diffusion layer where N-type impurities are diffused are formed at each P well 2A and 2B. Thus, in each of diffusion resistor 3 and 4, the difference in potential between the P wells 2A and 2B and the diffusion layer constituting the diffusion resistors 3 and 4 becomes equal and diffusion of depletion layers 3d1 and 4d1 becomes equal in each. Therefore, resistance R3 and R4 in each of diffusion resistors 3 and 4 becomes equal, potential at each connection point a can be accurately set to 1/2 VDD, and the depletion layers 3d1 and 4d1 of each diffusion resistors 3 and 4 can be set equally even if VDD is changed, thus enabling the value of the resistors R3 and R4 to be equally retained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device using a diffused resistor,
In particular, the present invention relates to a semiconductor integrated circuit device that divides voltage by connecting diffused resistors in series.

[Conventional technology]

A conventional structure in which a plurality of diffused resistors are formed on the same semiconductor substrate is shown in FIG. In the figure, 1 is an N-type semiconductor substrate, 2 is a P-well formed in this N-type semiconductor substrate 1, and two diffused resistors 3 and 4 in which N-type impurities are diffused are formed in this P-well 2. There is. In this configuration, even if the substrate potential V s u b changes, the potential of the P well 2 is fixed, so the spread of the depletion layer of the diffused resistor 3.4 is constant, and the resistance value of the diffused resistor 3.4 is constant. is maintained.

[Problems to be Solved by the Invention] When voltage is divided using the conventional diffused resistors described above, for example, as shown in FIG. When dividing the voltage to 1/2 VDD, as shown in FIG. 4, a 3.4-diffusion resistor is connected in series, and a voltage is applied to one end. The other end is grounded, and the partial voltage is taken out from the connection point a between the diffused resistors 3 and 4.

However, in the conventional configuration, the diffused resistors 3 and 4 are formed in one P-well 2, so in the above-mentioned wiring connection, the voltage applied to each of the diffused resistors 3 and 4 and the P-well 2 are A difference occurs in the potential difference between the diffusion resistance 3
, 4, the spread of each depletion layer 3d1°4dL is different. Therefore, the resistance values R,,R, are different, and a
The partial pressure at the point is correctly 1/2・■. be unable to do so.

In order to equalize the resistance values R, , R, of these diffused resistors 3.4, it is necessary to adjust the length of each diffused resistor 3.4. However, even with this adjustment, if VDD fluctuates, the depletion layer 3 dL + 4 dl will fluctuate, and the resistance value R,
, R, are different, and it is not necessarily effective.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device integrated circuit device that makes it possible to obtain a desired partial voltage by making the resistance values of a plurality of diffused resistors equal.

[Means for Solving the Problems] In the semiconductor integrated circuit device of the present invention, a plurality of independent wells are formed in a semiconductor substrate, and a diffused resistor is formed in each of these wells.

(Function) In the above-described configuration, it is possible to equalize the potential difference between the diffusion layer and the well in each diffused resistor, equalize the extent of the depletion layer in each, and equalize the resistance value.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the present invention.

In the figure, 1 is an N-type semiconductor substrate, and this N-type semiconductor substrate 1 has a plurality of independent P wells 2A,
2B is formed. In each of the P wells 2A and 2B, diffused resistors 3 and 4 made of diffusion layers in which N-type impurities are diffused are formed.

Then, in order to perform voltage division of vo using the diffused resistors 3 and 4 as shown in FIG. 3, the diffused resistors 3 and 4 are connected in series, and one end is connected to . . and ground the other end, 1/2·■, from the connection point a of the diffused resistors 3 and 4. is being taken out. However, in this wiring, the low potential side of each diffused resistor 3.4 is connected to the P wells 2A and 2B, respectively.

According to this configuration, in each diffused resistor 3.4, the diffused layer constituting the diffused resistor 3.4, the P well 2A,
2B, and therefore the depletion layer 3.2B in each becomes equal. The spread of 4dt becomes equal. Therefore, the resistance values Rs and Ra of each diffused resistor 3.4 are equal, and the potential at the eight connection points can be set correctly to 1/2.VDD.

In this configuration, ■. Even if the value is changed, each diffused resistance 3
．． The four depletion layers 3414 dl can be made equal to each other, and the resistance values R3 and R4 can be kept equal.

FIG. 2 is a sectional view of a second embodiment of the invention.

In this example, the voltage ■,. An example is shown in which the voltage is divided by three diffused resistors 3.4°5, and the diffused resistors 3 and 4°5 are formed in independent P wells 2A, 2B, and 2C, respectively. Then, connect the diffused resistors 3 and 4.5 in series between (Dl) and the ground, and connect them to point a or point b.

The partial pressure is obtained from each.

In this case as well, by connecting the low potential side of each diffused resistor 3, 4.5 to the P wells 2A, 2B, 2C, respectively, the spread of the depletion layer 3 at, 4 dl+5□ in each diffused resistor is made equal, Each resistance value R3, R-.

It becomes possible to make R6 equal.

In each of the above embodiments, an example was shown in which a P well was formed in an N type semiconductor substrate to form an N type diffused resistor, but it goes without saying that the structure may be of the opposite conductivity type. However, in this case ■. Of course, the connections are reversed.

〔Effect of the invention〕

As explained above, the present invention forms a diffused resistor in each of a plurality of wells independently provided in a semiconductor substrate, so that the potential difference between the diffused layer and the well in each diffused resistor is equalized. Make the spread of the depletion layer equal and set the resistance value of each diffused resistor to ■. It is possible to maintain the same voltage regardless of fluctuations in 0, etc., and has the effect of obtaining the required partial pressure.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a voltage dividing circuit.
FIG. 4 is a cross-sectional view of a conventional diffused resistor. 1...N-type semiconductor substrate, 2.2A, 2B, 2C...
・P well, 3, 4.5...diffused resistance.

Claims (1)

[Claims] 1. A semiconductor integrated circuit device in which a plurality of diffused resistors are formed on the same semiconductor substrate, characterized in that a plurality of independent wells are formed in the semiconductor substrate, and a diffused resistor is formed in each of these wells. Semiconductor integrated circuit device.