JPH02122545A - Method of designing semi-customized semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To secure the flexibility of setting of resistance and hence improve the degree of integration by arranging, according to necessary relative accuracy, a second resistance macro cell using a resistance element having resistance length shorter than a basic resistance element instead of a parallel circuit of the basic resistance element in a first resistance macro cell wherein there are combined the basic resistance elements of constant resistance length. CONSTITUTION:There are previously prepared for example a first 500OMEGA resistance macro cell wherein two 1kOMEGA resistance basic cells 103 are connected parallely through an electrode wiring 105, and a second 500OMEGA resistance macro cell wherein a distance between contact regions 106-1, 106-2 is reduced such that the resistance length is 1/2 the resistance length of the basic resistance element. Since voltage divider circuit is often used in analog integrated circuits where relative accuracy of resistance is required for good accuracy division, the first resistance macro cell is available. Further, since in an emitter follower circuit, the accuracy of a resistor R3 (=500OMEGA) is not severe, the second macro cell is available.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for integrating various types of semiconductor integrated circuits onto the same semiconductor substrate.
The present invention relates to a method for designing a semi-custom semiconductor integrated circuit, in particular a semi-custom semiconductor integrated circuit for analog circuits, which is realized by selecting and forming a wiring pattern using a base (base).

[Conventional technology]

Conventionally, in semi-custom semiconductor integrated circuits for analog use,
Similar to transistors, a semiconductor substrate (base) formed by arranging multiple basic cells of each resistance element, capacitance element, etc. is prepared in advance, and only the wiring design and wiring process after the contact formation process is performed. , semiconductor integrated circuits that meet predetermined specifications can be obtained in a short delivery time. Figure 4 shows the layer layer underneath the semi-custom semiconductor integrated circuit.
- In the figure, on a semiconductor chip 1 there are transistor basic cells 2. Resistance basic cell 3. A plurality of capacitor basic cells 4 are arranged. In analog circuits, it is necessary to construct resistance elements having various resistance values, but in the conventional semi-custom semiconductor integrated circuit design method, only one type of resistance macrocell is used.

Figure 5 is a layout diagram showing a conventional example of a resistor macrocell that achieves a desired resistance value simply by connecting resistor basic cells formed on the base in series or in parallel using wiring. is the contact area 6- to the resistor basic cell 3.
1.6-2 shows an example in which two resistive basic elements each connected to 82 electrode wirings 5 are connected in a row to form a resistive macrocell having a resistance value twice that of the resistive basic element, FIG. 5(b) shows an example in which two resistor macrocells are similarly connected in parallel to form a resistor macrocell having a resistance value that is half the resistance value of the resistor basic element.

FIG. 6 shows that the resistance length <1 can be achieved simply by changing the position of the contact with the underlying resistance basic cell. ,
FIG. 3 is a layout diagram illustrating a conventional example of a resistance macrocell that realizes a predetermined resistance value by changing eb). However, the electrode wiring is not nailed for convenience. For example, t2b =1! , /
2, the resistance value of the resistance macrocell shown in FIG. 6(b) is one half of the resistance value of the resistance macrocell shown in FIG. 6(a).

In this way, the conventional design method for semi-custom semiconductor integrated circuits uses a resistor macrocell, which is formed by connecting resistor basic elements with a fixed resistance length in series or parallel, and also uses a resistor macro cell, which is formed by connecting resistor basic elements with a fixed resistance length in series or parallel, and also changes the resistance by changing the contact position between the resistor basic cell and the wiring. There were two methods, one using resistive macrocells to realize different lengths.

[Problem to be solved by the invention]

However, in the conventional semi-custom semiconductor integrated circuit design method for analog circuits described above, only one type of resistor macrocell with a predetermined resistance value is used. In this method, there is a limit to the resolution of resistance value setting, and in order to achieve a low resistance value, many basic resistance elements must be connected in parallel, and many resistance basic cells are used, so it is not possible to achieve high integration. difficult to achieve.

(2) In the method of changing the resistance length depending on the contact position, for example, a voltage setting circuit using resistor voltage division,
In constant current setting circuits that use resistance value ratios, even when relative accuracy of the resistance is required, the resistance ratio between the resistance macrocells changes due to changes in the resistance length and contact resistance of each resistance macrocell, so it is difficult to maintain accuracy. Difficult to do well.

There is a drawback.

Accordingly, an object of the invention is to provide a method for designing a semi-custom semiconductor integrated circuit that has a degree of freedom in setting resistance values, improves the degree of integration, and satisfies the requirements for relative accuracy.

[Means to solve the problem]

The present invention provides a method for designing a semi-custom semiconductor integrated circuit in which a pair of electrode wirings are provided on an underlying resistive basic cell to realize a predetermined resistive element. and a second resistance macrocell using a resistance element whose resistance length is smaller than the basic resistance element in place of the parallel circuit of the basic resistance element in the first resistance macrocell is arranged according to the required relative accuracy. It is.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout diagram for explaining the first embodiment of the present invention, and FIG. 1(a) shows a basic cell 103 with a resistance of 1Ω.
, FIG. 1(b) shows a 500Ω first resistance macrocell in which two resistance basic cells 103 are connected in parallel by an electrode wiring 105, and FIG. 1(C) shows a resistance length of 1/1 of the basic resistance element in the contact process. 5, in which the distance between contact regions 106-1 and 106-2 is reduced so as to have a resistance length of 2.
A second resistance macrocell of 00Ω is shown.

The voltage divider circuit shown in FIG. 2(a) is often used in analog integrated circuits, but since accurate division requires relative precision of the resistors, the first resistor macrocell is used. The basic resistance element is set as Ω to R,=1, and R2=5
What is necessary is to use a first resistance macrocell in which two basic resistance elements are connected in parallel with a resistance of 00Ω.

In the emitter follower circuit shown in FIG. 2(b), the resistor R3
(=500Ω) accuracy is not so important, so the second macro cell may be used.

FIG. 3 is a layout diagram for explaining a second embodiment of the present invention. A basic resistance cell 203 made of a diffusion layer is formed on a semiconductor substrate as a base, and these resistances can be connected at the same time as the wiring process without changing the shape of the basic resistance cell formed on the base or the position of the contact area 206. In order to change the value, impurity ions are selectively implanted into the diffusion layer to form low resistance regions 207, 207'. Figure 3 (
1 shows a resistance basic cell of Ω, and FIG.
shows a 500Ω second resistance macrocell in which a low resistance region 207' is selectively added so that the resistance length is 1/2 that of the basic resistance element.

In the above embodiments, the resistance length of the second resistance macrocell was set to 1/2 that of the basic resistance element, but it was set to 1/2.1/3.1.
/4 may also be used.

〔Effect of the invention〕

As explained above, according to the present invention, by selecting macro cells with resistance elements suitable for required circuit characteristics on the same wiring design, resistance macro cells with a high degree of freedom in setting resistance values and with a small number of elements are used. By connecting basic resistance elements in series and parallel, it is possible to use a resistance macrocell with high relative accuracy with other resistance macrocells.
The macrocell is selected according to the usage conditions of the resistance element in each circuit, and the effect is that the number of basic resistance cells can be reduced and the relative accuracy requirements of the resistance can be met at the same time.

[Brief explanation of the drawing]

FIGS. 1(a), (b), and (C) are layout diagrams of a basic resistance cell, a first resistance macrocell, and a second resistance macrocell, respectively, for explaining the first embodiment of the present invention;
FIG. 2(a) is a circuit diagram of a voltage divider circuit, FIG. 2(b) is a circuit diagram of an emitter follower circuit, and FIGS. 3(a>, (b) and (c) are respectively a second embodiment of the present invention. A layout diagram of a basic resistance cell, a first resistance macrocell, and a second resistance macrocell for explaining an example; FIG. 4 is a layout diagram of the base of a semi-custom semiconductor integrated circuit; FIGS. 5(a) and (b) 6(a) and 6(b) are layout diagrams of a resistor macrocell in which basic resistance elements are connected in series and a resistance macrocell in parallel, respectively, and FIGS. 6(a) and (b) are resistors in which the distance between the basic resistance element and the contact area is shorter than that of the basic resistance element, respectively. It is a layout diagram of a macro cell. 1... Semiconductor chip, 2... Transistor basic cell, 3, 103, 203... Resistor basic cell, 4... Capacitor basic cell, 5, 105, 205... Electrode wiring, 6.6-1.6-2.6'-1,6'-2゜106
．． 106-1, 106-2, 206... contact region, 207, 207'... low resistance region. Agent Patent Attorney Susumu Uchihara (α) (b) (C) (Ol) (b) ? U1

Claims (1)

[Claims] A method for designing a semi-custom semiconductor integrated circuit in which a pair of electrode wirings are provided on an underlying resistance basic cell to realize a predetermined resistance element, a first resistance macrocell combining basic resistance elements with a constant resistance length; In place of the parallel circuit of the basic resistance elements in the resistance macrocell, second resistance macrocells each using a resistance element having a resistance length smaller than that of the basic resistance element are arranged according to the required relative accuracy. How to design custom semiconductor integrated circuits.