JPH09260597A - Semiconductor circuit and manufacture of semiconductor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain variation of output characteristic by constituting a direction of a main current path of a semiconductor element to become a specific surface orientation of semiconductor crystal which forms a semiconductor element. SOLUTION: An orientation flat is provided in a silicon wafer 1 and is formed along a surface orientation <100>. In an integrated circuit pattern 2, an orientation flat is provided along a surface orientation <100> in the silicon wafer 1 and is formed to make a side (a) parallel to an orientation flat. A direction of a main current path of a band gap element is made a surface orientation <110> of the silicon wafer 1 and unit patterns 4, 5 are formed so as to have an angle of 45 deg. to an orientation flat. Therefore, it is possible to restrain output characteristic from varying even if outer environment changes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit which suppresses the influence of external environmental changes such as stress application and a method for manufacturing the same, and in particular, it is incorporated in an A / D converter, a D / A converter, etc. The present invention relates to a technique suitable for being applied to a bandgap reference circuit that constitutes a reference voltage generation unit that supplies a voltage.

[0002]

2. Description of the Related Art In order to improve the accuracy of electronic devices such as A / D converters and D / A converters, a reference voltage generator for supplying a stable reference voltage is built in the electronic devices. It is necessary to make the composition.

In order to supply a stable reference voltage, the reference voltage generator has excellent environmental resistance, that is, the external environmental conditions such as externally applied voltage, temperature, and humidity vary. However, it must be manufactured so that a stable reference voltage can be supplied. Therefore, as explained below,
A bandgap reference circuit that supplies the above-mentioned reference voltage using a bandgap voltage is generally used.

Now, an example of a conventional bandgap reference circuit will be described with reference to the drawings. The bandgap reference circuit is a circuit configured to output a constant voltage by canceling an output having a negative temperature coefficient and an output having a positive temperature coefficient by using a bandgap voltage. . Here, the band gap voltage is a value peculiar to a substance at an absolute temperature of 0 degree, and is, for example, about 1.2 (V) in silicon, and this value has a negative temperature coefficient.

The junction voltage of the PN junction is determined by the bandgap voltage, the impurity density, the diffusion coefficient, the diffusion distance, etc., but the influence of the bandgap voltage is dominant, so that in the semiconductor circuit, Most commonly, the bandgap voltage is extracted by utilizing the junction voltage of the PN junction. Therefore, for ease of understanding, description will be made here on the assumption that the junction voltage of the PN junction is used.

Further, herein, a pair of semiconductor elements having a PN junction, which is a constituent element of the bandgap reference circuit and has a current mirror ratio of a predetermined value, will be referred to as a bandgap element.

FIG. 4 shows a CMO for a P-type silicon substrate.
It is a circuit diagram which shows the general structural example of the conventional band cap reference circuit manufactured by applying the S manufacturing process.

Q ₁ and Q ₂ are a pair of bandgap elements having a current mirror ratio of "1: N", both of which are PNP bipolar transistors. Such a current mirror ratio can be set by manufacturing the emitter area by adjusting the ratio.

The base terminals of Q ₁ and Q ₂ are connected to each other and grounded (ground voltage: V _SS ), and each collector terminal is also grounded (ground voltage: V _SS ). Further, Q ₃ and Q ₄ are composed of a pair of PMOS transistors having the same structure, the current mirror ratio is “1: 1”, and each drain terminal is a power supply terminal (power supply voltage: V _DD ) and each source terminal is
It is connected to a resistor R ₂ having the same resistance value.

Further, the output terminal of the operational amplifier A1 is Q
₃ and Q ₄ are connected to the respective gate terminals, and the inverting and non-inverting terminals of the operational amplifier A1 are connected to one end of the resistor R ₂ connected to Q ₃ and the resistor R ₂ connected to Q ₄ , respectively. ing.

Here, the PMOS transistor Q ₃ , PM
The feedback loop constituted by the OS transistor Q ₄ , the two resistors R ₂ and the operational amplifier A1 is the operational amplifier A
Since it forms the negative feedback loop of 1, the operational amplifier A1
Becomes a virtual ground state, the voltage difference between the inverting terminal and the non-inverting terminal becomes zero, and the points A and B have the same potential.

That is, the negative feedback loop acts so that the current I having the same value flows through Q ₁ and Q ₂ . Therefore,
The difference ΔV _BE between the _BE junction voltages of Q ₁ and Q ₂ occurs in the resistor R ₁ . Here, ΔV _BE is the current of Q ₁ and Q ₂ , I ₁ ,
When _{I 2, ΔV BE = kTln (} I 2 / I 1) / q,
It is known that, and now I ₂ / I ₁ = N,
ΔV _BE = kTlnN / q.

Here, k is Boltzmann's constant and T is
Absolute temperature, ln is natural logarithm, and q is electronic charge. Sa
At this time, the output voltage of the bandgap reference circuit
Pressure V_OUTIs "V_{OU T}= -V_BE2+ ((R₁+ R_Two) /
R₁) ・ ΔV_BETherefore, the resistance ratio “(R₁+ R
_Two) / R₁] And the current density ratio N are set to appropriate values.
By doing, Q _TwoBase-emitter voltage V_BE2The negative of
Temperature coefficient and ΔV_BECancel the positive temperature coefficient of
Output that is stable against fluctuations in power
A bandgap reference circuit can be realized.

Here, PN is used as the bandgap element.
Although a configuration example using the P bipolar transistor is shown, a circuit configuration using an NPN bipolar transistor, a PN diode, etc. is also proposed.

There are various possible configurations of the feedback loop and the entire circuit depending on the type of the manufacturing process of the circuit and the intended use, but a positive temperature coefficient due to the difference in the junction voltage between the bandgap elements is considered. Since the basic principle of canceling the negative temperature coefficient of the junction voltage of the bandgap element itself or another semiconductor element constituting the circuit by using the same does not change, description of other bandgap reference circuits will be omitted.

Now, in order to realize the bandgap reference circuit as an integrated circuit so as not to cause the characteristic deterioration due to the variation in the manufacturing process, etc., the above-mentioned pair of bandgap elements (PNP in the above example) is realized. The important point is how to realize the circuit so that the current mirror ratio of the bipolar transistor) is as designed.

Therefore, special attention is paid to the manufacture of the pattern of the band cap element. The conventional pattern manufacturing of the band cap element will be described with reference to FIG.

Reference numeral 1 in the drawing denotes a silicon wafer to which a P substrate CMOS process can be applied. The silicon wafer 1 is provided with an orientation flat (hereinafter referred to as “orientation flat”) to indicate the direction of the wafer, and C
In a MOS process wafer, the orientation flat is usually formed along the plane direction <100>.

A large number of integrated circuit patterns 2 are formed on the silicon wafer 1, and the integrated circuit patterns 2 are formed.
Is a circuit pattern including a band cap reference circuit. As can be seen from the figure, the integrated circuit pattern 2 is configured so that its outer shape is usually a quadrangle, and a large number of integrated circuit patterns 2 are formed so that the side a is parallel to the orientation flat.

Reference numeral 3 is a bandgap reference circuit pattern formed in the integrated circuit pattern 2, and reference numerals 4 and 5 are unit element patterns (unit patterns) constituting a pair of bandgap elements. Usually, the pattern of each unit pattern is formed to have a square outer shape.

Now, the unit patterns 4 and 5 are respectively shown in FIG.
Assuming that the unit for Q ₁ and the unit for Q ₂ shown in (4) are arranged with eight Q ₂ units 5 centered around _one Q ₁ unit 4, the current density ratio is 1:
A pair of bandgap elements of 8 "are realized.

By arranging the Q ₂ units 5 symmetrically with respect to the Q ₁ unit 4 as a center, a device for suppressing deterioration of characteristics due to variations in the manufacturing process is made. There is.

The unit patterns 4 and 5 constituting the bandgap element are usually constructed such that the main current path thereof is parallel to the orientation flat, that is, the main current path of the bandgap element is the plane direction <100>.

Here, the main current path of the bandgap element will be described with reference to FIG. FIG.
FIG. 3 is a drawing showing an actual semiconductor element structure of a Q ₁ unit 4 (or a Q ₂ unit 5).

An n well layer forming a base region and ap + layer forming a collector electrode are provided on the p substrate forming the collector region, and an emitter region is formed above the n well layer. An n + layer that forms the p + layer and the base electrode is provided.

The p + layer (emitter) as a whole,
P consisting of an n-well layer (base) and a p substrate (collector)
It operates as an NP bipolar transistor, and a base current and a collector current flow from the emitter to the base and collector respectively.

For the sake of convenience of description, only the current flowing on the base and collector sides on the left side of the figure with respect to the emitter is shown. By the way, the current path illustrated in the semiconductor cross-sectional view is a path as indicated by a in the figure when viewed from the upper surface side of the unit pattern 4 (5). Considering the symmetry of the unit pattern, such a path may be replaced by b, c,
There is one as shown by d.

Thus, in the bandgap element having the PN junction, the path in which the carriers flow most is called the main current path. Conventionally, the direction of the main current path of the bandgap element is the plane of the semiconductor crystal. Direction <100
> Was configured.

[0029]

By the way, in recent years, with the increase in the scale of integrated circuits and the reduction in size of packages for mounting large scale integrated circuits, package stress caused by changes in external environmental conditions such as temperature and humidity. caused by,
In many cases, characteristic fluctuations of integrated circuits have become a new problem.

Originally, in a bandgap reference circuit which is required to have stable output characteristics even if the external environmental conditions fluctuate, the output should be stable especially when package stress is applied. There is a need to improve performance.

Therefore, in view of the above problems, an object of the present invention is to improve the pattern forming process, and in particular, to suppress the output fluctuation caused by the package stress caused by the fluctuation of the external environmental conditions such as temperature. It is to realize a gap reference circuit.

[0032]

In order to solve the above problems and to achieve the object of the present invention, the invention according to claim 1 has a pair of semiconductor elements having a current mirror ratio of a predetermined value, A bandgap reference circuit configured to output a voltage, wherein a direction of a main current path of the semiconductor element is a surface direction <110 of a semiconductor crystal forming the semiconductor element.
> (110 indicates a Miller index) is a semiconductor circuit.

Further, the invention according to claim 2 is characterized in that, in claim 1, the semiconductor element is configured to have a PN junction, and the main current path is a movement path through which carriers most flow. Is a semiconductor circuit.

According to another aspect of the present invention, the following method is also conceivable. That is, the invention according to claim 3 has a bandgap reference circuit, which has a pair of semiconductor elements having a current mirror ratio of a predetermined value and is configured to output a constant voltage, on a semiconductor wafer made of a semiconductor crystal. In the method, the main current path of the semiconductor element has a direction <1.
A method of manufacturing a semiconductor circuit, which includes a step of forming the semiconductor element on the semiconductor wafer so that 10> (110 indicates a Miller index).

Further, the invention according to claim 4 is characterized in that, in claim 3, the semiconductor element is configured to have a PN junction, and the main current path is a movement path through which carriers most flow. And a method of manufacturing a semiconductor circuit.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In each embodiment, how to form the pattern of the bandgap element forming the bandgap reference circuit shown in FIG. 4 will be described, and the features of each embodiment will be described.

FIG. 1 is an explanatory view for explaining a pattern formation state of a pair of band gap elements, which is a first embodiment according to the present invention. 1 is a P substrate CMOS
It is a silicon wafer to which the process can be applied. The silicon wafer 1 is provided with an orientation flat to indicate the direction of the wafer, and the orientation flat is formed along the surface direction <100>.

A large number of integrated circuit patterns 2 are formed on the silicon wafer 1, and the integrated circuit patterns 2 are formed.
Is a circuit pattern including a band cap reference circuit. As can be seen from the drawing, the integrated circuit pattern 2 is configured so that its outer shape is usually a quadrangle, and a large number of integrated circuit patterns 2 are formed so that the side a is parallel to the orientation flat.

Reference numeral 3 is a bandgap reference circuit pattern formed in the integrated circuit pattern 2, and reference numerals 4 and 5 are unit element patterns (unit patterns) constituting a pair of bandgap elements. Usually, the pattern of each unit pattern is formed to have a square outer shape.

Now, the unit patterns 4 and 5 are respectively shown in FIG.
Assuming that the unit for Q ₁ and the unit for Q ₂ shown in (1) are arranged with eight Q ₂ units 5 around _one Q ₁ unit 4, the current mirror ratio becomes “1”. :
A pair of bandgap elements of 8 "are realized.

The features of this embodiment are as follows.
That is, first, the surface direction <10 with respect to the silicon wafer 1.
0> is provided along the orientation flat so that the integrated circuit pattern 2
The integrated circuit pattern 2 is formed such that the side a forming the outer shape of the integrated circuit pattern is parallel to the orientation flat. At that time, the main current path of the bandgap element included in the bandgap reference circuit included in the integrated circuit pattern 2 is formed. The direction of
The unit patterns 4 and 5 are formed so as to have a plane direction <110> of the silicon wafer 1, that is, an angle of 45 degrees with respect to the orientation flat.

As a result, the bandgap reference circuit pattern 3 is formed such that the direction of the main current path flowing inside the bandgap element is the surface direction <110> of the silicon wafer 1, and the output fluctuation caused by the package stress. A bandgap reference circuit that can suppress the Note that this means that the direction of the main current path of the bandgap element is such that the surface direction of the silicon wafer 1 <
By patterning so that 110>,
It is considered that this is because the component of the diffusion layer resistance existing between the emitter and the base and the like for the stress fluctuation becomes extremely small.

Next, FIG. 2 is an explanatory view for explaining a pattern formation state of a pair of bandgap elements which is a second embodiment according to the present invention. For ease of understanding, the same parts as those in FIG. 1 are designated by the same reference numerals and detailed description will not be given.

In the present embodiment, the orientation flat is formed on the silicon wafer 1 so as to indicate the direction of the wafer 1. However, on the silicon wafer 1, a large number of integrated circuits are formed. The pattern 2 is formed such that its side a forms an angle of 45 degrees with the orientation flat.

The features of this embodiment are as follows. That is, first, with respect to the silicon wafer 1, the surface direction <100
The orientation flat is provided so as to satisfy the condition>, and the integrated circuit pattern 2 is formed so that the side a that constitutes the outer shape of the integrated circuit pattern 2 forms an angle of 45 degrees with the orientation flat. The unit patterns 4 and 5 are formed such that the direction of the main current path of the bandgap element forming the bandgap reference circuit is <110> in the plane direction of the silicon wafer 1, that is, an angle of 45 degrees with the orientation flat. To do.

As a result, the bandgap reference circuit pattern 3 is formed such that the direction of the main current path flowing inside the bandgap element is the surface direction <110> of the silicon wafer 1, and the output fluctuation caused by the package stress. A bandgap reference circuit that can suppress the

In this embodiment, the mask used for forming the conventional mask pattern described in FIG. 5 can be used as it is. That is, at the stage of forming the integrated circuit pattern 2 on the silicon wafer 1, it is only necessary to incline the mask itself with respect to the orientation flat by 45 degrees or to install the silicon wafer 1 itself with an inclination of 45 degrees to form a pattern. .

Next, it is an explanatory view for explaining a pattern formation state of a pair of bandgap elements which is a third embodiment according to the present invention. For ease of understanding, the same parts as those in FIG. 1 are designated by the same reference numerals and detailed description will not be given.

In this embodiment, in order to show the wafer direction on the silicon wafer 1, the orientation flat is formed along the surface direction <110>, and a large number of integrated circuit patterns are formed on the silicon wafer 1. 2 is formed such that its side a is parallel to the orientation flat.

The features of this embodiment are as follows. That is, first, the surface direction <110 with respect to the silicon wafer 1.
The orientation flat is provided so as to satisfy the condition>, and the integrated circuit pattern 2 is formed so that the side a that forms the outer shape of the integrated circuit pattern 2 is parallel to the orientation flat, and at that time, the band gap included in the integrated circuit pattern 2 is formed. The unit patterns 4 and 5 are formed so that the direction of the main current path of the bandgap element forming the reference circuit is parallel to the plane direction <110> of the silicon wafer 1, that is, the orientation flat.

As a result, the bandgap reference circuit pattern 3 is formed so that the direction of the main current path flowing inside the bandgap element is the surface direction <110> of the silicon wafer 1, and the output fluctuation caused by the package stress is generated. A bandgap reference circuit that can suppress the

Also in the present embodiment, the mask used for forming the conventional mask pattern described in FIG. 5 is used as it is, and only by changing the wafer processing method, the main current path flowing inside the bandgap element is changed. Since the direction can be the plane direction <110>, the conventional band gap reference circuit and the integrated circuit including the same can be improved and easily manufactured.

In the above embodiments, the extremely basic bandgap reference circuit in which the PNP bipolar transistor is used as the bandgap element as shown in FIG. 4 has been described as an example. Depends on the substrate type (P-type, N-type), process type (CMOS, bipolar), bandgap element type (vertical NPN bipolar transistor, lateral PNP bipolar transistor, bulk PNP bipolar transistor, etc.) and circuit configuration mode. Without
Widely applicable to general bandgap reference circuits.

The effect of the application of the present invention is that most of the current paths in the bandgap element are in the plane direction <11.
It appears most significantly with respect to the lateral bandgap element with 0>, but in other cases, the effect is recognized also with respect to the vertical bandgap element, for example.

As described above, according to the present invention, attention is paid to the direction of the main current path flowing inside the pair of bandgap elements in which the current mirror ratio has a predetermined value, and the direction is the plane direction <
By forming a pattern so that 110>,
A band cap reference circuit with excellent environmental resistance that can suppress changes in output characteristics even if the external environment changes due to external stress applied,
It can be realized quite simply by improving the prior art.

[0056]

As described above, according to the first and second aspects.
According to the described invention, the direction of the main current path of the bandgap reference element is the plane direction <110> of the semiconductor crystal.
With such a configuration, it is possible to realize a bandgap reference circuit that suppresses changes in output characteristics even when the external environment changes due to external stress applied.

According to the invention described in claims 3 and 4,
Since the step of forming the bandgap reference circuit on the semiconductor wafer is included so that the plane direction <110> of the semiconductor crystal is the direction of the main current path of the bandgap element, stress or the like is externally applied. As a result, it is possible to realize a method of manufacturing a semiconductor circuit that suppresses changes in output characteristics even when the external environment changes.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a second embodiment of the present invention.

FIG. 3 is an explanatory diagram of a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a band gap reference circuit.

FIG. 5 is an explanatory diagram of a conventional band gap reference circuit and integrated circuit pattern generation including the same.

FIG. 6 is an explanatory diagram of a main current path.

[Explanation of symbols]

 1 silicon wafer 2 integrated circuit pattern 3 bandgap reference circuit pattern 4 unit pattern forming a bandgap element 5 unit pattern forming a bandgap element

Claims (4)

[Claims] 1. A bandgap reference circuit having a pair of semiconductor elements having a current mirror ratio of a predetermined value and configured to output a constant voltage, wherein a direction of a main current path of the semiconductor element is The semiconductor circuit is configured to have a plane direction <110> (110 indicates a Miller index) of a semiconductor crystal forming a semiconductor element. 2. The semiconductor element according to claim 1,
A semiconductor circuit having a PN junction, wherein the main current path is a moving path through which carriers most flow. 3. A method of forming a bandgap reference circuit, which has a pair of semiconductor elements having a current mirror ratio of a predetermined value and is configured to output a constant voltage, on a semiconductor wafer made of a semiconductor crystal. The semiconductor element is formed on the semiconductor wafer so that the direction of the main current path of the semiconductor element is the plane direction <110> (110 indicates Miller index) of the semiconductor crystal forming the semiconductor element. A method of manufacturing a semiconductor circuit, including the step of: 4. The semiconductor element according to claim 3,
A method of manufacturing a semiconductor circuit, comprising a PN junction, wherein the main current path is a moving path through which carriers most flow.