JP4857834B2 - Input protection circuit - Google Patents

Description

  The present invention relates to an input protection circuit for protecting an internal circuit from being destroyed when a surge voltage is applied to an input terminal.

FIG. 10 shows a configuration example of an input protection circuit for protecting the internal circuit from being destroyed when a surge voltage is applied to the input terminal of the semiconductor integrated circuit. Input terminals 1 and 2 of the semiconductor integrated circuit are connected to internal circuits 3 and 4, respectively. The internal circuits 3 and 4 are, for example, a transistor, an operational amplifier, a comparator, or the like. The anodes of the diodes 5 and 6 (D1 and D2) are connected to the input terminals 1 and 2, respectively, and the cathodes of the diodes 7 and 8 (D4 and D5) are connected to the input terminals 1 and 2, respectively.
The anodes of the diodes 7 and 8 are connected to the circuit ground, and the cathodes of the diodes 5 and 6 are connected to the circuit ground via the drain and source of an N-channel LD (Lateral Diffused) MOSFET 9 (Q1). A Zener diode 10 is connected between the drain and gate of the FET 9, and a resistor 11 (R1) is connected between the gate and source. The above constitutes the input protection circuit 12.

When a positive surge voltage is applied to the input terminal 1 or 2 and the voltage applied to the Zener diode 10 exceeds the Zener voltage VZ, the Zener diode 10 becomes conductive and a terminal voltage is generated in the resistor 11, and the FET 9 Turns on. Then, since a surge current flows from the input terminal 1 or 2 to the circuit ground via the FET 9, the internal circuit 3 or 4 can be protected.
Patent Document 1 discloses a configuration in which when the protection circuit shown in FIG. 10 is provided for each of a plurality of input terminals, they are operated in a connected state.
Special table 2003-530698 gazette

  According to the input protection circuit 12 configured as described above, a protection operation is possible against the application of a positive surge voltage. For example, in an IC such as an ECU (Electronic Control Unit) mounted on a vehicle, When a negative surge voltage such as field decay is applied, it cannot be protected. Assuming that the above configuration is simply applied to a negative surge, the configuration shown in FIG. 11 is obtained. That is, FIG. 11 shows only the input terminal 1, but an N-channel LDMOSFET 13 is connected between the circuit ground and the anode of the diode 7, and a Zener diode 14 (D6) between the drain and gate of the FET 13 and between the gate and source. A resistor 15 (R2) is connected.

However, even if the circuit as described above is provided, when each circuit element is formed by PN junction isolation when the entire circuit is integrated, a parasitic diode 7a is formed in the diode 7 for preventing backflow between the terminals. (See FIG. 12). Therefore, when a negative surge voltage (for example, about −100 V) is applied to the input terminal 1, a surge current flows from the ground via the parasitic diode 7a, so that the FET 14 constituting the input protection circuit is not turned ON. .
In this case, since the parasitic diode 7a cannot withstand such a large current, it may be thermally destroyed. Under such circumstances, it is difficult to make an IC including a protection circuit corresponding to a negative-polarity surge voltage conventionally, and protection measures are separately performed using an external discrete element. As a result, there is a problem in that the entire circuit is enlarged and the cost is increased.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an input protection circuit capable of protecting an internal circuit even when a negative surge voltage is applied to an input terminal.

According to the input protection circuit of claim 1, the second diode and the second clamp circuit for performing a protection operation when a negative surge voltage is applied to the input terminal, each circuit element is connected to the other The circuit element is formed in a region insulated from the formation region of the circuit element. Therefore, the parasitic diode as in the case of forming by PN junction isolation is not formed in each circuit element, and when a negative surge voltage is applied, the second clamp circuit operates, and from the circuit ground Since a surge current flows by forming a current path to the input terminal, the internal circuit can be protected.
When a positive or negative surge voltage is applied to the input terminal, the first and second bias circuits turn on the first and second transistors, respectively, and a current path from the circuit ground to the input terminal is established. Since it is formed, a larger surge current can flow through the first and second transistors.
In addition, the first and second transistors are arranged in a region on the outermost side on the substrate, and the input terminal is arranged between the first and second transistors and the internal circuit. That is, when the configuration of the present invention is adopted, the first and second diodes and the internal circuit are connected to the input terminal, and the first and second transistors are arranged in the region where the input terminal and the internal circuit are arranged. If it is arranged between the two, the wiring between the input terminal and the internal circuit needs to be detoured around the transistor arrangement region.
Therefore, if the transistor is disposed on the outermost peripheral side, the wiring connection between the input terminal, the diode and the internal circuit can be facilitated, and the wiring between the transistor and the diode can be made between the input terminal pads. Therefore, the entire wiring becomes easy and an increase in chip size can be suppressed.

  According to the input protection circuit of the second aspect, since each circuit element is formed in the trench-isolated region by the insulating film material on the SOI substrate, the formation region of each element can be reliably insulated.

According to the input protection circuit of the third aspect , since a plurality of first and second clamp circuits are connected in series, it is possible to cope with a case where a surge voltage of a larger level is applied.
According to the input protection circuit of claim 4, since a plurality of the first and second clamp circuits are connected in parallel, the current withstand capability is improved, and a larger surge current can flow when a surge voltage is applied. it can.

(First embodiment)
A first embodiment in which the present invention is applied to an IC mounted on a vehicle will be described below with reference to FIGS. The same parts as those in FIGS. 10 and 11 are denoted by the same reference numerals and description thereof is omitted, and only different parts are described below. The input protection circuit 21 of the present embodiment forms the circuit shown in FIG. 10 in a region where trench isolation is performed by an insulating film material on an SOI (Silicon On Insulator) substrate.

FIG. 2 shows, for example, the structure near the diode 7 (second diode) by a schematic cross section of a semiconductor substrate. An SiO2 film 23 as an isolation layer is formed on a P-type silicon substrate 22 as a support substrate, and an N ^- silicon layer 24 is formed thereon, and these constitute an SOI substrate 25. . Then, a P-type region 26 and an N-type region 27 are formed in the surface layer portion of the SOI substrate 25, and the diode 7 is configured.

The diode 7 and other circuit elements are electrically isolated (insulated) by a trench element isolation structure. In the trench isolation structure, first, a narrow trench (groove) 28 is formed by etching around the diode 7 so as to penetrate the N ⁻ layer 24 and reach the SiO 2 film 23. Next, the inner side is oxidized and covered with an SiO2 film (insulating film material) (not shown), and the trench 28 is filled with polysilicon (insulating film material) 29 or the like. Since the SiO2 films 23 and 29 separating the elements and between the elements and the P-type silicon substrate 22 are high-quality insulators, the leakage current flowing through them is extremely small.

  Note that the Zener voltage of the Zener diodes 10 and 14 (first and second bias circuits) is set to about 60 to 70 V, for example. A set of the FET 9 (first transistor), the Zener diode 10 (first bias circuit), and the resistance element 11 (first bias circuit) is referred to as a clamp circuit 42P (first clamp circuit), and the FET 13, the Zener diode 14, and the resistor The set of the elements 15 is referred to as a clamp circuit 42N (second clamp circuit).

  Next, the operation of this embodiment will be described. The circuit operation when a positive surge voltage is applied is exactly the same as that of the input protection circuit 12 shown in FIG. On the other hand, when a negative surge voltage such as field decay generated for an electronic circuit mounted on the vehicle is applied to the input terminal 1, the Zener diode 14 is turned on and the resistance element 15 (second bias circuit) ) To generate a voltage at both ends. Then, since the FET 13 (second transistor) is turned on, a current path from the circuit ground to the input terminal 1 via the FET 13 and the diode 7 is formed, and a surge current flows. At this time, since the surge voltage is clamped by the Zener voltage of the Zener diode 14 and the terminal voltage of the resistance element 15, the internal circuit 3 is protected.

As described above, according to the present embodiment, each circuit element constituting the input protection circuit 21 is formed in the region formed by trench isolation on the SOI substrate 25, so that it is formed by PN junction isolation. Such a parasitic transistor is not formed, and the formation region of each element can be reliably insulated.
When a negative surge voltage is applied to the input terminal 1, the Zener diode 14 constituting the clamp circuit 42N is turned on to turn on the FET 13, thereby forming a current path from the circuit ground to the input terminal 1. The internal circuit 3 can be protected. Therefore, the entire input protection circuit 21 can be easily integrated, and the cost can be reduced without increasing the circuit size. Also, a relatively large surge current can flow through the FET 13 during the clamping operation.

(Second embodiment)
3 to 6 show a second embodiment of the present invention, and different portions from the first embodiment will be described. In the second embodiment, when the input protection circuit 21 is integrated into an IC, the circuit arrangement (layout) of each element is characterized.

Here, FIG. 5 and FIG. 6 show a case where the input protection circuit 21 is integrated into an IC according to a circuit arrangement that is generally performed. In the IC chip 31, pads 32 a and 32 b corresponding to the input terminals 1 and 2 are arranged on the outermost peripheral part (left side and upper side part in the figure) of the chip 31 for wire bonding, and the internal circuit region 33 is located on the inner side thereof. Placed in. And it is preferable to make the wiring which becomes the surge absorption path as thick and short as possible.
Accordingly, between the pad 32a and the left side of the internal circuit region 33, the formation region 34a such as the diodes 5 to 7 and the formation region 35a such as the plus surge absorbing FET 9 are arranged side by side. On the other hand, between the pad 32b and the upper side of the internal circuit region 33, a diode forming region 34b and a forming region 35b such as a negative surge absorbing FET 13 are disposed.

  FIG. 6 shows only the portion corresponding to FIG. 1 in the arrangement of FIG. The wirings L1 and L2 extending from the pad 32a need to be connected to the internal circuit region 33 beyond the FET forming region 35a after being connected to the diode in the diode forming region 34a. There is no problem if a sufficient wiring layer can be prepared. However, if the degree of freedom of wiring is limited and the FET formation region 35a cannot be directly straddled, the wires L1 and L2 bypass the region 35a. Need to be routed. That is, in this case, the chip size has to be increased in order to secure an extra space for the wirings L1 and L2. Since the same space is required for the other pads 32, the size of the IC chip 31 increases as the number of input terminals increases.

  Therefore, in the IC chip 41 of the second embodiment, as shown in FIG. 3, the FET formation regions 35 a and 35 b are arranged on the outermost peripheral portion, and the pad 32 and the diode formation region 34 are provided between the internal circuit region 33. Deploy. When such an arrangement is adopted, as shown in FIG. 4, the wiring extending from the pad 32a (input terminal 1) is directly connected to the internal circuit region 33 (internal circuit) via the diode formation region 34a (diodes 5 and 7). It becomes possible to connect to 3).

  In this case, the diode formation region 34a and the FET formation region 35a are separated from each other, but the wiring between them can be performed between the pads 32a. Further, although the spacing between the pads 32a is narrow, it is possible to ensure current withstand capability by providing a plurality of wirings with the common connection point of the diode as shown in FIG. Then, wire bonding between the pad 32a and a lead (not shown) may be performed by skipping the FET formation region 35.

  As described above, according to the second embodiment, in the IC chip 41, since the FETs 9 and 13 are arranged in the region on the outermost periphery side, between the input terminals 1 and 2 -the diodes 5 to 8 and the internal circuits 3 and 4. The wiring between the FETs 9 and 13 and the diodes 5 to 7 can be made between the pads 32 corresponding to the respective input terminals, thereby facilitating the entire wiring and suppressing an increase in chip size. Can do.

(Third embodiment)
FIG. 7 shows a third embodiment of the present invention, and different portions from the first embodiment will be described. The input protection circuit 43 of the third embodiment is configured by connecting clamp circuits 42P and 42N in series in two stages. According to the third embodiment configured as described above, it is possible to cope with a case where a surge voltage of a higher level is applied.

(Fourth embodiment)
FIG. 8 shows a fourth embodiment of the present invention. The input protection circuit 44 of the fourth embodiment is configured by connecting clamp circuits 42P and 42N in parallel in two stages. According to the fourth embodiment configured as described above, the current resistance can be improved, and a larger current can flow when a surge voltage is applied.

(5th Example)
FIG. 9 shows a fifth embodiment of the present invention. The input protection circuit 45 of the fifth embodiment is a combination of the configuration of the third embodiment and the configuration of the fourth embodiment. The clamp circuits 42P and 42N are connected in series in two stages, and the diode 5, The clamp circuits 42P and 42N located on the 6th side and the diodes 7 and 8 side are respectively connected in parallel in two stages. According to the fifth embodiment configured as described above, the operational effects of the third and fourth embodiments can be obtained simultaneously.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications are possible.
As a transistor constituting the clamp circuit, a P-channel MOSFET may be used instead of the N-channel MOSFET. In this case, the connection position between the Zener diode and the resistance element constituting the bias circuit may be reversed. An NPN transistor may be used. Further, the clamp circuit may be composed of only a Zener diode.
The number of connection stages of the clamp circuits 42P and 42N in the third to fifth embodiments may be three or more.
The present invention can be widely applied without being limited to an electronic circuit mounted on a vehicle.

The figure which is a 1st Example at the time of applying this invention to IC mounted in a vehicle, and shows the structure of an input protection circuit Diagram showing the structure near the diode in a schematic cross section of a semiconductor substrate The figure which is 2nd Example of this invention, and shows the circuit arrangement | positioning of each element in the case of integrating an input protection circuit into IC FIG. 3 shows only the arrangement corresponding to FIG. 3 equivalent diagram corresponding to the conventional configuration 4 equivalent diagram FIG. 1 equivalent view showing a third embodiment of the present invention. FIG. 1 equivalent view showing a fourth embodiment of the present invention. FIG. 1 equivalent view showing a fifth embodiment of the present invention. Diagram showing a conventional input protection circuit Fig. 10 shows the same circuit as Fig. 10 configured for negative surges. 2 equivalent diagram

Explanation of symbols

  In the drawing, 1 and 2 are input terminals, 5 and 6 are diodes (first diodes), 7 and 8 are diodes (second diodes), 9 is an N-channel MOSFET (first transistor), and 10 is a zener diode (first diode). (Bias circuit), 11 is a resistance element (first bias circuit), 13 is an N-channel MOSFET (second transistor), 14 is a Zener diode (second bias circuit), 15 is a resistance element (second bias circuit), and 21 is An input protection circuit, 23 is an SiO2 film (insulating film material), 25 is an SOI substrate, 29 is an insulating film material, 42P and 42N are clamp circuits (first and second clamp circuits), and 43 to 45 are input protection circuits. .

Claims (4)

A first diode and a second diode, each having an anode and a cathode connected to an input terminal for transmitting an externally applied signal to an internal circuit;
A first clamp circuit connected between the cathode of the first diode and circuit ground;
A second clamp circuit connected between the anode of the second diode and circuit ground;
Forming each circuit element in a region insulated from the formation region of other circuit elements ;
The first and second clamp circuits are
A first transistor connected between the cathode of the first diode and circuit ground;
A second transistor connected between the anode of the second diode and circuit ground;
These are arranged on the input side of the first and second transistors, respectively, and when a positive or negative surge voltage is applied to the input terminal, a bias is applied so as to turn on the first and second transistors, respectively. A first bias circuit and a second bias circuit ;
The first and second transistors are arranged in a region on the outermost side on the substrate,
An input protection circuit , wherein the input terminal is arranged between the first and second transistors and the internal circuit.   2. The input protection circuit according to claim 1, wherein each of the circuit elements is formed in a region that is trench-isolated by an insulating film material on an SOI (Silicon On Insulator) substrate. 3. An input protection circuit according to claim 1, wherein a plurality of said first and second clamp circuits are connected in series . 4. The input protection circuit according to claim 1, wherein a plurality of the first and second clamp circuits are connected in parallel .

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