JP2008235922A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
JP2008235922A
JP2008235922A JP2008109052A JP2008109052A JP2008235922A JP 2008235922 A JP2008235922 A JP 2008235922A JP 2008109052 A JP2008109052 A JP 2008109052A JP 2008109052 A JP2008109052 A JP 2008109052A JP 2008235922 A JP2008235922 A JP 2008235922A
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
film
insulating film
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008109052A
Other languages
Japanese (ja)
Other versions
JP4701264B2 (en
Inventor
Noriaki Oda
典明 小田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Priority to JP2008109052A priority Critical patent/JP4701264B2/en
Publication of JP2008235922A publication Critical patent/JP2008235922A/en
Application granted granted Critical
Publication of JP4701264B2 publication Critical patent/JP4701264B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device improved in robustness against impacts to a bonding pad when probing and bonding. <P>SOLUTION: The semiconductor device with a bonding pad 130 on a semiconductor substrate 10 includes an upper Cu layer 100 formed on a lower surface of the bonding pad 130 via a barrier metal and having a larger Cu area ratio than a layer on which circuit wiring is formed, and a lower Cu layer 200 electrically insulated from the upper Cu layer 100 and formed on the side of the semiconductor substrate 10 from the upper Cu layer 100. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、ワイヤーボンディングのためのボンディングパッドを有する半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device having a bonding pad for wire bonding and a manufacturing method thereof.

従来、銅（Ｃｕ）配線を用いた半導体装置において、Ｃｕ配線上にボンディングパッドを形成する際、ボンディング部分をＣｕ配線上からずれた位置に設けるようにしているものがある（例えば、特許文献１参照）。   2. Description of the Related Art Conventionally, in a semiconductor device using copper (Cu) wiring, when a bonding pad is formed on a Cu wiring, a bonding portion is provided at a position shifted from the Cu wiring (for example, Patent Document 1). reference).

図５は従来技術による半導体装置の一構成例を示す断面構造図である。   FIG. 5 is a cross-sectional structure diagram showing a configuration example of a semiconductor device according to the prior art.

図５では、半導体基板１０上に形成されたＣｕ配線７００上に複数のＣｕパッドが設けられ、Ｃｕ最上層パッド７１０上にバリアメタル７２０を介して最上層Ａｌ配線７３０が形成されている。そして、上述のように、最上層Ａｌ配線７３０のボンディング部分７３５がＣｕ配線７００上からずれた位置にある。そのため、ボンディング時のストレスがボンディング部分７３５の下層のパッシベーション絶縁膜７４０および層間絶縁膜７５０にかかり、Ｃｕ配線７００へのストレスの影響が低減され、Ｃｕ配線７００が表面に露出することを防げる。
特開２００１−１５５１６号公報（第４頁〜第５頁、第２図） In FIG. 5, a plurality of Cu pads are provided on the Cu wiring 700 formed on the semiconductor substrate 10, and the uppermost Al wiring 730 is formed on the Cu uppermost layer pad 710 via the barrier metal 720. As described above, the bonding portion 735 of the uppermost Al wiring 730 is at a position shifted from the Cu wiring 700. Therefore, the stress at the time of bonding is applied to the passivation insulating film 740 and the interlayer insulating film 750 below the bonding portion 735, the influence of the stress on the Cu wiring 700 is reduced, and the Cu wiring 700 can be prevented from being exposed to the surface.
JP 2001-15516 A (pages 4 to 5 and FIG. 2)

上述した公報に示される半導体装置は、次のような問題があった。   The semiconductor device disclosed in the above publication has the following problems.

Ｃｕ配線上からずれた位置にボンディング部分を設けると、その分ボンディングパッドの面積が大きくなり、チップサイズの拡大化を招くことになる。   If the bonding portion is provided at a position shifted from the Cu wiring, the area of the bonding pad is increased correspondingly and the chip size is increased.

また、酸化膜よりも比誘電率が小さい低比誘電率膜がボンディング部分の下に存在する場合、プロービングやボンディング時の針の荷重によりボンディングパッドが沈み込み、ボンディングパッド下の層間絶縁膜にクラックが発生したり、ボンディングパッドの膜剥れが生じたりする。   In addition, when a low relative dielectric constant film having a relative dielectric constant smaller than that of the oxide film exists under the bonding part, the bonding pad sinks due to the load of the probe during probing or bonding, and cracks occur in the interlayer insulating film under the bonding pad. May occur or the film of the bonding pad may peel off.

本発明は上記したような従来の技術が有する問題点を解決するためになされたものであり、ブロービングおよびボンディング時のボンディングパッドへの衝撃に対する耐性（以下、「衝撃耐性」と称する）を向上させた半導体装置およびその製造方法を提供することを目的とする。   The present invention has been made to solve the above-described problems of the prior art, and improves resistance to impact on the bonding pad during blowing and bonding (hereinafter referred to as “impact resistance”). An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

上記目的を達成するための本発明の半導体装置は、半導体基板上にボンディングパッドを有する半導体装置であって、
前記ボンディングパッドの下面にバリアメタルを介して形成された上部Ｃｕ層と、
前記上部Ｃｕ層と比べて前記ボンディングパッド下におけるＣｕ層の面積が小さく、前記上部Ｃｕ層より前記半導体基板側に形成された下部Ｃｕ層と、を有し、
前記上部Ｃｕ層と前記下部Ｃｕ層とが、前記ボンディングパッドの下において、電気的に絶縁されていることを特徴とする。 In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device having a bonding pad on a semiconductor substrate,
An upper Cu layer formed on the lower surface of the bonding pad via a barrier metal;
An area of the Cu layer under the bonding pad is smaller than that of the upper Cu layer, and a lower Cu layer formed on the semiconductor substrate side of the upper Cu layer;
The upper Cu layer and the lower Cu layer are electrically insulated under the bonding pad.

また、本発明の半導体装置は、半導体基板上にボンディングパッドを有する半導体装置であって、
前記ボンディングパッドの下面にバリアメタルを介して形成され、回路配線が形成される層よりもＣｕ面積率が大きな上部Ｃｕ層と、
前記上部Ｃｕ層と電気的に絶縁され、前記上部Ｃｕ層よりも前記半導体基板側に形成された下部Ｃｕ層と、
を有する構成である。 The semiconductor device of the present invention is a semiconductor device having a bonding pad on a semiconductor substrate,
An upper Cu layer formed on the lower surface of the bonding pad via a barrier metal and having a larger Cu area ratio than a layer on which circuit wiring is formed;
A lower Cu layer that is electrically insulated from the upper Cu layer and formed closer to the semiconductor substrate than the upper Cu layer;
It is the structure which has.

また、上記本発明の半導体装置において、上部Ｃｕ層はＣｕ面積率が７０％以上９５％以下であることとしてもよく、ボンディングパッドおよび上部Ｃｕ層は平面寸法が略同一であることとしてもよい。   In the semiconductor device of the present invention, the upper Cu layer may have a Cu area ratio of 70% or more and 95% or less, and the bonding pad and the upper Cu layer may have substantially the same planar dimensions.

また、上記本発明の半導体装置において、上部Ｃｕ層が複数からなることとしてもよく、複数の上部Ｃｕ層における各Ｃｕ層のＣｕ面積率が同一であることとしてもよい。   In the semiconductor device of the present invention, the upper Cu layer may be composed of a plurality of Cu layers, and the Cu area ratio of each Cu layer in the plurality of upper Cu layers may be the same.

また、上記本発明の半導体装置において、複数の上部Ｃｕ層の層間には層間絶縁膜が設けられ、
前記各Ｃｕ層は、前記層間絶縁膜中にＣｕが埋設されたビアプラグを介して接続されていることとしてもよい。 In the semiconductor device of the present invention, an interlayer insulating film is provided between the plurality of upper Cu layers,
The Cu layers may be connected via via plugs in which Cu is embedded in the interlayer insulating film.

また、上記本発明の半導体装置において、複数の上部Ｃｕ層として、半導体基板側からボンディングパッド側に第１Ｃｕ層、第２Ｃｕ層、…、および第ｎＣｕ層（ｎは２以上の自然数）が順に設けられている場合、
ビアプラグ、および前記第ｎＣｕ層のＣｕ層パターンが第１の材料よりなる絶縁膜に埋設されていることとしてもよい。 In the semiconductor device of the present invention, a first Cu layer, a second Cu layer,..., And an nCu layer (n is a natural number of 2 or more) are sequentially provided from the semiconductor substrate side to the bonding pad side as a plurality of upper Cu layers. If
The via plug and the Cu layer pattern of the n-th Cu layer may be embedded in an insulating film made of the first material.

また、上記本発明の半導体装置において、下部Ｃｕ層はＣｕ面積率が１５％以上９５％以下であることとしてもよく、下部Ｃｕ層が複数からなることとしてもよい。   In the semiconductor device of the present invention, the lower Cu layer may have a Cu area ratio of 15% or more and 95% or less, and the lower Cu layer may be composed of a plurality.

また、上記本発明の半導体装置において、複数の下部Ｃｕ層における各Ｃｕ層のＣｕ面積率が同一であることとしてもよく、複数の下部Ｃｕ層の各Ｃｕ層間に第１の材料よりなる絶縁膜が介在することとしてもよい。   In the semiconductor device of the present invention, the Cu area ratio of each Cu layer in the plurality of lower Cu layers may be the same, and the insulating film made of the first material between the Cu layers of the plurality of lower Cu layers It is good also as interposing.

また、上記本発明の半導体装置において、複数の下部Ｃｕ層の各Ｃｕ層において同一層に形成されたＣｕ層パターン間に、第１の材料に比べて比誘電率が低い材料を有する第２の材料よりなる絶縁膜が介在することとしてもよく、第２の材料が第１の材料よりも軟質であることとしてもよい。   Further, in the semiconductor device of the present invention, a second material having a lower relative dielectric constant than the first material is formed between the Cu layer patterns formed in the same layer in each of the plurality of lower Cu layers. An insulating film made of a material may be interposed, and the second material may be softer than the first material.

また、上記本発明の半導体装置において、第２の材料よりなる絶縁膜は、ＳｉＯＣ膜、ＳｉＣ膜、ＳｉＯＦ膜、ポーラスＳｉＯ2膜、ポーラスＳｉＯＣ膜、および梯子型水素化シロキサン構造を有するラダーオキサイド膜のうちいずれか一つを含むこととしてもよい。 In the semiconductor device of the present invention, the insulating film made of the second material includes a SiOC film, a SiC film, a SiOF film, a porous SiO 2 film, a porous SiOC film, and a ladder oxide film having a ladder-type hydrogenated siloxane structure. It is good also as including any one of these.

また、上記本発明の半導体装置において、複数の下部Ｃｕ層の各Ｃｕ層間に、第１の材料に比べて比誘電率が低い材料を有する第３の材料よりなる絶縁膜が介在することとしてもよく、第３の材料が第１の材料よりも軟質であることとしてもよい。   In the semiconductor device of the present invention, an insulating film made of a third material having a material having a lower relative dielectric constant than the first material may be interposed between the Cu layers of the plurality of lower Cu layers. Alternatively, the third material may be softer than the first material.

また、上記本発明の半導体装置において、第３の材料よりなる絶縁膜は、ＳｉＯＣ膜、ＳｉＣ膜、ＳｉＯＦ膜、ポーラスＳｉＯ2膜、ポーラスＳｉＯＣ膜、および梯子型水素化シロキサン構造を有するラダーオキサイド膜のうちいずれか一つを含むこととしてもよい。 In the semiconductor device of the present invention, the insulating film made of the third material is a SiOC film, a SiC film, a SiOF film, a porous SiO 2 film, a porous SiOC film, and a ladder oxide film having a ladder-type hydrogenated siloxane structure. It is good also as including any one of these.

また、上記本発明の半導体装置において、バリアメタルがＴｉＮおよびＴａＮのうちいずれか一方を含むこととしてもよい。   In the semiconductor device of the present invention, the barrier metal may include any one of TiN and TaN.

さらに、上記本発明の半導体装置において、前記半導体装置に内部回路を備え、
前記内部回路およびボンディングパッドと電気的に接続された補助Ｃｕ配線を有することとしてもよい。 Furthermore, in the semiconductor device of the present invention, the semiconductor device includes an internal circuit,
It is good also as having the auxiliary | assistant Cu wiring electrically connected with the said internal circuit and the bonding pad.

一方、上記目的を達成するための本発明の半導体装置の製造方法は、上部Ｃｕ層および下部Ｃｕ層をダマシン法により形成するものである。   On the other hand, in the method of manufacturing a semiconductor device of the present invention for achieving the above object, an upper Cu layer and a lower Cu layer are formed by a damascene method.

また、本発明の半導体装置の製造方法は、第ｎＣｕ層および該第ｎＣｕ層に接触するビアプラグをデュアルダマシン法により形成するものである。   In the method for manufacturing a semiconductor device according to the present invention, the nCu layer and the via plug contacting the nCu layer are formed by a dual damascene method.

（作用）
上記のように構成される本発明では、Ｃｕは外部から加えられた力を跳ね返そうとする性質である弾性が酸化膜より大きいため、ボンディングパッド下に、耐衝撃層として、上部Ｃｕ層、および上部Ｃｕ層と同等以下のＣｕ面積率を有する下部Ｃｕ層を設けることで、プロービングおよびボンディング時の衝撃に対する耐性が向上する。 (Function)
In the present invention configured as described above, since Cu is more elastic than an oxide film, which has the property of repelling an externally applied force, an upper Cu layer as an impact resistant layer under the bonding pad, In addition, by providing a lower Cu layer having a Cu area ratio equal to or less than that of the upper Cu layer, resistance to impact during probing and bonding is improved.

また、本発明では、Ｃｕは弾性が酸化膜より大きいため、ボンディングパッド下に、回路配線が形成される層よりもＣｕ面積率が大きい上部Ｃｕ層、および下部Ｃｕ層を設けることで、プロービングおよびボンディング時の衝撃に対する耐性が向上する。   In the present invention, since Cu is more elastic than an oxide film, the upper Cu layer and the lower Cu layer having a Cu area ratio larger than that of the layer on which the circuit wiring is formed are provided below the bonding pad. Resistance to impact during bonding is improved.

また、本発明では、上部Ｃｕ層のＣｕ面積率を７０％以上９５％以下にすることで、プロービングおよびボンディング時の衝撃耐性がより向上する。   Moreover, in this invention, the impact resistance at the time of probing and bonding improves more by making Cu area rate of an upper Cu layer 70% or more and 95% or less.

また、本発明では、ボンディングパッドと上部Ｃｕ層との平面パターンの寸法が同一なので、ボンディングパッドと上部Ｃｕ層との接触面積が十分得られる。   In the present invention, since the dimensions of the planar pattern of the bonding pad and the upper Cu layer are the same, a sufficient contact area between the bonding pad and the upper Cu layer can be obtained.

また、本発明では、上部Ｃｕ層を複数にすることで、衝撃が各Ｃｕ層に分散する。また、本発明では、上部各Ｃｕ層のＣｕ面積率が同一であるため、衝撃がより均等に分散する。   Moreover, in this invention, an impact is disperse | distributed to each Cu layer by making multiple upper Cu layers. Moreover, in this invention, since the Cu area ratio of each upper Cu layer is the same, an impact is disperse | distributed more uniformly.

また、本発明では、上部各Ｃｕ層がビアプラグを介して接続されているため、最上層の衝撃が他の層に、より分散しやすくなる。   In the present invention, since the upper Cu layers are connected via via plugs, the impact of the uppermost layer is more easily distributed to other layers.

また、本発明では、上部第ｎＣｕ層およびビアプラグが埋設された、第１の材料よりなる絶縁膜が硬質であるため、ボンディング時に最も大きな衝撃力を受ける上部第ｎＣｕ層およびビアプラグを絶縁膜が均一に支持する。   Further, in the present invention, since the insulating film made of the first material in which the upper nCu layer and the via plug are embedded is hard, the insulating film is uniform in the upper nCu layer and the via plug that receive the greatest impact force during bonding. To support.

また、本発明では、下部Ｃｕ層のＣｕ面積率を１５％以上９５％以下にすることで、衝撃耐性をさらに向上することができる。そのため、下部Ｃｕ層をＣｕ面積率１５％以上９５％以下の回路配線層として利用し、ボンディングパッドの下の領域を有効に活用できる。   In the present invention, impact resistance can be further improved by setting the Cu area ratio of the lower Cu layer to 15% or more and 95% or less. Therefore, the lower Cu layer can be used as a circuit wiring layer having a Cu area ratio of 15% or more and 95% or less, and the region under the bonding pad can be effectively used.

また、本発明では、下部Ｃｕ層を複数にすることで、下部Ｃｕ層に伝わる衝撃が各層に分散する。   Moreover, in this invention, the impact transmitted to a lower Cu layer is disperse | distributed to each layer by using multiple lower Cu layers.

また、本発明では、下部各Ｃｕ層のＣｕ面積率が同一であるため、下部Ｃｕ層に伝わる衝撃がより均等に分散する。   Moreover, in this invention, since the Cu area ratio of each lower Cu layer is the same, the impact transmitted to a lower Cu layer is disperse | distributed more uniformly.

また、本発明では、下部Ｃｕ層の各Ｃｕ層間に、第１の材料よりなる絶縁膜を用いることで、絶縁膜が下部Ｃｕ層をより均一に支持する。   Moreover, in this invention, an insulating film supports a lower Cu layer more uniformly by using the insulating film which consists of 1st materials between each Cu layer of a lower Cu layer.

また、本発明では、上部Ｃｕ層および下部Ｃｕ層を設け、ボンディングパッドへの衝撃耐性が向上することにより、第１の材料よりも比誘電率の低い材料を有する第２の材料よりなる絶縁膜を下部Ｃｕ層の層間絶縁膜に用いることができ、異なる配線層の間の配線間容量を低減できる。   In the present invention, the upper Cu layer and the lower Cu layer are provided and the impact resistance to the bonding pad is improved, so that the insulating film made of the second material having a material having a lower relative dielectric constant than the first material. Can be used for the interlayer insulating film of the lower Cu layer, and the wiring capacity between different wiring layers can be reduced.

また、本発明では、上部Ｃｕ層および下部Ｃｕ層を設け、ボンディングパッドへの衝撃耐性が向上することにより、第１の材料よりも軟質な第２の材料よりなる絶縁膜を下部Ｃｕ層の層間絶縁膜に用いることができる。   In the present invention, the upper Cu layer and the lower Cu layer are provided, and the impact resistance to the bonding pad is improved, so that the insulating film made of the second material softer than the first material is formed between the lower Cu layers. It can be used for an insulating film.

また、本発明では、上部Ｃｕ層および下部Ｃｕ層を設け、ボンディングパッドへの衝撃耐性が向上することにより、第１の材料よりも比誘電率の低い材料を有する第３の材料よりなる絶縁膜を下部Ｃｕ層に介在する絶縁膜に用いることができ、同一層に形成される配線同士の間の容量を低減できる。   In the present invention, the upper Cu layer and the lower Cu layer are provided, and the impact resistance to the bonding pad is improved, whereby the insulating film made of the third material having a material having a relative dielectric constant lower than that of the first material. Can be used for the insulating film interposed in the lower Cu layer, and the capacitance between wirings formed in the same layer can be reduced.

また、本発明では、上部Ｃｕ層および下部Ｃｕ層を設け、ボンディングパッドへの衝撃耐性が向上することにより、第１の材料よりも軟質な第３の材料よりなる絶縁膜を下部Ｃｕ層に介在する絶縁膜に用いることができる。   In the present invention, the upper Cu layer and the lower Cu layer are provided, and the resistance to impact to the bonding pad is improved, so that an insulating film made of a third material softer than the first material is interposed in the lower Cu layer. It can be used for an insulating film.

また、本発明では、バリアメタルとして、ＴｉＮおよびＴａＮのうちいずれか一つを用いることで、ＡｌとＣｕとが相互に拡散することを防げる。   In the present invention, Al and Cu can be prevented from diffusing each other by using any one of TiN and TaN as the barrier metal.

さらに、本発明では、ボンディングパッドと補助Ｃｕ配線とが接続されているため、ボンディング時の衝撃で上部Ｃｕ層にクラックが入って接続不良になっても、ボンディングパッドと内部回路との電気的接続を確保できる。   Furthermore, in the present invention, since the bonding pad and the auxiliary Cu wiring are connected, even if the upper Cu layer cracks due to an impact during bonding and the connection becomes defective, the electrical connection between the bonding pad and the internal circuit is achieved. Can be secured.

本発明は以上説明したように構成されているので、以下に記載する効果を奏する。   Since the present invention is configured as described above, the following effects can be obtained.

本発明では、外部から加えられた力を跳ね返そうとする性質である弾性が酸化膜より大きいＣｕ層を、ボンディングパッド下にバリアメタルを介して形成することにより、プロービングやボンディング時に針が跳ね返りやすく、下方に衝撃が伝わりにくくなる。そのため、衝撃耐性が向上し、ボンディングパッドにプロービングの針を立ててもパッドが破壊されることを防げる。   In the present invention, by forming a Cu layer having elasticity larger than that of the oxide film, which is a property to repel externally applied force, via a barrier metal under the bonding pad, the needle rebounds during probing and bonding. It is easy and the impact is difficult to be transmitted downward. Therefore, impact resistance is improved, and even if a probing needle is raised on the bonding pad, the pad can be prevented from being destroyed.

また、ボンディングパッド下にＣｕ層が形成されているので、ボンディングの際、金ワイヤーとボンディングパッドとを共晶するための超音波がＬ−Ｏｘ膜等の低比誘電率膜に吸収されることなく金ワイヤーとボンディングパッドに十分に伝わり、金ワイヤーとボンディングパッドとの密着性が強化され、ワイヤプル強度が大きくなる。   In addition, since a Cu layer is formed under the bonding pad, ultrasonic waves for eutecticizing the gold wire and the bonding pad are absorbed by the low dielectric constant film such as the L-Ox film during bonding. The wire is sufficiently transmitted to the gold wire and the bonding pad, the adhesion between the gold wire and the bonding pad is enhanced, and the wire pull strength is increased.

さらに、ボンディングパッド部の実質的なメタル膜厚がアルミとボンディングパッド下のＣｕ層との和となるので、プロービングおよびボンディングに対する硬度が十分になり、下層のＬ−Ｏｘ膜等の低比誘電率膜付近にかかる荷重が軽減される。そのため、クラックが層間絶縁膜に発生することを防げる。   Furthermore, since the substantial metal film thickness of the bonding pad portion is the sum of aluminum and the Cu layer under the bonding pad, the hardness for probing and bonding is sufficient, and the low relative dielectric constant of the lower L-Ox film, etc. The load applied near the membrane is reduced. Therefore, it is possible to prevent cracks from occurring in the interlayer insulating film.

本発明の半導体装置は、耐衝撃層として、ボンディングパッドの下層にバリアメタルを介して形成された上部Ｃｕ層と、この上部Ｃｕ層と電気的に絶縁された下部Ｃｕ層とを設けたことを特徴とする。   The semiconductor device of the present invention is provided with an upper Cu layer formed through a barrier metal under a bonding pad and a lower Cu layer electrically insulated from the upper Cu layer as an impact resistant layer. Features.

（第１実施例）
本発明の半導体装置の構成について説明する。 (First embodiment)
The structure of the semiconductor device of the present invention will be described.

図１は本発明の半導体装置の一構成例を示す平面図および断面構造図である。   1A and 1B are a plan view and a cross-sectional structure diagram illustrating a configuration example of a semiconductor device of the present invention.

図１（ｂ）の断面構造図に示すように、本発明の半導体装置は、アルミニウム（Ａｌ）を主成分とする金属膜を含むボンディングパッド１３０の下層に、アルミニウムが下層に含まれる元素と反応するのを防ぐためのバリアメタルを介して形成された、衝撃耐性向上のための上部Ｃｕ層１００を有する構成である。   As shown in the cross-sectional structure diagram of FIG. 1B, the semiconductor device of the present invention reacts with an element in which aluminum is contained in a lower layer of a bonding pad 130 including a metal film containing aluminum (Al) as a main component. This is a structure having an upper Cu layer 100 for improving impact resistance, which is formed through a barrier metal for preventing the above.

上部Ｃｕ層１００およびボンディングパッド１３０は平面寸法が略同一（誤差の範囲内で同一であることを意味する）であり、上部Ｃｕ層１００がボンディングパッド１３０を下方から均一に支持する。   The upper Cu layer 100 and the bonding pad 130 have substantially the same planar dimensions (meaning that they are the same within an error range), and the upper Cu layer 100 supports the bonding pad 130 uniformly from below.

また、図１（ｂ）に示すように、衝撃耐性をより向上させるために、上部Ｃｕ層１００の下層に酸化膜（ＳｉＯ2膜）３２を介して、上部Ｃｕ層１００と電気的に絶縁された下部Ｃｕ層２００を設けている。上部Ｃｕ層１００および下部Ｃｕ層２００の間に低比誘電率膜よりも硬質な絶縁膜のＳｉＯ2膜３２を設けることで、ボンディング時に加わる力による沈み込みを防止している。 Further, as shown in FIG. 1B, in order to further improve the impact resistance, the upper Cu layer 100 is electrically insulated from the upper Cu layer 100 via an oxide film (SiO 2 film) 32 below the upper Cu layer 100. A lower Cu layer 200 is provided. By providing the SiO 2 film 32, which is harder than the low relative dielectric constant film, between the upper Cu layer 100 and the lower Cu layer 200, sinking due to the force applied during bonding is prevented.

本実施例では、上部Ｃｕ層１００は上部第１Ｃｕ層１１０および上部第２Ｃｕ層１２０の２層を有し、この２層は、Ｃｕを主成分とするビアプラグ１４０で電気的に接続されている。このように、上部Ｃｕ層１００を複数の層にすることで、ボンディングパッド１３０に加わる衝撃が各層に分散されるため、より衝撃耐性が向上する。   In the present embodiment, the upper Cu layer 100 has two layers of an upper first Cu layer 110 and an upper second Cu layer 120, and these two layers are electrically connected by a via plug 140 containing Cu as a main component. Thus, by making the upper Cu layer 100 into a plurality of layers, the impact applied to the bonding pad 130 is dispersed in each layer, so that the impact resistance is further improved.

上部第２Ｃｕ層１２０およびビアプラグ１４０のそれぞれは、第１の材料よりなる絶縁膜であるＳｉＯ2膜４２、４４にそれぞれ埋設されている。上部第２Ｃｕ層１２０およびビアプラグ１４０が埋設された絶縁膜が硬質であるため、絶縁膜が上部第２Ｃｕ層１２０およびビアプラグ１４０を均一に支持する。上部第２Ｃｕ層１２０およびビアプラグ１４０はボンディング時に加わる力を最も大きく受ける部分であるため、上部第２Ｃｕ層１２０およびビアプラグ１４０を、低比誘電率膜よりも硬質な絶縁膜のＳｉＯ2膜に埋設することが望ましい。 The upper second Cu layer 120 and the via plug 140 are respectively embedded in SiO 2 films 42 and 44 which are insulating films made of the first material. Since the insulating film in which the upper second Cu layer 120 and the via plug 140 are embedded is hard, the insulating film uniformly supports the upper second Cu layer 120 and the via plug 140. Since the upper second Cu layer 120 and the via plug 140 are the portions that receive the greatest force during bonding, the upper second Cu layer 120 and the via plug 140 are embedded in an SiO 2 film that is harder than the low relative dielectric constant film. It is desirable.

また、下部Ｃｕ層２００は下部第１Ｃｕ層２１０および下部第２Ｃｕ層２２０の２層を有する。この２層は、ＳｉＯ2膜２２で絶縁されている。下部Ｃｕ層２００を複数のＣｕ層にすることで、上述の上部Ｃｕ層１００と同様な効果がある。下部第１Ｃｕ層２１０のＣｕ層パターン間には、梯子型水素化シロキサン構造を持つ低比誘電率膜であるラダーオキサイド（Ｌ−Ｏｘ（ＮＥＣエレクトロニクス株式会社の商標（出願中）））膜、およびＳｉＯ2膜からなる積層絶縁膜１４が介在している。下部第２Ｃｕ層２２０についても、同様に、Ｌ−Ｏｘ膜およびＳｉＯ2膜からなる積層絶縁膜２４がＣｕ層パターン間に介在している。第１の材料に比べて比誘電率が低い第２の材料を有する絶縁膜としてＬ−Ｏｘ膜を用いることにより、下部Ｃｕ層２００と同一層に形成されるＣｕ配線の配線間容量が低減される。 The lower Cu layer 200 has two layers, a lower first Cu layer 210 and a lower second Cu layer 220. The two layers are insulated by the SiO 2 film 22. By making the lower Cu layer 200 into a plurality of Cu layers, the same effect as the upper Cu layer 100 described above can be obtained. Between the Cu layer patterns of the lower first Cu layer 210, a ladder oxide (L-Ox (trademark of NEC Electronics Corporation) (pending))) film which is a low dielectric constant film having a ladder-type hydrogenated siloxane structure, and A laminated insulating film 14 made of a SiO 2 film is interposed. Similarly, in the lower second Cu layer 220, the laminated insulating film 24 composed of the L-Ox film and the SiO 2 film is interposed between the Cu layer patterns. By using the L-Ox film as the insulating film having the second material having a relative dielectric constant lower than that of the first material, the interwiring capacitance of the Cu wiring formed in the same layer as the lower Cu layer 200 is reduced. The

さらに、本発明の半導体装置は、半導体基板１０上に形成された、トランジスタ、抵抗およびキャパシタ等の半導体素子と、これらの半導体素子を接続するための回路配線とを有する内部回路を備えている。回路配線は、例えば、上部Ｃｕ層１００および下部Ｃｕ層２００のうちいずれかと同一層に形成されたＣｕ層、半導体基板１０に形成された拡散層、ならびに不純物拡散されたポリシリコン等の導電層により形成される。ボンディングパッド１３０は、上部Ｃｕ層１００を介して内部回路と接続されている。なお、半導体素子、回路配線および内部回路については、図に示すことを省略している。   Furthermore, the semiconductor device of the present invention includes an internal circuit formed on a semiconductor substrate 10 and having semiconductor elements such as transistors, resistors, and capacitors, and circuit wiring for connecting these semiconductor elements. The circuit wiring is formed by, for example, a Cu layer formed in the same layer as any one of the upper Cu layer 100 and the lower Cu layer 200, a diffusion layer formed in the semiconductor substrate 10, and a conductive layer such as polysilicon diffused with impurities. It is formed. The bonding pad 130 is connected to the internal circuit through the upper Cu layer 100. In addition, about a semiconductor element, circuit wiring, and an internal circuit, it abbreviate | omits to showing in a figure.

次に、上部Ｃｕ層１００および下部Ｃｕ層２００の平面パターンについて説明する。   Next, planar patterns of the upper Cu layer 100 and the lower Cu layer 200 will be described.

図１（ａ）は上部第１Ｃｕ層１１０の平面パターンとして設けられたダミーパターンの一例を示す模式図であり、鎖線部分の断面構造が図１（ｂ）に示されている。なお、上部第２Ｃｕ層１２０の平面パターンについては上部第１Ｃｕ層１１０と同様なため、以下では、説明を省略する。   FIG. 1A is a schematic diagram showing an example of a dummy pattern provided as a planar pattern of the upper first Cu layer 110, and a cross-sectional structure of a chain line portion is shown in FIG. The planar pattern of the upper second Cu layer 120 is the same as that of the upper first Cu layer 110, and thus the description thereof is omitted below.

図に示すように、上部第１Ｃｕ層１１０の平面パターンは、Ｃｕの面積密度が均一になるように、Ｌ−Ｏｘ膜およびＳｉＯ2膜からなる積層絶縁膜３４の方形状パターンがＣｕ層に複数配置された構成である。上部第１Ｃｕ層１１０について、平面パターンのＣｕ面積占有率であるＣｕ面積率は、衝撃耐性を向上させるために、回路配線が形成される層よりも大きい。実験結果から、Ｃｕ面積率は７０％以上であることが望ましい。また、Ｃｕ層のＣＭＰ（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ）処理の際のディッシングを防止するために、Ｃｕ面積率は９５％以下であることが望ましい。 As shown in the figure, the planar pattern of the upper first Cu layer 110 includes a plurality of square patterns of the laminated insulating film 34 composed of the L-Ox film and the SiO 2 film in the Cu layer so that the Cu area density is uniform. It is an arranged configuration. Regarding the upper first Cu layer 110, the Cu area ratio, which is the Cu area occupation ratio of the planar pattern, is larger than the layer in which the circuit wiring is formed in order to improve impact resistance. From the experimental results, the Cu area ratio is desirably 70% or more. In order to prevent dishing during the CMP (Chemical Mechanical Polishing) process of the Cu layer, the Cu area ratio is desirably 95% or less.

図１（ｃ）は下部第１Ｃｕ層２１０の平面パターンとして設けられたダミーパターンの一例を示す模式図であり、鎖線部分の断面構造が図１（ｂ）に示されている。なお、下部第２Ｃｕ層２２０の平面パターンについては下部第１Ｃｕ層２１０と同様なため、以下では、説明を省略する。   FIG. 1C is a schematic diagram showing an example of a dummy pattern provided as a planar pattern of the lower first Cu layer 210, and the cross-sectional structure of the chain line portion is shown in FIG. In addition, since the planar pattern of the lower second Cu layer 220 is the same as that of the lower first Cu layer 210, description thereof will be omitted below.

図に示すように、下部第１Ｃｕ層２１０の平面パターンは、Ｃｕの面積密度が均一になるように、十字状パターンの積層絶縁膜１４がＣｕ層に複数配置された構成である。下部第１Ｃｕ層２１０のＣｕ面積率は、衝撃耐性をより向上させるために１５％以上であることが望ましく、上部Ｃｕ層１００と同様の理由で９５％以下であることが望ましい。また、下部Ｃｕ層２００は上部Ｃｕ層１００に比べてボンディング時に受ける衝撃力が小さいため、下部Ｃｕ層２００のＣｕ面積率は上部Ｃｕ層１００と比べて同等以下であってもよい。   As shown in the drawing, the planar pattern of the lower first Cu layer 210 has a configuration in which a plurality of cross-shaped stacked insulating films 14 are arranged on the Cu layer so that the Cu area density is uniform. The Cu area ratio of the lower first Cu layer 210 is desirably 15% or more in order to further improve the impact resistance, and desirably 95% or less for the same reason as the upper Cu layer 100. Further, since the lower Cu layer 200 has a smaller impact force during bonding than the upper Cu layer 100, the Cu area ratio of the lower Cu layer 200 may be equal to or less than that of the upper Cu layer 100.

なお、下部Ｃｕ層２００の平面パターンは、上部Ｃｕ層１００と電気的に絶縁されているため、ダミーパターンの代わりに、回路配線のためのパターンであってもよい。下部Ｃｕ層２００を回路配線層として利用することで、ボンディングパッド１３０の下の領域を有効に活用できる。このとき、下部Ｃｕ層２００のＣｕ面積率は上部Ｃｕ層１００のＣｕ面積率より小さくなる。また、下部第１Ｃｕ層２１０および下部第２Ｃｕ層２２０は、層間絶縁膜で電気的に絶縁されているが、ビアプラグを介して電気的に接続するようにしてもよい。   Note that the planar pattern of the lower Cu layer 200 is electrically insulated from the upper Cu layer 100, and may be a pattern for circuit wiring instead of the dummy pattern. By using the lower Cu layer 200 as a circuit wiring layer, the region under the bonding pad 130 can be used effectively. At this time, the Cu area ratio of the lower Cu layer 200 is smaller than the Cu area ratio of the upper Cu layer 100. The lower first Cu layer 210 and the lower second Cu layer 220 are electrically insulated by an interlayer insulating film, but may be electrically connected via via plugs.

次に、図１（ｂ）に示した断面構造図を用いて、本実施例の半導体装置の製造方法について説明する。以下では、ボンディングパッド１３０の衝撃耐性向上のための部分について説明し、耐衝撃層となる各Ｃｕ層と同一層に形成される回路配線についての詳細な説明は省略する。   Next, a method for manufacturing the semiconductor device of this example will be described with reference to the cross-sectional structure diagram shown in FIG. Below, the part for the impact-resistant improvement of the bonding pad 130 is demonstrated, and detailed description about the circuit wiring formed in the same layer as each Cu layer used as an impact-resistant layer is abbreviate | omitted.

半導体基板１０の上に図に示さないトランジスタ、抵抗およびキャパシタ等の半導体素子を形成し、その上にＣＶＤ法により、層間絶縁膜としてＳｉＯ2膜１２を３００〜５００ｎｍ形成し、エッチング停止のための膜（以下、「エッチングストッパー膜」と称する）としてＳｔｏｐｐｅｒ−ＳｉＣＮ膜１３を３０〜５０ｎｍ形成する。 Semiconductor elements such as transistors, resistors, and capacitors not shown in the figure are formed on the semiconductor substrate 10, and an SiO 2 film 12 having a thickness of 300 to 500 nm is formed thereon as an interlayer insulating film by CVD to stop etching. A Stopper-SiCN film 13 is formed to a thickness of 30 to 50 nm as a film (hereinafter referred to as “etching stopper film”).

続いて、Ｓｔｏｐｐｅｒ−ＳｉＣＮ膜１３の上に、塗布法および焼成処理によりＬ−Ｏｘ膜を３００〜５００ｎｍ形成し、その上にＳｉＯ2膜を１００〜２００ｎｍ成膜して、Ｌ−Ｏｘ膜およびＳｉＯ2膜からなる積層絶縁膜１４を形成する。その後、ホトリソグラフィー工程（以下、「ホトリソ工程」と称する）によりレジストパターンを積層絶縁膜１４上に形成し、エッチング工程により、所定のダミーパターン、および図に示さない回路配線を形成するための配線用溝部を積層絶縁膜１４に形成した後、レジストパターンを除去する。 Subsequently, an L-Ox film having a thickness of 300 to 500 nm is formed on the Stopper-SiCN film 13 by a coating method and a baking process, and an SiO 2 film is formed thereon with a thickness of 100 to 200 nm. A two- layer laminated insulating film 14 is formed. Thereafter, a resist pattern is formed on the laminated insulating film 14 by a photolithography process (hereinafter referred to as “photolitho process”), and a wiring for forming a predetermined dummy pattern and a circuit wiring not shown in the figure by an etching process. After forming the groove portion in the laminated insulating film 14, the resist pattern is removed.

ダミーパターンおよび配線用溝部が形成された積層絶縁膜１４上にバリアメタルを３０〜５０ｎｍ、シード層を５０〜２００ｎｍ成膜し、その上に電解メッキ法でＣｕ膜を５００〜１０００ｎｍ成膜する。続いて、ＣＭＰ処理により積層絶縁膜１４の上面が露出するまでＣｕ膜を研磨した後、Ｃｕ拡散防止膜としてＣａｐ−ＳｉＣＮ膜１５を３０〜５０ｎｍ成膜する。このようにして、図１（ｃ）に示した平面パターンを有する下部第１Ｃｕ層２１０を形成する。   A barrier metal 30 to 50 nm and a seed layer 50 to 200 nm are formed on the laminated insulating film 14 on which the dummy pattern and the wiring trench are formed, and a Cu film is formed 500 to 1000 nm thereon by electrolytic plating. Subsequently, after the Cu film is polished by CMP treatment until the upper surface of the laminated insulating film 14 is exposed, a Cap-SiCN film 15 is formed as a Cu diffusion preventing film by 30 to 50 nm. In this way, the lower first Cu layer 210 having the planar pattern shown in FIG. 1C is formed.

その後、下部第１Ｃｕ層２１０の上にＳｉＯ2膜２２を３００〜５００ｎｍ形成し、上記下部第１Ｃｕ層２１０と同様にして、下部第２Ｃｕ層２２０を形成する。 Thereafter, the SiO 2 film 22 is formed to 300 to 500 nm on the lower first Cu layer 210, and the lower second Cu layer 220 is formed in the same manner as the lower first Cu layer 210.

次に、下部第２Ｃｕ層２２０の上にＳｉＯ2膜３２を３００〜５００ｎｍおよびＳｔｏｐｐｅｒ−ＳｉＣＮ膜３３を３０〜５０ｎｍ形成する。続いて、膜厚３００〜５００ｎｍのＬ−Ｏｘ膜、および膜厚１００〜２００ｎｍのＳｉＯ2膜からなる積層絶縁膜３４を形成する。その後、ホトリソ工程によりレジストパターンを積層絶縁膜３４上に形成し、エッチング工程により、所定のダミーパターン、および図に示さない回路配線を形成するための配線用溝部を積層絶縁膜３４に形成した後、レジストパターンを除去する。 Next, the SiO 2 film 32 and the Stopper-SiCN film 33 are formed on the lower second Cu layer 220 to 300 to 500 nm and 30 to 50 nm, respectively. Subsequently, a laminated insulating film 34 including an L—Ox film having a thickness of 300 to 500 nm and an SiO 2 film having a thickness of 100 to 200 nm is formed. Thereafter, a resist pattern is formed on the laminated insulating film 34 by a photolithography process, and a predetermined dummy pattern and a wiring groove for forming a circuit wiring (not shown) are formed in the laminated insulating film 34 by an etching process. Then, the resist pattern is removed.

ダミーパターンおよび配線用溝部が形成された積層絶縁膜３４上にバリアメタルを３０〜５０ｎｍ、シード層を５０〜１００ｎｍ、およびＣｕ膜を６００〜１０００ｎｍ成膜する。続いて、ＣＭＰ処理により積層絶縁膜３４の上面が露出するまでＣｕ膜を研磨した後、Ｃａｐ−ＳｉＣＮ膜３５を３０〜５０ｎｍ成膜する。このようにして、図１（ａ）に示した平面パターンを有する上部第１Ｃｕ層１１０を形成する。   A barrier metal of 30 to 50 nm, a seed layer of 50 to 100 nm, and a Cu film of 600 to 1000 nm are formed on the laminated insulating film 34 on which the dummy pattern and the wiring trench are formed. Subsequently, after the Cu film is polished by CMP treatment until the upper surface of the laminated insulating film 34 is exposed, a Cap-SiCN film 35 is formed to a thickness of 30 to 50 nm. In this way, the upper first Cu layer 110 having the planar pattern shown in FIG. 1A is formed.

次に、上部第１Ｃｕ層１１０の上にＳｉＯ2膜４２を３００〜５００ｎｍ、Ｓｔｏｐｐｅｒ−ＳｉＣＮ膜４３を５０〜７０ｎｍ、およびＳｉＯ2膜４４を３００〜５００ｎｍ形成する。続いて、ホトリソ工程によりビアプラグ１４０形成のためのレジストパターンをＳｉＯ2膜４４上に形成し、Ｃａｐ−ＳｉＣＮ膜３５が露出するまでエッチングしてビア部を形成した後、レジストパターンを除去する。その後、ホトリソ工程により上部第２Ｃｕ層１２０形成のためのレジストパターンをＳｉＯ2膜４４上に形成し、エッチング工程によりＳｉＯ2膜４４に図１（ａ）で示したパターンを形成する。そして、レジストパターン除去後に、ビア底部のＣａｐ−ＳｉＣＮ膜３５をエッチングにより除去する。 Next, the SiO 2 film 42 is formed on the upper first Cu layer 110 to 300 to 500 nm, the Stopper-SiCN film 43 is formed to 50 to 70 nm, and the SiO 2 film 44 is formed to 300 to 500 nm. Subsequently, a resist pattern for forming the via plug 140 is formed on the SiO 2 film 44 by a photolithography process, etching is performed until the Cap-SiCN film 35 is exposed, and then the resist pattern is removed. Thereafter, a resist pattern for the upper first 2Cu layer 120 formed is formed on the SiO 2 film 44 by photolithography process to form a pattern shown in the SiO 2 film 44 in FIGS. 1 (a) by an etching process. Then, after removing the resist pattern, the Cap-SiCN film 35 at the bottom of the via is removed by etching.

続いて、バリアメタルを３０〜５０ｎｍ、シード層を５０〜１００ｎｍ、およびＣｕ膜を６００〜１０００ｎｍ成膜する。そして、ＣＭＰ処理によりＳｉＯ2膜４４上面が露出するまでＣｕ膜を研磨した後、Ｃａｐ−ＳｉＣＮ膜４５を３０〜５０ｎｍ成膜する。このようにして、図１（ａ）に示した平面パターンを有する上部第２Ｃｕ層１２０を形成する。 Subsequently, a barrier metal is formed to 30 to 50 nm, a seed layer is formed to 50 to 100 nm, and a Cu film is formed to 600 to 1000 nm. Then, after polishing the Cu film until the upper surface of the SiO 2 film 44 is exposed by CMP treatment, a Cap-SiCN film 45 is formed to a thickness of 30 to 50 nm. In this way, the upper second Cu layer 120 having the planar pattern shown in FIG.

次に、Ｃａｐ−ＳｉＣＮ膜４５の上にＳｉＯ2膜５２を３００〜５００ｎｍ形成し、ホトリソ工程により、上部第２Ｃｕ層１２０上に開口部を設けるためのレジストパターンをＳｉＯ2膜５２上に形成する。続いて、エッチング工程により、露出したＳｉＯ2膜５２、およびその下層のＣａｐ−ＳｉＣＮ膜４５をエッチングして、上部第２Ｃｕ層１２０とボンディングパッド１３０とを接続するための開口部を形成する。レジストパターンを除去した後、スパッタリング法により、バリアメタルとしてＴｉＮ膜５４を１００〜２００ｎｍ、Ａｌ−Ｃｕ（０．５％）膜を８００〜１０００ｎｍ、および反射防止膜としてＴｉＮ膜６４を５０〜１００ｎｍ成膜する。 Next, the SiO 2 film 52 is 300~500nm formed on the Cap-SiCN film 45, a photolithographic process to form a resist pattern for forming an opening on the upper first 2Cu layer 120 on the SiO 2 film 52 . Subsequently, the exposed SiO 2 film 52 and the underlying Cap-SiCN film 45 are etched by an etching process to form an opening for connecting the upper second Cu layer 120 and the bonding pad 130. After removing the resist pattern, the sputtering method is used to form a TiN film 54 as a barrier metal of 100 to 200 nm, an Al—Cu (0.5%) film of 800 to 1000 nm, and a TiN film 64 of 50 to 100 nm as an antireflection film. Film.

続いて、ホトリソ工程によりボンディングパッド１３０を形成するためのレジストパターンをＴｉＮ膜６４上に形成し、エッチング工程によりボンディングパッド１３０を形成した後、レジストパターンを除去する。そして、ボンディングパッド１３０上のＴｉＮ６４を覆うようにＳｉＯ2膜６２を１００〜２００ｎｍ形成し、ＳｉＯ2膜６２の上にポリイミド膜６６を８００〜１０００ｎｍ形成する。 Subsequently, a resist pattern for forming the bonding pad 130 is formed on the TiN film 64 by a photolithography process. After the bonding pad 130 is formed by an etching process, the resist pattern is removed. Then, the SiO 2 film 62 is formed to a thickness of 100 to 200 nm so as to cover the TiN 64 on the bonding pad 130, and the polyimide film 66 is formed to a thickness of 800 to 1000 nm on the SiO 2 film 62.

ホトリソ工程によりボンディングパッド１３０上のポリイミド膜６６に開口部を形成し、開口部のＳｉＯ2膜６２およびＴｉＮ膜６４をエッチングして、ボンディングパッド１３０を露出させる。 An opening is formed in the polyimide film 66 on the bonding pad 130 by a photolithography process, and the SiO 2 film 62 and the TiN film 64 in the opening are etched to expose the bonding pad 130.

本実施例では、外部から加えられた力を跳ね返そうとする性質である弾性が酸化膜より大きいＣｕ層を、ボンディングパッド１３０下にバリアメタルを介して形成することにより、プロービングやボンディング時に針が跳ね返りやすく、下方に衝撃が伝わりにくくなる。そのため、衝撃耐性が向上し、ボンディングパッドにプロービングの針を立ててもパッドが破壊されることを防げる。   In this embodiment, a Cu layer, which has the property of repelling the force applied from the outside and has a larger elasticity than that of the oxide film, is formed under the bonding pad 130 via a barrier metal so that needles can be used during probing and bonding. Is easy to bounce off, making it difficult for impact to be transmitted downward. Therefore, impact resistance is improved, and even if a probing needle is raised on the bonding pad, the pad can be prevented from being destroyed.

また、ボンディングパッド１３０下にＣｕ層が形成されているので、ボンディングの際、金ワイヤーとボンディングパッド１３０とを共晶させるための超音波がＬ−Ｏｘ膜等の低比誘電率膜に吸収されることなく金ワイヤーとボンディングパッド１３０に十分に伝わり、金ワイヤーとボンディングパッドとの密着性が強化され、ワイヤプル強度が大きくなる。   In addition, since a Cu layer is formed under the bonding pad 130, ultrasonic waves for eutecticizing the gold wire and the bonding pad 130 are absorbed by a low dielectric constant film such as an L-Ox film during bonding. Without being sufficiently transmitted to the gold wire and the bonding pad 130, the adhesion between the gold wire and the bonding pad is enhanced, and the wire pull strength is increased.

さらに、ボンディングパッド部の実質的なメタル膜厚がアルミとボンディングパッド下のＣｕ層との和となるので、プロービングおよびボンディングに対する硬度が十分になり、下層のＬ−Ｏｘ膜付近にかかる荷重が軽減される。そのため、クラックが層間絶縁膜に発生することを防げる。   Furthermore, since the substantial metal film thickness of the bonding pad portion is the sum of aluminum and the Cu layer under the bonding pad, the hardness against probing and bonding is sufficient, and the load applied to the vicinity of the lower L-Ox film is reduced. Is done. Therefore, it is possible to prevent cracks from occurring in the interlayer insulating film.

（第２実施例）
本実施例は、内部回路に接続された補助Ｃｕ配線を設け、補助Ｃｕ配線にボンディングパッドを接続したことを特徴とする。 (Second embodiment)
This embodiment is characterized in that an auxiliary Cu wiring connected to an internal circuit is provided, and a bonding pad is connected to the auxiliary Cu wiring.

図２は本実施例の半導体装置の断面構造図である。   FIG. 2 is a sectional structural view of the semiconductor device of this embodiment.

図２に示すように、本実施例の半導体装置は、内部回路に接続され、上部第２Ｃｕ層１２０と同一層に形成された補助Ｃｕ配線１２５を有し、ボンディングパッド１３０と補助Ｃｕ配線１２５とがビアホール１５０を介して電気的に接続された構成である。   As shown in FIG. 2, the semiconductor device of this embodiment has an auxiliary Cu wiring 125 connected to an internal circuit and formed in the same layer as the upper second Cu layer 120. The bonding pad 130, the auxiliary Cu wiring 125, Are electrically connected through the via hole 150.

本実施例の半導体装置の製造方法について説明する。なお、第１実施例と同様の工程については、その詳細な説明を省略する。   A method for manufacturing the semiconductor device of this embodiment will be described. Detailed description of the same steps as those in the first embodiment will be omitted.

上部第１Ｃｕ層１１０を形成するまで、第１実施例と同様に処理する。その後、図１に示したＳｉＯ2膜４４に補助Ｃｕ配線１２５形成のための溝部を形成し、上部第２Ｃｕ層１２０を形成する際、図２に示す補助Ｃｕ配線１２５を形成する。上部第２Ｃｕ層１２０上に開口部を設けるためのレジストパターンをＳｉＯ2膜５２上に形成する際、補助Ｃｕ配線１２５とボンディングパッド１３０を接続するためのビアホールパターンを形成する。 Processing is performed in the same manner as in the first embodiment until the upper first Cu layer 110 is formed. Thereafter, a groove for forming the auxiliary Cu wiring 125 is formed in the SiO 2 film 44 shown in FIG. 1, and when forming the upper second Cu layer 120, the auxiliary Cu wiring 125 shown in FIG. 2 is formed. When a resist pattern for providing an opening on the upper second Cu layer 120 is formed on the SiO 2 film 52, a via hole pattern for connecting the auxiliary Cu wiring 125 and the bonding pad 130 is formed.

本実施例では、上記第１実施例の効果を有するだけでなく、プロービングおよびボンディング時におけるボンディングパッドへの衝撃により、上部第２Ｃｕ層１２０にクラックが発生し、上部第２Ｃｕ層１２０とボンディングパッド１３０との間で電気的な導通が十分に得られなくなっても、ボンディングパッド１３０はビアホール１５０および補助Ｃｕ配線１２５を介して内部回路との電気的な導通を確保できる。   In this embodiment, not only the effects of the first embodiment are obtained, but also cracks are generated in the upper second Cu layer 120 due to an impact on the bonding pad during probing and bonding, and the upper second Cu layer 120 and the bonding pad 130 are generated. Even if sufficient electrical continuity is not obtained, the bonding pad 130 can ensure electrical continuity with the internal circuit via the via hole 150 and the auxiliary Cu wiring 125.

なお、ボンディングパッド１３０は補助Ｃｕ配線１２５を介して内部回路と接続されるため、上部Ｃｕ層１００は内部回路と接続していなくてもよい。   Since the bonding pad 130 is connected to the internal circuit via the auxiliary Cu wiring 125, the upper Cu layer 100 may not be connected to the internal circuit.

さらに、補助Ｃｕ配線１２５を上部第２Ｃｕ層１２０と同一層で形成したが、上部第１Ｃｕ層１１０などその他の導電層で形成してもよい。   Further, although the auxiliary Cu wiring 125 is formed of the same layer as the upper second Cu layer 120, it may be formed of other conductive layers such as the upper first Cu layer 110.

（第３実施例）
本実施例は、第２実施例で示したボンディングパッドを複数配置した場合の一例を示すものである。本実施例の構成について、以下に説明する。 (Third embodiment)
This embodiment shows an example when a plurality of bonding pads shown in the second embodiment are arranged. The configuration of this embodiment will be described below.

図３はボンディングパッドを複数配置した場合の一例を示す平面図および断面構造図であり、図３（ｂ）は、図３（ａ）に示す鎖線ＡＡ’部分の断面構造図である。なお、ボンディングパッド１３０上のＴｉＮ膜６４からポリイミド膜６６までの構成は、第１実施例および第２実施例と同様なため、図に示すことを省略している。   3A and 3B are a plan view and a cross-sectional structure diagram showing an example in which a plurality of bonding pads are arranged, and FIG. 3B is a cross-sectional structure diagram of a chain line AA ′ portion shown in FIG. The configuration from the TiN film 64 to the polyimide film 66 on the bonding pad 130 is the same as that in the first embodiment and the second embodiment, and is not shown in the figure.

本実施例では、図３（ａ）に示すように、スクライブ線６００に近い側のボンディングパッドである外側パッド１３２と、外側パッド１３２よりチップ中心に近い側のボンディングパッドである内側パッド１３４とが互い違いに並んだ構成である。   In the present embodiment, as shown in FIG. 3A, an outer pad 132 that is a bonding pad closer to the scribe line 600 and an inner pad 134 that is a bonding pad closer to the chip center than the outer pad 132 are provided. It is a configuration arranged in a staggered manner.

図３（ｂ）に示すように、下部第１Ｃｕ層２１０と同一層に、回路配線のための下部第１Ｃｕ配線２１２が形成されている。同様に、下部第２Ｃｕ層２２０と同一層に、回路配線のための下部第２Ｃｕ配線２２２が形成されている。また、上部第２Ｃｕ層１２０と同一層に、回路配線のための上部第２Ｃｕ配線１２２が形成されている。   As shown in FIG. 3B, a lower first Cu wiring 212 for circuit wiring is formed in the same layer as the lower first Cu layer 210. Similarly, a lower second Cu wiring 222 for circuit wiring is formed in the same layer as the lower second Cu layer 220. An upper second Cu wiring 122 for circuit wiring is formed in the same layer as the upper second Cu layer 120.

外側パッド１３２の下には、耐衝撃層として、上部第２Ｃｕ層１２０、上部第１Ｃｕ層１１０、下部第２Ｃｕ層２２０および下部第１Ｃｕ層２１０が形成されている。外側パッド１３２は、補助Ｃｕ配線１２５およびビアプラグ１４０を介して、下部第１Ｃｕ配線２１２および下部第２Ｃｕ配線２２２に接続されている。   Under the outer pad 132, an upper second Cu layer 120, an upper first Cu layer 110, a lower second Cu layer 220, and a lower first Cu layer 210 are formed as an impact resistant layer. The outer pad 132 is connected to the lower first Cu wiring 212 and the lower second Cu wiring 222 via the auxiliary Cu wiring 125 and the via plug 140.

内側パッド１３４の下には、耐衝撃層として、上部第２Ｃｕ層１２０および上部第１Ｃｕ層１１０が形成されている。内側パッド１３４は、補助Ｃｕ配線となる上部第２Ｃｕ配線１２２と接続されている。   Under the inner pad 134, an upper second Cu layer 120 and an upper first Cu layer 110 are formed as an impact resistant layer. The inner pad 134 is connected to the upper second Cu wiring 122 serving as an auxiliary Cu wiring.

なお、内側パッド１３４の下に、下部第２Ｃｕ層２２０および下部第１Ｃｕ層２１０を設けるようにしてもよい。その際、隣り合う下部第２Ｃｕ配線２２２同士がショートしないように、下部第２Ｃｕ層２２０を設ける。下部第１Ｃｕ層２１０についても同様の構成となる。   Note that the lower second Cu layer 220 and the lower first Cu layer 210 may be provided under the inner pad 134. At this time, the lower second Cu layer 220 is provided so that adjacent lower second Cu wirings 222 do not short-circuit. The lower first Cu layer 210 has the same configuration.

本実施例では、外側パッド１３２および内側パッド１３４について、第２実施例と同様に、プロービングおよびボンディング時におけるボンディングパッドへの衝撃により、ボンディングパッドにクラックが発生し、上部第２Ｃｕ層１２０とボンディングパッドとの間で電気的な導通が十分に得られなくなっても、ボンディングパッドは補助Ｃｕ配線１２５を介して内部回路との電気的な導通を確保できる。   In this embodiment, as with the second embodiment, the outer pad 132 and the inner pad 134 are cracked by the impact on the bonding pad during probing and bonding, and the upper second Cu layer 120 and the bonding pad. Even if sufficient electrical continuity is not obtained, the bonding pad can ensure electrical continuity with the internal circuit via the auxiliary Cu wiring 125.

（第４実施例）
本実施例では、下部Ｃｕ層の層間絶縁膜として、ＳｉＯ2膜の代わりに、第１の材料に比べて比誘電率の低い材料を有する第３の絶縁膜としてＳｉＯＣ膜を用いたことを特徴とする。以下に、本実施例の構成について説明する。 (Fourth embodiment)
In this embodiment, an SiOC film is used as the third insulating film having a material having a lower relative dielectric constant than the first material, instead of the SiO 2 film, as the interlayer insulating film of the lower Cu layer. And The configuration of the present embodiment will be described below.

図４は、本実施例の半導体装置の構成を示す断面構造図である。   FIG. 4 is a cross-sectional structure diagram showing the configuration of the semiconductor device of this example.

図４に示すように、下部Ｃｕ層２００として、下部第１Ｃｕ層４１０、下部第２Ｃｕ層４１２、下部第３Ｃｕ層４１４、および下部第４Ｃｕ層４１６の４層を設けている。各層は、図１（ａ）に示した上部第１Ｃｕ層１１０の平面パターンと同様である。上記４層のそれぞれは、Ｃｕ層パターン間に、Ｌ−Ｏｘ膜およびＳｉＯ2膜からなる積層絶縁膜３１０、３１４、３１８、３２２のそれぞれが介在している。また、上記４層の各層間絶縁膜として、ＳｉＯＣ膜３１２、３１６、３２０が形成されている。 As shown in FIG. 4, four layers of a lower first Cu layer 410, a lower second Cu layer 412, a lower third Cu layer 414, and a lower fourth Cu layer 416 are provided as the lower Cu layer 200. Each layer is the same as the planar pattern of the upper first Cu layer 110 shown in FIG. Each of the four layers, between the Cu layer pattern, each of the stacked insulating film 310,314,318,322 is interposed consisting L-Ox film and SiO 2 film. In addition, SiOC films 312, 316, and 320 are formed as the four interlayer insulating films.

また、本実施例では、上部Ｃｕ層および下部Ｃｕ層のＣｕ面積率を略同一にしているため、各Ｃｕ層のＣｕ面積率が略同一となり、衝撃がより均等に分散し、衝撃耐性がさらに向上する。   In this example, the Cu area ratio of the upper Cu layer and the lower Cu layer is substantially the same, so the Cu area ratio of each Cu layer is substantially the same, the impact is more evenly distributed, and the impact resistance is further increased. improves.

また、本実施例における積層絶縁膜３１０、３１４、３１８、３２２、３２６は、ＳｉＯＣ膜であってもよい。   Further, the laminated insulating films 310, 314, 318, 322, and 326 in this embodiment may be SiOC films.

本実施例のように、層間絶縁膜に低比誘電率膜を用いることで、異なる配線層の間の配線間容量を低減できる。   By using a low relative dielectric constant film as an interlayer insulating film as in this embodiment, the inter-wiring capacitance between different wiring layers can be reduced.

次に、上記第１実施例〜第４実施例および従来技術の構成について、ボンディング後に、ボンディングワイヤの引っ張り強度を調べるワイヤプル試験を行ったので、その試験方法と結果について説明する。   Next, the wire pull test for examining the tensile strength of the bonding wire after bonding was performed on the configurations of the first to fourth embodiments and the prior art, and the test method and results will be described.

ワイヤプル試験は、ボンディングワイヤを上に引っ張り上げ、その強度が４ｇｆ未満で、ワイヤが切断したり、ボールが外れたり、ボンディングパッドが剥れたりした場合を不良と判定した。ワイヤプル試験の不良率は、図５に示した従来技術の構成で、層間絶縁膜７５０がＳｉＯ2膜である場合に約１０％あり、層間絶縁膜７５０が低比誘電率膜のＳｉＯＣ膜である場合には約２０％あった。これに対して、第１実施例〜第４実施例の場合では、不良率はいずれも０％であった。 In the wire pull test, the bonding wire was pulled up, the strength was less than 4 gf, and the case where the wire was cut, the ball was detached, or the bonding pad was peeled was judged as defective. The defect rate of the wire pull test is about 10% when the interlayer insulating film 750 is a SiO 2 film in the configuration of the prior art shown in FIG. 5, and the interlayer insulating film 750 is a SiOC film of a low relative dielectric constant film. In some cases, it was about 20%. On the other hand, in the case of the first to fourth examples, the defect rate was 0%.

なお、上記第１実施例〜第４実施例において、上部Ｃｕ層１００および下部Ｃｕ層２００のそれぞれは、上述の２層や４層の場合に限らず、２層および４層以外の複数層であってもよい。ここで、上部Ｃｕ層１００として、半導体基板１０側からボンディングパッド１３０側に第１Ｃｕ層、第２Ｃｕ層、…、および第ｎＣｕ層（ｎは２以上の自然数）が順に設けられている場合、第ｎＣｕ層およびビアプラグが第１の材料よりなる絶縁膜に埋設された構成となる。   In the first to fourth embodiments, each of the upper Cu layer 100 and the lower Cu layer 200 is not limited to the above-described two layers or four layers, and may be a plurality of layers other than the two layers and the four layers. There may be. Here, as the upper Cu layer 100, when the first Cu layer, the second Cu layer,..., And the n-th Cu layer (n is a natural number of 2 or more) are sequentially provided from the semiconductor substrate 10 side to the bonding pad 130 side, The nCu layer and the via plug are embedded in the insulating film made of the first material.

また、上部Ｃｕ層１００および下部Ｃｕ層２００のそれぞれは、単層であってもよい。単層にすれば、他のＣｕ層を回路配線層として用いることができる。   Each of the upper Cu layer 100 and the lower Cu layer 200 may be a single layer. If a single layer is used, another Cu layer can be used as a circuit wiring layer.

また、上部Ｃｕ層１００および下部Ｃｕ層２００の平面パターンがダミーパターンの場合、図１に示した形状に限られず、Ｃｕの面積密度が均一になるようなパターンであればよい。   Further, when the planar pattern of the upper Cu layer 100 and the lower Cu layer 200 is a dummy pattern, the pattern is not limited to the shape shown in FIG.

また、ビアプラグ１４０および上部第２Ｃｕ層１２０をデュアルダマシン法により形成したが、シングルダマシン法によりビアプラグ１４０および上部第２Ｃｕ層１２０を別々に形成してもよい。   In addition, although the via plug 140 and the upper second Cu layer 120 are formed by the dual damascene method, the via plug 140 and the upper second Cu layer 120 may be separately formed by a single damascene method.

また、第１の材料を有する絶縁膜としてＳｉＯ2膜を用いたが、他の絶縁膜であってもよい。上述のように、第１の材料を有する絶縁膜がＳｉＯ2膜である場合、上記第２の材料を有する絶縁膜をＬ−Ｏｘ膜とし、上記第３の材料を有する絶縁膜をＳｉＯＣ膜としたが、第２の材料を有する絶縁膜および第３の材料を有する絶縁膜のそれぞれが、Ｌ−Ｏｘ膜、ＳｉＯＣ膜、ＳｉＣ膜、ＳｉＯＦ膜、ポーラスＳｉＯ2膜、ポーラスＳｉＯＣ膜等の低比誘電率膜のうち少なくともいずれか一つ含む膜であってもよい。 In addition, although the SiO 2 film is used as the insulating film having the first material, other insulating films may be used. As described above, when the insulating film having the first material is an SiO 2 film, the insulating film having the second material is an L-Ox film, and the insulating film having the third material is an SiOC film. However, each of the insulating film having the second material and the insulating film having the third material has a low ratio of the L-Ox film, the SiOC film, the SiC film, the SiOF film, the porous SiO 2 film, the porous SiOC film, or the like. It may be a film including at least one of the dielectric constant films.

また、エッチングストッパー膜およびＣｕ拡散防止膜としてＳｉＣＮ膜を用いたが、ＳｉＣＮに限らず、ＳｉＣ膜およびＳｉＮ膜のいずれの膜であってもよい。また、エッチングストッパー膜にＳｉＯＮ膜を用いてもよい。これらの膜同士で、被エッチング膜とのエッチング速度の比である選択比、および誘電率を比較し、パターン加工がしやすく、かつ配線間容量が小さくなるように、エッチングストッパー膜およびＣｕ拡散防止膜を選択すればよい。   Further, although the SiCN film is used as the etching stopper film and the Cu diffusion preventing film, the film is not limited to SiCN, and any film of SiC film and SiN film may be used. Further, a SiON film may be used as the etching stopper film. Compare the etching ratio between these films and the etching rate of the film to be etched, and the dielectric constant. Etching stopper film and Cu diffusion prevention to facilitate pattern processing and reduce inter-wiring capacitance. A membrane may be selected.

また、上部Ｃｕ層１００および下部Ｃｕ層２００を設けることにより、ボンディング時の衝撃耐性が向上するため、上部第２Ｃｕ層１２０に介在するＳｉＯ2膜４４などの第１の材料を有する絶縁膜に代えて、ＳｉＯ2膜より軟質なＬ−Ｏｘ膜やＳｉＯＣ膜などの低比誘電率膜を含む膜を設けるようにしてもよい。 In addition, since the upper Cu layer 100 and the lower Cu layer 200 are provided, the impact resistance during bonding is improved, so that the insulating film having the first material such as the SiO 2 film 44 interposed in the upper second Cu layer 120 is replaced. A film including a low relative dielectric constant film such as an L-Ox film or a SiOC film softer than the SiO 2 film may be provided.

また、ボンディングパッド１３０のバリアメタルは、ＡｌおよびＣｕが相互に拡散するのを防ぐものとして、ＴｉＮ膜に限らず、ＴａＮ膜であってもよい。   Further, the barrier metal of the bonding pad 130 is not limited to the TiN film but may be a TaN film as a means for preventing Al and Cu from diffusing each other.

さらに、上記Ｃｕ層およびビアプラグは、ＳｉやＡｌ等の他の元素を微量含有するものであってもよい。   Further, the Cu layer and the via plug may contain a trace amount of other elements such as Si and Al.

本発明の半導体装置の一構成例を示す平面図および断面構造図である。1A and 1B are a plan view and a cross-sectional structure diagram illustrating a configuration example of a semiconductor device of the present invention. 第２実施例の半導体装置の構成を示す断面構造図である。It is sectional structure drawing which shows the structure of the semiconductor device of 2nd Example. 第３実施例の半導体装置の構成を示す平面図および断面構造図である。It is the top view and sectional structure figure which show the structure of the semiconductor device of 3rd Example. 第４実施例の半導体装置の構成を示す断面構造図である。It is a cross-section figure showing the composition of the semiconductor device of the 4th example. 従来技術による半導体装置の一構成例を示す断面構造図である。It is sectional drawing which shows the example of 1 structure of the semiconductor device by a prior art.

符号の説明Explanation of symbols

１０ 半導体基板
１２、２２、３２、４２、４４、５２、６２、３２８、３３０ ＳｉＯ2膜
１３、２３、３３、４３ Ｓｔｏｐｐｅｒ−ＳｉＣＮ膜
１４、２４、３４、３１０、３１４、３１８、３２２、３２６ 積層絶縁膜
１５、２５、３５、４５ Ｃａｐ−ＳｉＣＮ膜
１００ 上部Ｃｕ層
１１０ 上部第１Ｃｕ層
１２０ 上部第２Ｃｕ層
１２２ 上部第２Ｃｕ配線
１２５ 補助Ｃｕ配線
１３０ ボンディングパッド
１３２ 外側パッド
１３４ 内側パッド
１４０ ビアプラグ
１５０ ビアホール
２００ 下部Ｃｕ層
２１０、４１０ 下部第１Ｃｕ層
２１２ 下部第１Ｃｕ配線
２２０、４１２ 下部第２Ｃｕ層
２２２ 下部第２Ｃｕ配線
３１２、３１６、３２０、３２４ ＳｉＯＣ膜
４１４ 下部第３Ｃｕ層
４１６ 下部第４Ｃｕ層
６００ スクライブ線
７００ Ｃｕ配線
７１０ Ｃｕ最上層パッド
７２０ バリアメタル
７３０ 最上層Ａｌ配線
７３５ ボンディング部分
７４０ パッシベーション絶縁膜
７５０ 層間絶縁膜 10 Semiconductor substrate 12, 22, 32, 42, 44, 52, 62, 328, 330 SiO 2 film 13, 23, 33, 43 Stopper-SiCN film 14, 24, 34, 310, 314, 318, 322, 326 Lamination Insulating film 15, 25, 35, 45 Cap-SiCN film 100 Upper Cu layer 110 Upper first Cu layer 120 Upper second Cu layer 122 Upper second Cu wiring 125 Auxiliary Cu wiring 130 Bonding pad 132 Outer pad 134 Inner pad 140 Via plug 150 Via hole 200 Lower Cu layer 210, 410 Lower first Cu layer 212 Lower first Cu wiring 220, 412 Lower second Cu layer 222 Lower second Cu wiring 312, 316, 320, 324 SiOC film 414 Lower third Cu layer 416 Lower fourth Cu layer 600 Scribe line 7 0 Cu wiring 710 Cu uppermost pad 720 barrier metal 730 uppermost Al wiring 735 bonding portion 740 passivation layer 750 interlayer insulating film

Claims (19)

半導体基板上にボンディングパッドを有する半導体装置であって、
前記ボンディングパッドの下面にバリアメタルを介して形成された上部Ｃｕ層と、
前記上部Ｃｕ層と比べて前記ボンディングパッド下におけるＣｕ層の面積が小さく、前記上部Ｃｕ層より前記半導体基板側に形成された下部Ｃｕ層と、を有し、
前記上部Ｃｕ層と前記下部Ｃｕ層とが、前記ボンディングパッドの下において、電気的に絶縁されている半導体装置。 A semiconductor device having a bonding pad on a semiconductor substrate,
An upper Cu layer formed on the lower surface of the bonding pad via a barrier metal;
An area of the Cu layer under the bonding pad is smaller than that of the upper Cu layer, and a lower Cu layer formed on the semiconductor substrate side of the upper Cu layer;
A semiconductor device in which the upper Cu layer and the lower Cu layer are electrically insulated under the bonding pad. 請求項１に記載の半導体装置であって、
前記ボンディングパッド下における上部Ｃｕ層と下部Ｃｕ層との間に、Ｃｕが形成されていない層間絶縁膜が設けられている半導体装置。 The semiconductor device according to claim 1,
A semiconductor device in which an interlayer insulating film in which Cu is not formed is provided between an upper Cu layer and a lower Cu layer under the bonding pad. 請求項２に記載の半導体装置であって、
前記層間絶縁膜が、下部Ｃｕ層に用いられる層間絶縁膜よりも硬質である半導体装置。 The semiconductor device according to claim 2,
A semiconductor device in which the interlayer insulating film is harder than an interlayer insulating film used for a lower Cu layer. 請求項２に記載の半導体装置であって、
前記層間絶縁膜が、下部Ｃｕ層に用いられる層間絶縁膜よりも比誘電率が高い半導体装置。 The semiconductor device according to claim 2,
A semiconductor device in which the interlayer insulating film has a higher relative dielectric constant than an interlayer insulating film used for a lower Cu layer. 請求項１乃至４のいずれかに記載の半導体装置であって、
前記上部Ｃｕ層が複数層からなる半導体装置。 The semiconductor device according to claim 1,
A semiconductor device in which the upper Cu layer comprises a plurality of layers. 請求項５に記載の半導体装置であって、
各Ｃｕ層の層間には層間絶縁膜が設けられ、
前記各Ｃｕ層は、前記層間絶縁膜中にＣｕが埋設されたビアプラグを介して接続されている半導体装置。 The semiconductor device according to claim 5,
An interlayer insulating film is provided between each Cu layer,
The Cu layers are connected to each other through via plugs in which Cu is embedded in the interlayer insulating film. 請求項５または６に記載の半導体装置であって、
前記複数層の上部Ｃｕ層として、半導体基板側からボンディングパッド側に第１Ｃｕ層、第２Ｃｕ層、…、および第ｎＣｕ層（ｎは２以上の自然数）が順に設けられている場合、
ビアプラグ、および前記第ｎＣｕ層のＣｕ層パターンが第１の材料よりなる絶縁膜に埋設されている半導体装置。 The semiconductor device according to claim 5, wherein:
When the first Cu layer, the second Cu layer,..., And the n-th Cu layer (n is a natural number of 2 or more) are sequentially provided from the semiconductor substrate side to the bonding pad side as the plurality of upper Cu layers,
A semiconductor device in which a via plug and a Cu layer pattern of the n-th Cu layer are embedded in an insulating film made of a first material. 請求項１乃至７のいずれかに記載の半導体装置であって、
前記下部Ｃｕ層が複数層からなる半導体装置。 A semiconductor device according to claim 1,
A semiconductor device in which the lower Cu layer comprises a plurality of layers. 請求項８に記載の半導体装置であって、
前記複数層の下部Ｃｕ層の各Ｃｕ層間に第１の材料よりなる絶縁膜が介在する半導体装置。 The semiconductor device according to claim 8,
A semiconductor device in which an insulating film made of a first material is interposed between each Cu layer of the plurality of lower Cu layers. 請求項８または９に記載の半導体装置であって、
前記複数層の下部Ｃｕ層の各Ｃｕ層において同一層に形成されたＣｕ層パターン間に、第１の材料に比べて比誘電率が低い材料を有する第２の材料よりなる絶縁膜が介在する半導体装置。 A semiconductor device according to claim 8 or 9, wherein
An insulating film made of a second material having a material having a lower relative dielectric constant than the first material is interposed between Cu layer patterns formed in the same layer in each Cu layer of the plurality of lower Cu layers. Semiconductor device. 請求項１０に記載の半導体装置であって、
第２の材料が第１の材料よりも軟質である半導体装置。 The semiconductor device according to claim 10,
A semiconductor device in which the second material is softer than the first material. 請求項１０または１１に記載の半導体装置であって、
第２の材料よりなる絶縁膜は、ＳｉＯＣ膜、ＳｉＣ膜、ＳｉＯＦ膜、ポーラスＳｉＯ2膜、ポーラスＳｉＯＣ膜、および梯子型水素化シロキサン構造を有するラダーオキサイド膜のうちいずれか一つを含む半導体装置。 The semiconductor device according to claim 10 or 11,
The insulating film made of the second material includes a semiconductor device including any one of a SiOC film, a SiC film, a SiOF film, a porous SiO 2 film, a porous SiOC film, and a ladder oxide siloxane hydride structure . 請求項８乃至１２のいずれかに記載の半導体装置であって、
複数層の前記下部Ｃｕ層の各Ｃｕ層間に、第１の材料に比べて比誘電率が低い材料を有する第３の材料よりなる絶縁膜が介在する半導体装置。 A semiconductor device according to any one of claims 8 to 12,
A semiconductor device in which an insulating film made of a third material having a material having a relative dielectric constant lower than that of the first material is interposed between the Cu layers of the plurality of lower Cu layers. 請求項１３に記載の半導体装置であって、
第３の材料が第１の材料よりも軟質である半導体装置。 The semiconductor device according to claim 13,
A semiconductor device in which the third material is softer than the first material. 請求項１３または１４に記載の半導体装置であって、
第３の材料よりなる絶縁膜は、ＳｉＯＣ膜、ＳｉＣ膜、ＳｉＯＦ膜、ポーラスＳｉＯ2膜、ポーラスＳｉＯＣ膜、および梯子型水素化シロキサン構造を有するラダーオキサイド膜のうちいずれか一つを含む半導体装置。 The semiconductor device according to claim 13 or 14,
The insulating film made of the third material includes one of a SiOC film, a SiC film, a SiOF film, a porous SiO 2 film, a porous SiOC film, and a ladder oxide film having a ladder-type hydrogenated siloxane structure. . 請求項１乃至１５のいずれかに記載の半導体装置であって、
バリアメタルがＴｉＮおよびＴａＮのうちいずれか一方を含む半導体装置。 A semiconductor device according to claim 1,
A semiconductor device in which the barrier metal includes one of TiN and TaN. 請求項１乃至１６のいずれかに記載の半導体装置であって、
前記半導体装置に内部回路を備え、
前記内部回路およびボンディングパッドと電気的に接続された補助Ｃｕ配線を有する半導体装置。 A semiconductor device according to claim 1,
The semiconductor device includes an internal circuit,
A semiconductor device having auxiliary Cu wiring electrically connected to the internal circuit and the bonding pad. 請求項１乃至１７のいずれかに記載の半導体装置の製造方法であって、
前記上部Ｃｕ層および前記下部Ｃｕ層をダマシン法により形成する半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the upper Cu layer and the lower Cu layer are formed by a damascene method. 請求項５に記載の半導体装置の製造方法であって、
第ｎＣｕ層および該第ｎＣｕ層に接触するビアプラグをデュアルダマシン法により形成することを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 5,
A method of manufacturing a semiconductor device, comprising: forming an nCu layer and a via plug contacting the nCu layer by a dual damascene method.
JP2008109052A 2008-04-18 2008-04-18 Semiconductor device and manufacturing method of semiconductor device Expired - Fee Related JP4701264B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008109052A JP4701264B2 (en) 2008-04-18 2008-04-18 Semiconductor device and manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008109052A JP4701264B2 (en) 2008-04-18 2008-04-18 Semiconductor device and manufacturing method of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2003021959A Division JP4170103B2 (en) 2003-01-30 2003-01-30 Semiconductor device and manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2008235922A true JP2008235922A (en) 2008-10-02
JP4701264B2 JP4701264B2 (en) 2011-06-15

Family

ID=39908263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008109052A Expired - Fee Related JP4701264B2 (en) 2008-04-18 2008-04-18 Semiconductor device and manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP4701264B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013229455A (en) * 2012-04-26 2013-11-07 Renesas Electronics Corp Semiconductor device and method for manufacturing the same
US10529766B2 (en) 2017-04-24 2020-01-07 Canon Kabushiki Kaisha Camera and solid-state image sensor that includes a wiring structure with an electrically conductive pattern having plural primary and auxiliary lines arranged on a semiconductor substrate

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10340920A (en) * 1997-06-10 1998-12-22 Sony Corp Method for manufacturing semiconductor device
JPH1154544A (en) * 1997-05-01 1999-02-26 Texas Instr Inc <Ti> System and method for reinforcing bond pad
JPH1167763A (en) * 1997-08-21 1999-03-09 Sony Corp Semiconductor device and manufacturing method therefor
JPH11186320A (en) * 1997-12-09 1999-07-09 Samsung Electron Co Ltd Semiconductor element with multilayered pad, and manufacture thereof
JPH11307724A (en) * 1998-04-21 1999-11-05 Rohm Co Ltd Semiconductor integrated circuit
JP2001015516A (en) * 1999-06-30 2001-01-19 Toshiba Corp Semiconductor device and manufacture thereof
JP2001267323A (en) * 2000-03-21 2001-09-28 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2002353221A (en) * 2001-05-29 2002-12-06 Sony Corp Semiconductor device and its manufacturing method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1154544A (en) * 1997-05-01 1999-02-26 Texas Instr Inc <Ti> System and method for reinforcing bond pad
JPH10340920A (en) * 1997-06-10 1998-12-22 Sony Corp Method for manufacturing semiconductor device
JPH1167763A (en) * 1997-08-21 1999-03-09 Sony Corp Semiconductor device and manufacturing method therefor
JPH11186320A (en) * 1997-12-09 1999-07-09 Samsung Electron Co Ltd Semiconductor element with multilayered pad, and manufacture thereof
JPH11307724A (en) * 1998-04-21 1999-11-05 Rohm Co Ltd Semiconductor integrated circuit
JP2001015516A (en) * 1999-06-30 2001-01-19 Toshiba Corp Semiconductor device and manufacture thereof
JP2001267323A (en) * 2000-03-21 2001-09-28 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2002353221A (en) * 2001-05-29 2002-12-06 Sony Corp Semiconductor device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013229455A (en) * 2012-04-26 2013-11-07 Renesas Electronics Corp Semiconductor device and method for manufacturing the same
US10529766B2 (en) 2017-04-24 2020-01-07 Canon Kabushiki Kaisha Camera and solid-state image sensor that includes a wiring structure with an electrically conductive pattern having plural primary and auxiliary lines arranged on a semiconductor substrate

Also Published As

Publication number Publication date
JP4701264B2 (en) 2011-06-15

Similar Documents

Publication Publication Date Title
JP4170103B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP5205066B2 (en) Semiconductor device and manufacturing method thereof
US8310056B2 (en) Semiconductor device
US7459792B2 (en) Via layout with via groups placed in interlocked arrangement
US20120248605A1 (en) Semiconductor device and manufacturing method thereof
US7420278B2 (en) Semiconductor device
US20040164418A1 (en) Semiconductor device having a pillar structure
JP2006261631A (en) Top via pattern of bond pad structure
TW201115697A (en) Semiconductor device
US20100090344A1 (en) Semiconductor device
JP2005085939A (en) Semiconductor device and its manufacturing method
KR101096101B1 (en) Semiconductor device and method of manufacturing semiconductor device
JP4701264B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2005142351A (en) Semiconductor device and its manufacturing method
JP4663510B2 (en) Semiconductor device
KR20100070633A (en) Structure for bonding pad and manufacturing method used the same
JP4422004B2 (en) Semiconductor device
JP5564557B2 (en) Semiconductor device
JP2006318989A (en) Semiconductor device
JP2005327763A (en) Semiconductor device
JP2007242644A (en) Semiconductor device and manufacturing method therefor
JP5168265B2 (en) Semiconductor device and manufacturing method thereof
JP2006324388A (en) Semiconductor device and its manufacturing method
JP2014179657A (en) Semiconductor device

Legal Events

Date Code Title Description
RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20100701

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100825

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100907

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101207

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110204

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110301

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110307

R150 Certificate of patent or registration of utility model

Ref document number: 4701264

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees