JPH10340920A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH10340920A
JPH10340920A JP9151749A JP15174997A JPH10340920A JP H10340920 A JPH10340920 A JP H10340920A JP 9151749 A JP9151749 A JP 9151749A JP 15174997 A JP15174997 A JP 15174997A JP H10340920 A JPH10340920 A JP H10340920A
Authority
JP
Japan
Prior art keywords
film
wiring
wire
opening
pad portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9151749A
Other languages
Japanese (ja)
Other versions
JP3906522B2 (en
Inventor
Kazuhiro Hoshino
和弘 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP15174997A priority Critical patent/JP3906522B2/en
Publication of JPH10340920A publication Critical patent/JPH10340920A/en
Application granted granted Critical
Publication of JP3906522B2 publication Critical patent/JP3906522B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor device having high electrical reliability by enabling wire bonding, in using a Cu wiring or a thin-filmed Al wiring. SOLUTION: Using a semiconductor chip 1 provided with a wiring 3, an insulating film 4 covering the wiring 3 and an opening 5 which is formed in the insulating film 4 and enables the wiring 3 to be looked onto on an upper surface of a substrate 2, first a pad 6 is obtained by forming a conductive film 61 made of a conductive material selectively containing Al in the opening 5 of this semiconductor chip 1. Next, the semiconductor chip 1 is mounted on a mounting substrate, and the pad 6 and the conductive portion of the mounting substrate are bonded using an Au wire 7.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特に搭載基板の導電部と半導体チップの配線
とのワイヤーボンディングに適用される半導体装置の製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device applied to wire bonding between a conductive portion of a mounting substrate and wiring of a semiconductor chip.

【０００２】[0002]

【従来の技術】ＬＳＩ（Large Scale Integrated-circu
it) チップ、ＩＣチップ（Integrated-Circuit) 等の半
導体チップには、最上層の配線上にパッド部が形成され
て、このパッド部と半導体チップが搭載されるＩＣパッ
ケージのリード部とがワイヤーボンディングされるもの
が知られている。上記パッド部は、最上層の配線上に形
成された絶縁膜を開口して配線の一部を外側に臨ませた
状態で形成した部分である。現在、ワイヤーボンディン
グでは、例えば金（Ａｕ）線からなるワイヤーが用いら
れ、３００℃程度の温度で超音波を付加しながら加圧に
よってパッド部とＡｕワイヤーとを接合する超音波併用
熱圧着法が主流になっている。2. Description of the Related Art LSI (Large Scale Integrated-circu)
In semiconductor chips such as it) chips and IC chips (Integrated-Circuit), a pad portion is formed on the uppermost layer wiring, and this pad portion and a lead portion of an IC package on which the semiconductor chip is mounted are wire-bonded. Is known. The pad portion is a portion formed by opening an insulating film formed on the uppermost wiring so that a part of the wiring faces outside. At present, in wire bonding, for example, a wire made of a gold (Au) wire is used, and an ultrasonic combined thermocompression bonding method in which a pad portion and an Au wire are joined by pressure while applying ultrasonic waves at a temperature of about 300 ° C. It has become mainstream.

【０００３】なお、ワイヤーボンディングにおける接合
は、線材の金属原子（例えばＡｕワイヤーのＡｕ）が接
合部位の金属組織（例えばアルミニウム（Ａｌ））へ拡
散し、連続的な原子構造を形成することにより行われ
る、いわゆる固相拡散接合である。この拡散に要するエ
ネルギーは、上記したように熱、加圧、超音波等の形で
与えられる。[0003] Bonding in wire bonding is performed by diffusing metal atoms (for example, Au of an Au wire) of a wire into a metal structure (for example, aluminum (Al)) at a bonding portion to form a continuous atomic structure. This is the so-called solid phase diffusion bonding. The energy required for this diffusion is provided in the form of heat, pressure, ultrasonic waves, etc., as described above.

【０００４】ところで従来、半導体チップの配線材料に
は、加工の容易なＡｌ系合金が用いられていたが、高集
積化に伴う配線の微細化とこれによる高電流密度化の進
行とにより、エレクトロマイグレーション（ＥＭ）等に
よる断線が発生し易くなる等、十分な信頼性が得られ難
くなってきている。そのため、Ａｌに替えて銅（Ｃｕ）
が用いた配線形成技術の開発も進められている。Ｃｕは
比抵抗が１．８μΩｃｍとＡｌよりも低いためデバイス
の高速化に有利であり、しかもＡｌよりも高ＥＭ耐性を
有することから配線の信頼性の向上を図るうえで有効と
されている。Conventionally, an Al-based alloy that is easy to process has been used as a wiring material for a semiconductor chip. It is becoming difficult to obtain sufficient reliability, for example, disconnection due to migration (EM) or the like is likely to occur. Therefore, instead of Al, copper (Cu)
The development of the wiring formation technology used by the company is also underway. Cu has a specific resistance of 1.8 μΩcm, which is lower than that of Al, which is advantageous for increasing the speed of the device. Further, Cu has higher EM resistance than Al, and is effective in improving the reliability of wiring.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、Ｃｕを
用いて配線を形成した場合には、通常のＡｕ線を用いた
ワイヤーボンディングを行おうとすると、Ａｕワイヤー
とＣｕとの反応温度が４００℃程度と高くしかもＣｕの
硬度もＡｌに比較して高いために、パッド部にＡｕワイ
ヤーが接合されず、結果としてＩＣパッケージに組むこ
とができないという難点がある。However, when the wiring is formed using Cu, when the wire bonding using the normal Au wire is performed, the reaction temperature between the Au wire and Cu becomes about 400 ° C. Since the hardness of Cu is higher than that of Al, the Au wire is not bonded to the pad portion, and as a result, it cannot be assembled into an IC package.

【０００６】この解決策として、Ｃｕ配線上のパッド部
にＡｌ膜を一層追加する方法が提案されている（Advanc
ed Metallization "Electromigration in CMP-copper i
nterconnect with quarter micron size prepared by s
putter-reflow"(1996-Oct.-23,24) N.Misawa,et al p.1
51-154) 。ところが、この方法では配線層が一層追加さ
れることになるため、絶縁膜形成、スパッタリング、リ
ソグラフィやドライエッチングの工程が増える。よっ
て、製造が煩雑になるとともにコスト的にもデメリット
が大きく、これらの点から実際に半導体装置の製造に適
用することは困難であると考えられる。As a solution to this, a method has been proposed in which an Al film is further added to a pad portion on a Cu wiring (Advanc).
ed Metallization "Electromigration in CMP-copper i
nterconnect with quarter micron size prepared by s
putter-reflow "(1996-Oct.-23, 24) N. Misawa, et al p.1
51-154). However, in this method, an additional wiring layer is added, so that the steps of insulating film formation, sputtering, lithography, and dry etching increase. Therefore, the production becomes complicated and the cost is greatly disadvantageous. From these points, it is considered that it is difficult to actually apply the method to the production of a semiconductor device.

【０００７】一方、配線材料にこれまで通りＡｌ系合金
を用いながら、配線のＥＭを抑制する対策も種々検討さ
れている。しかしながら、半導体装置の高集積化に伴い
Ａｌの膜厚を減少させる傾向にあるため、Ａｌ膜が例え
ば３００ｎｍ程度と薄く、かつＡｌ膜上層に窒化チタン
（ＴｉＮ）等の反射防止膜（Anti Reflection Coating;
以下、ＡＲＣ膜と記す）が７０ｎｍ程度と比較的厚く形
成されるような配線構造の場合に、ワイヤーボンディン
グが困難になる不具合が生じる。On the other hand, various measures have been studied for suppressing EM of wiring while using an Al-based alloy as the wiring material as before. However, since the thickness of the Al film tends to decrease with the increase in the degree of integration of the semiconductor device, the Al film is thin, for example, about 300 nm, and an antireflection film (Anti Reflection Coating) such as titanium nitride (TiN) is formed on the Al film. ;
In the case of a wiring structure in which the ARC film is formed to be relatively thick, about 70 nm, a problem that wire bonding becomes difficult occurs.

【０００８】すなわち、パッド部となる開口部を形成す
るためにドライエッチングによってＡＲＣ膜を除去する
際、ＴｉＮ膜とＡｌ膜とのエッチングの選択比が小さい
ためにオーバーエッチングを行うと、Ａｌ膜も掘られて
しまってＡｌ膜がさらに薄くなる。その結果、パッド部
にＡｕワイヤーを用いたボンディングを行うと、Ａｌと
Ａｕとの固相拡散が十分に進まず、接合部にボイドが形
成されたり、Ａｕワイヤーの密着力が弱くてＡｕワイヤ
ーが剥がれる等の不具合が生じてしまうのである。ま
た、膜厚が３００ｎｍ程度のＡｌ膜へのワイヤーボンデ
ィングでは、一応接合が達成されるが、２００℃前後の
温度で長時間が経過すると、Ａｕの拡散量に対して供給
されるＡｌが不足するようになって接合部にボンドが生
じ易くなる。That is, when the ARC film is removed by dry etching to form an opening serving as a pad portion, the overetching is performed because the etching selectivity between the TiN film and the Al film is small. The Al film is further thinned by being dug. As a result, when the bonding using the Au wire is performed on the pad portion, the solid phase diffusion of Al and Au does not sufficiently proceed, and a void is formed at the bonding portion or the adhesion force of the Au wire is weak and the Au wire is weakened. Problems such as peeling occur. In the wire bonding to an Al film having a thickness of about 300 nm, the bonding can be achieved for a time. However, when a long time elapses at a temperature of about 200 ° C., the amount of Al supplied becomes insufficient with respect to the diffusion amount of Au. As a result, a bond is easily generated at the joint.

【０００９】またＴｉＮ膜は、バリアメタルとしても用
いられるようにＣｕ膜よりもさらにＡｕワイヤーと反応
し難い膜である。したがって、開口部を形成するための
ＡＲＣ膜のドライエッチングの際に、オーバーエッチン
グによりさらにＡｌ膜を薄膜化しないようにＴｉＮ膜を
残した場合にも、通常のワイヤーボンディングによって
パッド部にＡｕワイヤーを接合することができない。し
たがって、Ｃｕ配線や薄膜化したＡｌ配線を用いた場合
に、確実にワイヤーボンディングを行え、電気的信頼性
の高い半導体装置を製造できる製造方法の確立が切望さ
れている。[0009] The TiN film is a film which is harder to react with the Au wire than the Cu film so as to be used as a barrier metal. Therefore, when dry etching of the ARC film for forming the opening, even if the TiN film is left so as not to make the Al film thinner by over-etching, the Au wire is applied to the pad portion by ordinary wire bonding. Cannot be joined. Therefore, when a Cu wiring or a thinned Al wiring is used, it is desired to establish a manufacturing method capable of reliably performing wire bonding and manufacturing a semiconductor device having high electrical reliability.

【００１０】[0010]

【課題を解決するための手段】そこで、上記課題を解決
するために本発明は、基体の上面に配線とこれを覆う絶
縁膜とこの絶縁膜に形成されて上記配線を外側に臨ませ
る開口部とを有してなる半導体チップを用い、まずこの
半導体チップの開口部内に選択的にＡｌを含む導電材料
からなる導電膜を形成してパッド部を得、次いで半導体
チップを搭載基板に搭載して、パッド部と搭載基板の導
電部とをワイヤーボンディングする構成となっている。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a wiring, an insulating film covering the wiring, and an opening formed in the insulating film to expose the wiring to the outside. First, a conductive film made of a conductive material containing Al is selectively formed in an opening of the semiconductor chip to obtain a pad portion, and then the semiconductor chip is mounted on a mounting substrate. The pad portion and the conductive portion of the mounting substrate are wire-bonded.

【００１１】この発明では、開口部内にＡｌを含む導電
材料からなる導電膜を形成してパッド部を得た後、パッ
ド部と搭載基板の導電部とをワイヤーボンディングする
ため、たとえ配線がＣｕからなって、このＣｕを外側に
臨ませた状態で開口部が形成され、しかもＣｕとの接合
が困難なＡｕワイヤーを用いてボンディングを行う場合
にも、ボンディングに何ら影響がなく、パッド部とＡｕ
ワイヤーとが密着性よく接合されることになる。同様
に、配線の最上層が、Ａｕワイヤーとの接合がさらに困
難なＴｉＮ膜からなり、このＴｉＮ膜を外部に露出させ
た状態で開口部が形成されていても、パッド部とＡｕワ
イヤーとが密着性よく接合されることになる。さらに、
配線が薄膜化したＡｌからなっていても、このＡｌ配線
上にＡｌを含む導電膜を形成してパッド部を得ることか
ら接合部におけるＡｌ膜の膜厚が厚くなるので、パッド
部とワイヤーとをボンディングする際、ワイヤーの拡散
量に対して十分なＡｌが供給されることになる。よっ
て、Ａｌとワイヤーとの固相拡散が十分に進むため、接
合部におけるボイドの発生が防止される。またパッド部
とワイヤーとが密着性良く接合されてワイヤーが剥がれ
ることもない。According to the present invention, a conductive film made of a conductive material containing Al is formed in the opening to obtain a pad portion, and then the pad portion and the conductive portion of the mounting substrate are wire-bonded. Therefore, even when an opening is formed with the Cu facing outward and bonding is performed using an Au wire that is difficult to bond with Cu, the bonding is not affected at all and the pad portion and the Au are not affected.
The wire and the wire are joined with good adhesion. Similarly, even if the uppermost layer of the wiring is made of a TiN film that is more difficult to bond with the Au wire, and the opening is formed in a state where the TiN film is exposed to the outside, the pad portion and the Au wire are still in contact with each other. It will be joined with good adhesion. further,
Even if the wiring is made of thinned Al, a conductive film containing Al is formed on this Al wiring to obtain a pad portion, so that the thickness of the Al film at the bonding portion is increased. When bonding, a sufficient amount of Al with respect to the diffusion amount of the wire is supplied. Therefore, the solid phase diffusion between Al and the wire sufficiently proceeds, so that the occurrence of voids at the joint is prevented. Further, the pad portion and the wire are joined with good adhesion, and the wire does not peel off.

【００１２】[0012]

【発明の実施の形態】以下、本発明に係る半導体装置の
製造方法の実施形態を説明するが、ここでは特に本発明
の特徴であるパッド部の形成工程およびワイヤーボンデ
ィング工程を示した図面を用いて実施形態を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described. Here, a drawing showing a pad forming step and a wire bonding step, which are features of the present invention, will be particularly described. An embodiment will be described.

【００１３】図１（ａ）〜（ｃ）は本発明の第１実施形
態に係る半導体装置の製造方法を工程順に示した要部側
断面図である。第１実施形態では、半導体装置を製造す
るに先立ち、図１（ａ）に示すようなＬＳＩチップから
なる半導体チップ１を用意する。すなわち、半導体チッ
プ１においては、例えばウエハからなる基板（図示略）
に半導体素子が形成されて基体２が構成されており、基
体２の最表面が酸化シリコン（ＳｉＯ2 ）膜からなる絶
縁膜２ａとなっている。そして、この基体２の上面に半
導体チップ１における最上層の配線３が形成されてい
る。FIGS. 1A to 1C are main-part sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps. In the first embodiment, prior to manufacturing a semiconductor device, a semiconductor chip 1 composed of an LSI chip as shown in FIG. 1A is prepared. That is, in the semiconductor chip 1, for example, a substrate (not shown) formed of a wafer
A substrate 2 is formed by forming a semiconductor element on the substrate 1. The outermost surface of the substrate 2 is an insulating film 2a made of a silicon oxide (SiO 2 ) film. The wiring 3 of the uppermost layer in the semiconductor chip 1 is formed on the upper surface of the base 2.

【００１４】配線３は例えば、基体２上面に形成された
バリアメタル層３１と、バリアメタル層３１上に形成さ
れた配線層３２と、この上層に形成されたＡＲＣ膜（反
射防止膜）３３とからなる。上記バリアメタル層３１
は、２０ｎｍ程度の膜厚のチタン（Ｔｉ）膜と、Ｔｉ膜
上に積層された２０ｎｍ程度のＴｉＮ膜とから構成され
ており、配線層３２は４００ｎｍ程度の膜厚のＣｕ膜で
形成されている。さらにＡＲＣ膜３３は、５ｎｍ程度の
Ｔｉ膜の上層に７０ｎｍ程度のＴｉＮ膜が積層されて形
成されている。The wiring 3 includes, for example, a barrier metal layer 31 formed on the upper surface of the base 2, a wiring layer 32 formed on the barrier metal layer 31, and an ARC film (anti-reflection film) 33 formed thereon. Consists of The barrier metal layer 31
Is composed of a titanium (Ti) film having a thickness of about 20 nm and a TiN film having a thickness of about 20 nm laminated on the Ti film, and the wiring layer 32 is formed of a Cu film having a thickness of about 400 nm. I have. The ARC film 33 is formed by stacking a TiN film of about 70 nm on a Ti film of about 5 nm.

【００１５】上記配線３が形成された基体２上面には、
配線３を覆うようにして例えば窒化シリコン（ＳｉＮ）
膜からなる絶縁膜４が形成されている。また絶縁膜４の
上記パッド部を形成する位置には、配線３に達しかつ配
線３の最上層であるＡＲＣ膜３３のＴｉＮ膜を外側に臨
ませた状態で開口部５が形成されている。On the upper surface of the base 2 on which the wiring 3 is formed,
For example, silicon nitride (SiN) so as to cover the wiring 3
An insulating film 4 made of a film is formed. An opening 5 is formed in the insulating film 4 at a position where the pad portion is to be formed, with the TiN film of the ARC film 33 which is the uppermost layer of the wiring 3 reaching the wiring 3 and facing the outside.

【００１６】このような半導体チップ１を用意した後
は、まず選択成長Ａｌ−ＣＶＤ（化学的気相成長）法を
用いて、図１（ｂ）に示すように開口部５内に選択的に
Ａｌを堆積させてＡｌ膜からなる導電膜６１を形成する
ことによりパッド部６を得る。ここでは、導電膜６１を
５００ｎｍ程度の厚みに形成する。選択成長Ａｌ−ＣＶ
Ｄ法を用いた導電膜６１の堆積条件の一例およびこの堆
積の前に実施するプレクリーン条件の一例を以下に示
す。After preparing such a semiconductor chip 1, first, as shown in FIG. 1B, the semiconductor chip 1 is selectively formed in the opening 5 by selective growth Al-CVD (chemical vapor deposition). The pad portion 6 is obtained by depositing Al to form a conductive film 61 made of an Al film. Here, the conductive film 61 is formed to a thickness of about 500 nm. Selective growth Al-CV
An example of the conditions for depositing the conductive film 61 using the method D and an example of the pre-clean conditions performed before the deposition are shown below.

【００１７】＜プレクリーン条件＞ 反応ガスおよび流量；ＢＣｌ3 ／Ａｒ：１００ｓｃｃｍ
／１００ｓｃｃｍ〔ｓｃｃｍは標準状態における体積流
量（ｃｍ3 ／分）〕 雰囲気圧力；１３３Ｐａ（１．０Ｔｏｒｒ） ＲＦパワー；５００Ｗ ＜Ａｌ−ＣＶＤ条件＞ 反応ガスおよび流量；ＤＭＡＨ〔Ａｌ（ＣＨ3)2 Ｈ〕：
５０ｓｃｃｍ キャリアガスおよび流量；Ｈ2 ：５００ｓｃｃｍ 雰囲気圧力；２６７Ｐａ（２．０Ｔｏｒｒ） 温度；２２０℃<Preclean conditions> Reaction gas and flow rate: BCl 3 / Ar: 100 sccm
/ 100 sccm [sccm is the volume flow rate under standard conditions (cm 3 / min)] Atmospheric pressure; 133 Pa (1.0 Torr) RF power; 500 W <Al-CVD conditions> Reaction gas and flow rate; DMAH [Al (CH 3 ) 2 H ]:
50 sccm carrier gas and flow rate; H 2 : 500 sccm atmosphere pressure; 267 Pa (2.0 Torr) temperature; 220 ° C.

【００１８】次いで、通常の半導体装置の製造における
後工程において、例えば搭載基板としてパッケージ（図
示略）に半導体チップ１を搭載する。そして、Ａｕワイ
ヤー７を用いてパッケージの導電部、例えばリード部と
パッド部６とのワイヤーボンディングを例えば超音波併
用熱圧着法により行う。その後は、例えば半導体チップ
とパッケージのリード部とを一体に封止して半導体装置
を得る。Next, in a post-process of manufacturing a normal semiconductor device, the semiconductor chip 1 is mounted on a package (not shown) as a mounting substrate, for example. Then, using the Au wire 7, wire bonding between the conductive portion of the package, for example, the lead portion and the pad portion 6, is performed by, for example, thermocompression combined use with ultrasonic waves. After that, for example, the semiconductor device is obtained by integrally sealing the semiconductor chip and the lead of the package.

【００１９】なお、上記ワイヤーボンディングにおける
条件例を以下に示す。 ＜ワイヤーボンディング条件＞ 温度；２９０℃ 超音波印加時間；２０ミリ秒 荷重；５０グラムAn example of conditions in the wire bonding is shown below. <Wire bonding conditions> Temperature: 290 ° C Ultrasonic application time: 20 ms Load: 50 g

【００２０】上記したように第１実施形態では、配線３
上に形成した開口部５内にＡｌの導電膜６１を選択的に
堆積してパッド部６を得た後、このパッド部６とＡｕワ
イヤー７とのワイヤーボンディングを行っている。この
ため、Ａｕとの接合が困難なＡＲＣ層３３のＴｉＮ膜を
外側に臨ませた状態で開口部５が形成されていても、ワ
イヤーボンディングに何ら影響がなく、パッド部６とＡ
ｕワイヤー７とを密着性良く接合することができる。よ
って、パッケージと半導体チップ１との良好な電気的導
通を得ることができる。As described above, in the first embodiment, the wiring 3
After selectively depositing a conductive film 61 of Al in the opening 5 formed above to obtain a pad portion 6, wire bonding between the pad portion 6 and the Au wire 7 is performed. For this reason, even if the opening 5 is formed with the TiN film of the ARC layer 33 facing the outside difficult to bond with Au, there is no effect on wire bonding, and the pad 6 and the A
The u wire 7 can be joined with good adhesion. Therefore, good electrical continuity between the package and the semiconductor chip 1 can be obtained.

【００２１】また、開口部５内を埋込むようにして導電
膜６１が形成されることから導電膜６１を厚く形成でき
るため、上記ボンディングの際にＡｕワイヤー７の拡散
量に対して十分なＡｌを供給できる。よって、パッド部
６のＡｌとＡｕワイヤー７との固相拡散が十分に進むた
め、接合部におけるボイドの発生も防止できる。さらに
選択成長Ａｌ−ＣＶＤ法によって、開口部５内に選択的
に導電膜６１を形成できるため、工程数の増加はこの導
電膜６１を形成する一工程だけで済む。したがって、電
気的信頼性が向上し、配線層３２が低抵抗なＣｕで形成
されて高速化された高集積ＬＳＩからなる半導体装置を
容易に製造することができる。Further, since the conductive film 61 is formed so as to fill the inside of the opening 5, the conductive film 61 can be formed thick, so that sufficient Al is supplied with respect to the diffusion amount of the Au wire 7 during the bonding. it can. Therefore, solid phase diffusion between the Al of the pad portion 6 and the Au wire 7 proceeds sufficiently, so that the occurrence of voids at the joint portion can be prevented. Further, since the conductive film 61 can be selectively formed in the opening 5 by the selective growth Al-CVD method, the number of steps is increased by only one step of forming the conductive film 61. Therefore, electrical reliability is improved, and a semiconductor device composed of a high-speed integrated LSI in which the wiring layer 32 is formed of low-resistance Cu and whose speed is increased can be easily manufactured.

【００２２】次に、本発明に係る半導体装置の製造方法
の第２実施形態を図２に基づいて説明する。なお、図２
（ａ）〜（ｄ）は第２実施形態を工程順に示した要部側
断面図であり、図において第１実施形態と同一の形成要
素には同一の符号を付して説明を省略する。Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. Note that FIG.
(A)-(d) is a principal part side sectional view showing the second embodiment in the order of steps. In the drawings, the same reference numerals are given to the same forming elements as in the first embodiment, and the description will be omitted.

【００２３】第２実施形態において、第１実施形態と相
違するところは、導電膜６２の形成にスパッタリング法
および化学的機械研磨（Chemical Mechanical Polishin
g;以下，ＣＭＰと記す）法を用いたことにある。すなわ
ち、第２実施形態においても図２（ａ）に示すように、
半導体装置を製造するに先立ち、第１実施形態の場合と
同様に構成された半導体チップ１を用意する。The second embodiment differs from the first embodiment in that the conductive film 62 is formed by a sputtering method and chemical mechanical polishing (Chemical Mechanical Polishing).
g; hereinafter, referred to as CMP) method. That is, also in the second embodiment, as shown in FIG.
Prior to manufacturing a semiconductor device, a semiconductor chip 1 having the same configuration as in the first embodiment is prepared.

【００２４】そして、まず図２（ｂ）に示すように、ス
パッタリング法を用いて絶縁膜４の全面に導電材料の
膜、ここではＡｌ膜６２ａを堆積するとともにＡｌ膜６
２ａで開口部５内を埋込む。この際のＡｌ膜６２ａの膜
厚は例えば２．０μｍ程度とする。スパッタリング法を
用いたＡｌ膜６２ａの堆積条件の一例を以下に示す。ま
たＡｌ膜６２ａの堆積前にＲＦエッチングによって、Ａ
ＲＣ層３３のＴｉＮ膜表面に形成された自然酸化膜を除
去するプレクリーンを行う。Then, as shown in FIG. 2B, a film of a conductive material, here an Al film 62a, is deposited on the entire surface of the insulating film 4 by sputtering, and the Al film 6 is formed.
The opening 5 is buried in 2a. At this time, the thickness of the Al film 62a is, for example, about 2.0 μm. An example of the deposition conditions for the Al film 62a using the sputtering method is shown below. Before the deposition of the Al film 62a, A
A pre-clean for removing a natural oxide film formed on the surface of the TiN film of the RC layer 33 is performed.

【００２５】＜プレクリーン条件＞ エッチングガスおよび流量；Ａｒ：３０ｓｃｃｍ 雰囲気圧力；０．２７Ｐａ（２ｍＴｏｒｒ） ＲＦパワー；５００Ｗ ＴｉＮ膜エッチング量；１０ｎｍ ＜Ａｌスパッタリング条件＞ スパッタリングガスおよび流量；Ａｒ：９０ｓｃｃｍ 雰囲気圧力；０．６７Ｐａ（５ｍＴｏｒｒ） ＤＣパワー；１２ｋＷ 温度；２２０℃<Preclean conditions> Etching gas and flow rate; Ar: 30 sccm atmosphere pressure; 0.27 Pa (2 mTorr) RF power; 500 W TiN film etching amount; 10 nm <Al sputtering conditions> Sputtering gas and flow rate: Ar: 90 sccm atmosphere pressure 0.67 Pa (5 mTorr) DC power; 12 kW Temperature; 220 ° C.

【００２６】次いで、ＣＭＰ法によって、図２（ｃ）に
示すように開口部５内のＡｌ膜６２ａを残した状態で絶
縁膜４の上面が露出する位置までＡｌ膜６２ａを除去す
る。このことによって、開口部５内にＡｌからなる導電
膜６２を選択的に形成してパッド部６を得る。ＣＭＰの
条件例を以下に示す。Next, as shown in FIG. 2C, the Al film 62a is removed to a position where the upper surface of the insulating film 4 is exposed while the Al film 62a in the opening 5 is left as shown in FIG. As a result, the conductive film 62 made of Al is selectively formed in the opening 5 to obtain the pad 6. An example of the conditions for CMP is shown below.

【００２７】＜ＣＭＰ条件＞ 研磨材（スラリー）；過酸化水素水＋アルミナ スラリー流量；２０ｓｃｃｍ 研磨ヘッド圧力；４．０ｐｓｉ 基体（ウエハ）回転数；２０ｒｐｍ ヘッド回転数；２０ｒｐｍ<CMP Conditions> Abrasive (slurry); Hydrogen peroxide water + alumina Slurry flow rate: 20 sccm Polishing head pressure: 4.0 psi Substrate (wafer) rotation speed: 20 rpm Head rotation speed: 20 rpm

【００２８】その後は、第１実施形態と同様にして、例
えばパッケージ（図示略）に半導体チップ１を搭載し、
図２（ｄ）に示すようにＡｕワイヤー７を用いてパッケ
ージのリード部とパッド部６とのワイヤーボンディング
を例えば超音波併用熱圧着法により行う。そして、例え
ば半導体チップ１とパッケージのリード部とを一体に封
止して半導体装置を得る。なお、上記ワイヤーボンディ
ングの条件は、例えば第１実施形態にて示した条件が採
用される。Thereafter, similarly to the first embodiment, the semiconductor chip 1 is mounted on a package (not shown), for example.
As shown in FIG. 2D, wire bonding between the lead portion of the package and the pad portion 6 is performed by using an Au wire 7, for example, by thermocompression combined with ultrasonic waves. Then, for example, the semiconductor chip 1 and the lead portion of the package are integrally sealed to obtain a semiconductor device. The conditions for the wire bonding are, for example, the conditions described in the first embodiment.

【００２９】上記した第２実施形態においても、スパッ
タリング法およびＣＭＰ法を用いて配線３上に形成した
開口部５内にＡｌの導電膜６２を選択的に形成してパッ
ド部６を得た後、このパッド部６とＡｕワイヤー７との
ワイヤーボンディングを行っている。このため、第１実
施形態と同様に、Ａｕとの接合が難しいＡＲＣ層３３の
ＴｉＮ膜を外側に臨ませた状態で開口部５が形成されて
いても、パッド部６とＡｕワイヤー７とを密着性良く接
合することができ、パッケージと半導体チップ１との良
好な電気的導通を得ることができる。Also in the second embodiment described above, after the Al conductive film 62 is selectively formed in the opening 5 formed on the wiring 3 by using the sputtering method and the CMP method, the pad portion 6 is obtained. The wire bonding between the pad portion 6 and the Au wire 7 is performed. For this reason, as in the first embodiment, even if the opening 5 is formed with the TiN film of the ARC layer 33 facing the outside, which is difficult to bond with Au, the pad 6 and the Au wire 7 are connected. Good adhesion can be achieved, and good electrical conduction between the package and the semiconductor chip 1 can be obtained.

【００３０】また、開口部５内を埋込んだ状態に導電膜
６２が形成されることから導電膜６２を厚く形成できる
ため、第１実施形態と同様、ボイドを発生させることな
くパッド部６とＡｕワイヤー７とを密着性良く接合する
ことができる。さらにスパッタリング法による成膜およ
びＣＭＰ法によって、開口部５内に選択的に導電膜６２
を形成できるため、工程数の増加はこの導電膜６１を形
成する二工程だけで済む。したがって、工程数の増加を
抑制しつつパッド部６とＡｕワイヤー７とが確実に接合
された電気的信頼性の高い超高集積ＬＳＩからなる半導
体装置を製造することができるとともに、配線層３２が
Ｃｕで形成されているため半導体装置の高速化も図るこ
とができる。Further, since the conductive film 62 is formed so as to bury the inside of the opening 5, the conductive film 62 can be formed thicker. The Au wire 7 can be joined with good adhesion. Further, the conductive film 62 is selectively formed in the opening 5 by the film formation by the sputtering method and the CMP method.
Can be formed, the number of steps is increased only by two steps for forming the conductive film 61. Therefore, it is possible to manufacture a semiconductor device composed of an ultra-highly integrated LSI with high electrical reliability in which the pad portion 6 and the Au wire 7 are securely joined while suppressing an increase in the number of steps, and the wiring layer 32 is formed. Since the semiconductor device is formed of Cu, the speed of the semiconductor device can be increased.

【００３１】次に、本発明に係る半導体装置の製造方法
の第３実施形態を図３に基づいて説明する。なお、図３
（ａ）〜（ｃ）は第３実施形態を工程順に示した要部側
断面図であり、図において第１実施形態と同一の形成要
素には同一の符号を付して説明を省略する。Next, a third embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. Note that FIG.
(A)-(c) is a principal part sectional view showing the third embodiment in the order of steps. In the figure, the same reference numerals are given to the same forming elements as in the first embodiment, and the description will be omitted.

【００３２】第３実施形態では、半導体装置を製造する
に先立ち、図３（ａ）に示すような半導体チップ８を用
意する。すなわち、半導体チップ８では、例えば第１実
施形態と同様に構成された基体２の上面に最上層の配線
９が形成されている。配線９は例えば、基体２上面に形
成されたバリアメタル層９１と、バリアメタル層９１上
に形成された配線層９２と、この上層に形成されたＡＲ
Ｃ膜９３とからなる。上記バリアメタル層９１は、２０
ｎｍ程度の膜厚のＴｉ膜と、Ｔｉ膜上に積層された２０
ｎｍ程度のＴｉＮ膜とから構成されており、配線層９２
は３００ｎｍ程度の膜厚のＡｌ膜で形成されている。さ
らにＡＲＣ膜９３は、５ｎｍ程度のＴｉ膜の上層に７０
ｎｍ程度のＴｉＮ膜が積層されて形成されている。In the third embodiment, a semiconductor chip 8 as shown in FIG. 3A is prepared before manufacturing a semiconductor device. That is, in the semiconductor chip 8, for example, the uppermost layer wiring 9 is formed on the upper surface of the base 2 configured similarly to the first embodiment. The wiring 9 includes, for example, a barrier metal layer 91 formed on the upper surface of the base 2, a wiring layer 92 formed on the barrier metal layer 91, and an AR formed on this upper layer.
C film 93. The barrier metal layer 91 is composed of 20
a Ti film having a thickness of about nm and 20
and a TiN film of about nm.
Is formed of an Al film having a thickness of about 300 nm. Further, the ARC film 93 has a thickness of 70 nm on the Ti film of about 5 nm.
A TiN film of about nm is laminated and formed.

【００３３】上記配線９が形成された基体２上には、配
線９を覆うようにして絶縁膜４が形成されている。また
絶縁膜４のパッド部を形成する位置には、配線９の配線
層９２に達する開口部１０が形成されている。つまり、
開口部１０を形成する際のオーバーエッチングによっ
て、パッド部を形成する位置のＡＲＣ膜９３が除去され
てＡｌ膜の配線層９２を外側に臨ませた状態で開口部１
０が形成されている。またこの際、配線層９２もエッチ
ングされて１８０ｎｍ程度の膜厚に減少している。The insulating film 4 is formed on the substrate 2 on which the wiring 9 is formed so as to cover the wiring 9. An opening 10 that reaches the wiring layer 92 of the wiring 9 is formed at a position where the pad portion of the insulating film 4 is formed. That is,
The ARC film 93 at the position where the pad portion is to be formed is removed by over-etching when forming the opening 10, and the opening 1 is formed with the wiring layer 92 of the Al film facing outward.
0 is formed. At this time, the wiring layer 92 is also etched to reduce the film thickness to about 180 nm.

【００３４】このような半導体チップ８を用意した後
は、まず図３（ｂ）に示すように、選択成長Ａｌ−ＣＶ
Ｄ法を用いて、開口部１０内に選択的にＡｌを堆積させ
てＡｌ膜からなる導電膜１１１を形成することによりパ
ッド部１１を得る。ここでは、導電膜１１１を７００ｎ
ｍ程度の厚みに形成する。選択成長Ａｌ−ＣＶＤ法を用
いた導電膜１１１の堆積条件の例およびこの堆積の前に
実施するプレクリーン条件の例としては、第１実施形態
における導電膜６１の堆積条件およびプレクリーン条件
が挙げられる。After preparing such a semiconductor chip 8, first, as shown in FIG.
The pad portion 11 is obtained by selectively depositing Al in the opening portion 10 using the D method to form a conductive film 111 made of an Al film. Here, the conductive film 111 is 700 n
The thickness is about m. Examples of the deposition conditions for the conductive film 111 using the selective growth Al-CVD method and examples of the pre-clean conditions performed before the deposition include the deposition conditions and the pre-clean conditions for the conductive film 61 in the first embodiment. Can be

【００３５】次いで、通常の半導体装置の製造における
後工程において、例えば搭載基板としてパッケージ（図
示略）に半導体チップ１を搭載する。そして、Ａｕワイ
ヤー７を用いてパッケージのリード部とパッド部１１と
のワイヤーボンディングを例えば超音波併用熱圧着法に
より行う。その後は、例えば半導体チップ８とパッケー
ジのリード部とを一体に封止して半導体装置を得る。な
お、上記ワイヤーボンディングの条件は、例えば第１実
施形態にて示した条件が採用される。Next, in a subsequent step in the manufacture of a normal semiconductor device, the semiconductor chip 1 is mounted on a package (not shown) as a mounting substrate, for example. Then, wire bonding between the lead portion of the package and the pad portion 11 is performed by using the Au wire 7 by, for example, thermocompression combined with ultrasonic waves. Thereafter, for example, the semiconductor chip 8 and the lead portion of the package are integrally sealed to obtain a semiconductor device. The conditions for the wire bonding are, for example, the conditions described in the first embodiment.

【００３６】上記した第３実施形態では、配線９上に形
成した開口部１０内にＡｌの導電膜１１１を選択的に形
成してパッド部１１を得た後、このパッド部１１とＡｕ
ワイヤー７とのボンディングを行っている。このため、
オーバーエッチングによって上記のようにＡｌ膜の配線
層９２が薄膜化されても、導電膜１１１の形成によって
接合部におけるＡｌ膜が厚膜となるので、上記ボンディ
ングの際にＡｕワイヤー７の拡散量に対して十分なＡｌ
が供給されることになる。よって、パッド部１１のＡｌ
とＡｕワイヤー７との固相拡散が十分に進むため、ボイ
ドを発生させることなくパッド部１１とＡｕワイヤー７
とを密着性良く接合することができ、パッケージと半導
体チップ８との良好な電気的導通を得ることができる。In the above-described third embodiment, after the pad portion 11 is obtained by selectively forming the Al conductive film 111 in the opening portion 10 formed on the wiring 9, the pad portion 11 and the Au
The bonding with the wire 7 is performed. For this reason,
Even if the wiring layer 92 of the Al film is thinned as described above due to over-etching, the amount of diffusion of the Au wire 7 during the bonding is reduced because the Al film at the bonding portion becomes thick due to the formation of the conductive film 111. Al enough for
Will be supplied. Therefore, the Al
The solid phase diffusion between the Au wire 7 and the pad portion 11 and the Au wire 7 do not generate voids.
Can be joined with good adhesion, and good electrical conduction between the package and the semiconductor chip 8 can be obtained.

【００３７】また選択成長Ａｌ−ＣＶＤ法によって、開
口部１０内に選択的に導電膜１１１を形成できるため、
工程数の増加はこの導電膜１１１を形成する一工程だけ
で済む。したがって、工程数の増加を抑制しつつパッド
部１１とＡｕワイヤー７とが確実に接合された電気的信
頼性の高い超高集積ＬＳＩからなる半導体装置を実現で
きる。Since the conductive film 111 can be selectively formed in the opening 10 by the selective growth Al-CVD method,
The number of steps is increased only by one step of forming the conductive film 111. Therefore, it is possible to realize a semiconductor device composed of an ultra-highly integrated LSI with high electrical reliability in which the pad portion 11 and the Au wire 7 are securely joined while suppressing an increase in the number of steps.

【００３８】次に、本発明に係る半導体装置の製造方法
の第４実施形態を図４に基づいて説明する。なお、図４
（ａ）〜（ｄ）は第４実施形態を工程順に示した要部側
断面図であり、図において第３実施形態と同一の形成要
素には同一の符号を付して説明を省略する。Next, a fourth embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. FIG.
(A) to (d) are cross-sectional views of essential parts showing the fourth embodiment in the order of steps. In the drawings, the same components as those in the third embodiment are denoted by the same reference numerals, and description thereof will be omitted.

【００３９】第４実施形態では、半導体装置を製造する
に先立ち、図４（ａ）に示すような半導体チップ１２を
用意する。すなわち、半導体チップ１２では、例えば第
１実施形態と同様に構成された基体２の上面に最上層の
配線１３が形成されている。配線１３は例えば、基体２
上面に形成されたバリアメタル層１３１と、バリアメタ
ル層１３１上に形成された配線層１３２と、この上層に
形成されたＡＲＣ膜１３３とからなる。上記バリアメタ
ル層１３１は、２０ｎｍ程度の膜厚のＴｉ膜と、Ｔｉ膜
上に積層された２０ｎｍ程度のＴｉＮ膜とから構成され
ており、配線層１３２は３００ｎｍ程度の膜厚のＣｕ膜
で形成されている。さらにＡＲＣ膜１３３は、５ｎｍ程
度のＴｉ膜の上層に７０ｎｍ程度のＴｉＮ膜が積層され
て形成されている。In the fourth embodiment, prior to manufacturing a semiconductor device, a semiconductor chip 12 as shown in FIG. 4A is prepared. That is, in the semiconductor chip 12, for example, the uppermost layer wiring 13 is formed on the upper surface of the base 2 configured in the same manner as in the first embodiment. The wiring 13 is, for example, the base 2
It comprises a barrier metal layer 131 formed on the upper surface, a wiring layer 132 formed on the barrier metal layer 131, and an ARC film 133 formed thereon. The barrier metal layer 131 is composed of a Ti film having a thickness of about 20 nm and a TiN film having a thickness of about 20 nm laminated on the Ti film, and the wiring layer 132 is formed of a Cu film having a thickness of about 300 nm. Have been. Further, the ARC film 133 is formed by stacking a TiN film of about 70 nm on a Ti film of about 5 nm.

【００４０】上記配線１３が形成された基体２上には、
配線１３を覆うようにして絶縁膜４が形成されている。
また絶縁膜４のパッド部を形成する位置には、配線１３
の配線層１３２に達する開口部１４が形成されている。
つまり、開口部１４を形成する際のオーバーエッチング
によって、パッド部を形成する位置のＡＲＣ膜１３３が
除去されて配線層１３２を外側に臨ませた状態で開口部
１４が形成されている。またこの際、配線層１３２もエ
ッチングされて２００ｎｍ程度の膜厚に減少している。On the substrate 2 on which the wiring 13 is formed,
An insulating film 4 is formed so as to cover the wiring 13.
In the position where the pad portion of the insulating film 4 is formed, the wiring 13 is formed.
The opening 14 reaching the wiring layer 132 is formed.
That is, the ARC film 133 at the position where the pad is to be formed is removed by overetching when forming the opening 14, and the opening 14 is formed with the wiring layer 132 facing outward. At this time, the wiring layer 132 is also etched to reduce the film thickness to about 200 nm.

【００４１】このような半導体チップ１２を用意した後
は、まず図４（ｂ）に示すように、スパッタリング法を
用いてＴｉＮ膜からなるバリアメタル膜１５を絶縁膜４
の全面に形成するとともに開口部１４の内面を覆うよう
に形成する。この際のバリアメタル膜１５の膜厚は例え
ば２０ｎｍ程度とする。After preparing such a semiconductor chip 12, first, as shown in FIG. 4B, a barrier metal film 15 made of a TiN film is
And is formed so as to cover the inner surface of the opening 14. At this time, the thickness of the barrier metal film 15 is, for example, about 20 nm.

【００４２】次いで、絶縁膜４の全面にバリアメタル膜
１５を介してＡｌ膜１６１ａを堆積するとともに開口部
１５内にバリアメタル膜１５を介してＡｌ膜１６１ａを
埋込む。この際のＡｌ膜１６１ａの膜厚は例えば２．０
μｍ程度とする。スパッタリング法を用いたバリアメタ
ル膜１５、Ａｌ膜１６１ａのそれぞれの堆積条件の一例
を以下に示す。またＡｌ膜１６１ａの堆積前にＲＦエッ
チングによって、Ｃｕの配線層１３２表面に形成された
自然酸化膜を除去するプレクリーンを行う。Then, an Al film 161a is deposited on the entire surface of the insulating film 4 via the barrier metal film 15, and the Al film 161a is buried in the opening 15 via the barrier metal film 15. At this time, the thickness of the Al film 161a is, for example, 2.0
It is about μm. An example of the respective deposition conditions of the barrier metal film 15 and the Al film 161a using the sputtering method is shown below. Before the deposition of the Al film 161a, a pre-clean for removing a natural oxide film formed on the surface of the Cu wiring layer 132 by RF etching is performed.

【００４３】＜プレクリーン条件＞ エッチングガスおよび流量；Ａｒ：３０ｓｃｃｍ 雰囲気圧力；０．２７Ｐａ（２ｍＴｏｒｒ） ＲＦパワー；５００Ｗ Ｃｕ配線層エッチング量；１０ｎｍ ＜ＴｉＮスパッタリング条件＞ スパッタリングガスおよび流量；Ａｒ＋Ｎ2：６０ｓｃ
ｃｍ＋１２０ｓｃｃｍ 雰囲気圧力；０．６７Ｐａ（５ｍＴｏｒｒ） ＤＣパワー；８ｋＷ 温度；２００℃ ＜Ａｌスパッタリング条件＞ スパッタリングガスおよび流量；Ａｒ：９０ｓｃｃｍ 雰囲気圧力；０．６７Ｐａ（５ｍＴｏｒｒ） ＤＣパワー；１２ｋＷ 温度；２２０℃<Preclean conditions> Etching gas and flow rate; Ar: 30 sccm Atmospheric pressure; 0.27 Pa (2 mTorr) RF power; 500 W Cu wiring layer etching amount; 10 nm <TiN sputtering condition> Sputtering gas and flow rate: Ar + N 2 : 60 sc
cm + 120 sccm Atmospheric pressure; 0.67 Pa (5 mTorr) DC power; 8 kW Temperature; 200 ° C. <Al sputtering conditions> Sputtering gas and flow rate: Ar: 90 sccm Atmospheric pressure; 0.67 Pa (5 mTorr) DC power; 12 kW Temperature; 220 ° C.

【００４４】次いで、ＣＭＰ法によって、図４（ｃ）に
示すように開口部１４内のＡｌ膜１６１ａおよびバリア
メタル膜１５を残した状態で絶縁膜４の上面が露出する
位置までＡｌ膜１６１ａおよびバリアメタル膜１５を除
去する。このことによって開口部１４内にバリアメタル
膜１５を介してＡｌからなる導電膜１６１を選択的に形
成してパッド部１６を得る。このときのＣＭＰ条件とし
ては、例えば第２実施形態におけるＣＭＰ条件が採用さ
れる。Next, as shown in FIG. 4C, the Al film 161a and the Al film 161a are removed by CMP until the upper surface of the insulating film 4 is exposed with the Al film 161a and the barrier metal film 15 remaining in the opening 14. The barrier metal film 15 is removed. As a result, a conductive film 161 made of Al is selectively formed in the opening 14 via the barrier metal film 15 to obtain the pad portion 16. As the CMP condition at this time, for example, the CMP condition in the second embodiment is adopted.

【００４５】次いで、通常の半導体装置の製造における
後工程において、例えば搭載基板としてパッケージ（図
示略）に半導体チップ１を搭載する。そして、Ａｕワイ
ヤー７を用いてパッケージのリード部とパッド部１６と
のワイヤーボンディングを例えば超音波併用熱圧着法に
より行った後、例えば半導体チップ１２とパッケージの
リード部とを一体に封止して半導体装置を得る。なお、
上記ワイヤーボンディングの条件は、例えば第１実施形
態にて示した条件が採用される。Next, in a later step in the manufacture of a normal semiconductor device, the semiconductor chip 1 is mounted on a package (not shown) as a mounting substrate, for example. Then, after the wire bonding between the lead portion of the package and the pad portion 16 is performed by using, for example, an ultrasonic combined thermocompression bonding method using the Au wire 7, for example, the semiconductor chip 12 and the package lead portion are integrally sealed. Obtain a semiconductor device. In addition,
As the conditions of the wire bonding, for example, the conditions described in the first embodiment are employed.

【００４６】上記した第４実施形態では、配線１３上に
形成した開口部１４内に、スパッタリング法およびＣＭ
Ｐ法を用いてＡｌの導電膜１６１を選択的に形成してパ
ッド部１６を得た後、このパッド部１６とＡｕワイヤー
７とのワイヤーボンディングを行っている。このため、
開口部１４の内面と導電膜１６１との間にＡｕの接合が
難しいＴｉＮ膜からなるバリアメタル膜１５が形成され
ていても、ワイヤーボンディングに何ら影響がなく、パ
ッド部１６とＡｕワイヤー７とを密着性良く接合するこ
とができる。よってパッケージと半導体チップ１２との
良好な電気的導通を得ることができる。In the fourth embodiment described above, the sputtering method and the CM are used in the opening 14 formed on the wiring 13.
After the pad portion 16 is obtained by selectively forming the Al conductive film 161 using the P method, wire bonding between the pad portion 16 and the Au wire 7 is performed. For this reason,
Even if the barrier metal film 15 made of a TiN film, to which Au is difficult to bond, is formed between the inner surface of the opening 14 and the conductive film 161, there is no effect on wire bonding, and the pad portion 16 and the Au wire 7 Bonding can be performed with good adhesion. Therefore, good electrical conduction between the package and the semiconductor chip 12 can be obtained.

【００４７】またこの実施形態においても、開口部１４
内を埋込んだ状態に導電膜１６１が形成されることによ
り、Ａｌからなる導電膜１６１を厚く形成できることか
ら、ボイドを発生させることなくパッド部１６とＡｕワ
イヤー７とを密着性良く接合できる。しかも、導電膜１
６１を形成するためにスパッタリング法とＣＭＰ法との
二工程を増加させるだけで済む。したがって、電気的信
頼性が向上し、配線層１３２が低抵抗なＣｕで形成され
て高速化された高集積ＬＳＩからなる半導体装置を容易
に製造することができる。Also in this embodiment, the opening 14
By forming the conductive film 161 in a state in which the inside is buried, the conductive film 161 made of Al can be formed thick, so that the pad portion 16 and the Au wire 7 can be bonded with good adhesion without generating voids. Moreover, the conductive film 1
It is only necessary to increase two steps of the sputtering method and the CMP method to form 61. Therefore, the electrical reliability is improved, and a semiconductor device composed of a high-speed integrated LSI in which the wiring layer 132 is formed of low-resistance Cu and whose speed is increased can be easily manufactured.

【００４８】なお、上記第１実施形態〜第４実施形態で
は、Ａｌ膜で導電膜を形成したが、ワイヤーボンディン
グで用いるワイヤーと接合可能なＡｌを含む導電材料で
形成されればよく、実施形態の例に限定されない。ま
た、配線がＡｌあるいはＣｕで形成されている例を述べ
たが、その他、種々の配線材料を用いてもよいのはもち
ろんである。例えばＣｕ以外のワイヤーボンディングで
用いるＡｕワイヤーとのボンディングが困難な配線材料
を用いてもよく、この場合にもパッド部とワイヤーとを
確実に接合するできる効果が得られる。In the first to fourth embodiments, the conductive film is formed of an Al film. However, the conductive film may be formed of a conductive material containing Al which can be bonded to a wire used in wire bonding. Is not limited to the example. Further, the example in which the wiring is formed of Al or Cu has been described, but it is a matter of course that various other wiring materials may be used. For example, a wiring material other than Cu that is difficult to bond with an Au wire used in wire bonding may be used, and in this case also, an effect that the pad portion and the wire can be securely bonded is obtained.

【００４９】また第１実施形態〜第４実施形態で述べた
条件等は一例であって、本発明の主旨に反しない限り適
宜変更可能である。The conditions and the like described in the first to fourth embodiments are merely examples, and can be appropriately changed without departing from the gist of the present invention.

【００５０】[0050]

【発明の効果】以上説明したように本発明の半導体装置
の製造方法によれば、開口部内にＡｌを含む導電材料か
らなる導電膜を形成してパッド部を得た後、パッド部と
搭載基板の導電部とをワイヤーボンディングするように
したことにより、たとえワイヤーとの接合が困難な配線
材料を外側に臨ませた状態で開口部が形成されていて
も、パッド部とワイヤーとが密着性良く接合することが
できる。また、配線が薄膜化したＡｌからなっていて
も、このＡｌ配線上にＡｌを含む導電膜を形成してパッ
ド部を得ることから、パッド部のＡｌとワイヤーとの固
相拡散を十分に進ませることができ、接合部におけるボ
イドの発生を防止できる。したがって、電気的信頼性が
高い高集積ＬＳＩからなる半導体装置を実現することが
できる。As described above, according to the method for manufacturing a semiconductor device of the present invention, a conductive film made of a conductive material containing Al is formed in an opening to obtain a pad portion, and then the pad portion and a mounting substrate are formed. By conducting wire bonding with the conductive part, even if the opening is formed with the wiring material that is difficult to bond with the wire facing outside, the pad part and the wire have good adhesion. Can be joined. Further, even if the wiring is made of thinned Al, a conductive film containing Al is formed on the Al wiring to obtain a pad portion, so that solid phase diffusion between the Al and the wire in the pad portion sufficiently proceeds. And the occurrence of voids at the joint can be prevented. Therefore, a semiconductor device including a highly integrated LSI with high electrical reliability can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】（ａ）〜（ｃ）は本発明の第１実施形態に係る
半導体装置の製造方法を工程順に示した要部側断面図で
ある。FIGS. 1A to 1C are cross-sectional views of a main part showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

【図２】（ａ）〜（ｄ）は本発明の第２実施形態に係る
半導体装置の製造方法を工程順に示した要部側断面図で
ある。FIGS. 2A to 2D are side sectional views of a main part showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

【図３】（ａ）〜（ｃ）は本発明の第３実施形態に係る
半導体装置の製造方法を工程順に示した要部側断面図で
ある。FIGS. 3A to 3C are side sectional views of a main part showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps.

【図４】（ａ）〜（ｄ）は本発明の第４実施形態に係る
半導体装置の製造方法を工程順に示した要部側断面図で
ある。FIGS. 4A to 4D are main-part side sectional views showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention in the order of steps;

【符号の説明】[Explanation of symbols]

１，８，１２…半導体チップ、２…基体、３，９，１３
…配線、４…絶縁膜、５，１０，１４…開口部、６，１
１，１６…パッド部、７…Ａｕワイヤー、１５…バリア
メタル膜、６１，６２，１１１，１６１…導電膜、６２
ａ、１６１ａ…Ａｌ膜1, 8, 12: semiconductor chip, 2: base, 3, 9, 13
... wiring, 4 ... insulating film, 5, 10, 14 ... opening, 6, 1
1, 16: pad portion, 7: Au wire, 15: barrier metal film, 61, 62, 111, 161: conductive film, 62
a, 161a ... Al film

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 基体の上面に配線とこれを覆う絶縁膜と
該絶縁膜に形成されて前記配線を外側に臨ませる開口部
とを有してなる半導体チップを用い、この半導体チップ
の前記開口部内に選択的にアルミニウムを含む導電材料
からなる導電膜を形成してパッド部を得る工程と、 前記パッド部を形成した半導体チップを搭載基板に搭載
して、前記パッド部と前記搭載基板の導電部とをワイヤ
ーボンディングする工程とを有していることを特徴とす
る半導体装置の製造方法。1. A semiconductor chip comprising a wiring on an upper surface of a base, an insulating film covering the wiring, and an opening formed on the insulating film to expose the wiring to the outside, wherein the opening of the semiconductor chip is used. Forming a conductive film made of a conductive material containing aluminum selectively in the portion to obtain a pad portion; mounting the semiconductor chip on which the pad portion is formed on a mounting substrate to form a conductive film between the pad portion and the mounting substrate; And a step of wire-bonding the semiconductor device to the semiconductor device. 【請求項２】 前記パッド部を得る工程では、化学的気
相成長法によって前記開口部内に選択的にアルミニウム
を成長させることにより前記導電膜を形成することを特
徴とする請求項１記載の半導体装置の製造方法。2. The semiconductor according to claim 1, wherein, in the step of obtaining the pad portion, the conductive film is formed by selectively growing aluminum in the opening portion by a chemical vapor deposition method. Device manufacturing method. 【請求項３】 前記パッド部を得る工程では、前記絶縁
膜の全面に前記導電材料の膜を形成するとともに該導電
材料で前記開口部内を埋込み、その後に化学的機械研磨
法によって、前記開口部内を埋め込んだ導電材料を残し
た状態で前記絶縁膜の上面が露出する位置まで前記導電
材料からなる膜を除去することにより前記導電膜を形成
することを特徴とする請求項１記載の半導体装置の製造
方法。3. In the step of obtaining the pad portion, a film of the conductive material is formed on the entire surface of the insulating film and the inside of the opening is buried with the conductive material, and then the inside of the opening is formed by a chemical mechanical polishing method. 2. The semiconductor device according to claim 1, wherein the conductive film is formed by removing the film made of the conductive material up to a position where the upper surface of the insulating film is exposed while leaving the conductive material embedded with the conductive material. 3. Production method. 【請求項４】 前記パッド部を得る工程に先立ち、前記
開口部の内面を覆うようにバリアメタル膜を形成するこ
とを特徴とする請求項１記載の半導体装置の製造方法。4. The method according to claim 1, wherein a barrier metal film is formed so as to cover an inner surface of the opening prior to the step of obtaining the pad portion.
JP15174997A 1997-06-10 1997-06-10 Manufacturing method of semiconductor device Expired - Fee Related JP3906522B2 (en)

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