JP2006324388A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the tolerance to process charging damage of a low dielectric constant film while at the same time improving its tolerance to both mechanical and thermal stress. <P>SOLUTION: The semiconductor device comprises first to fifth insulation films 2, 4, 5, 13, and 14 formed in this order from bottom to top on a substrate 1, a first dummy via 11 which consists of a first conductive material and is formed in the third insulation film 5, and a second dummy via 16 which consists of a second conductive material and is formed in the fifth insulation film 14. In top view, the second dummy via 16 is formed immediately above the first dummy via 11. The first dummy via 11 and the second dummy via 16 are electrically insulated from each other by the fourth insulation film 13. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, when a low dielectric constant film is used as an interlayer insulating film and a dummy pattern is disposed for CMP and stress mitigation, the low dielectric constant film is damaged by charging damage. The present invention relates to a method for forming a dummy pattern to be reduced and a method for manufacturing the same.

  2. Description of the Related Art In recent years, techniques for using a low dielectric constant film as an interlayer insulating film have been proposed along with higher integration, higher functionality, and higher speed of semiconductor integrated circuit devices. When a low dielectric constant insulating film is used as the interlayer insulating film, the wiring capacitance is reduced, so that the problem of signal delay can be avoided, and high speed, low power consumption, and high integration can be realized.

  However, the low dielectric constant film is disadvantageous in that it is vulnerable to mechanical or thermal stress and is liable to be peeled off or cracked. In order to avoid this problem, many techniques using dummy wirings and dummy vias have been proposed (see, for example, Patent Document 1).

  Hereinafter, an example of a method of forming dummy wirings and dummy vias in the low dielectric constant interlayer insulating film will be described with reference to FIGS.

  First, as shown in FIG. 5A, after forming a transistor or the like (not shown) on the P-type semiconductor substrate 1, the interlayer insulating film 2 is deposited, the contact plug 31 is formed, and then the first layer The Cu wiring 3 and the first layer Cu dummy wiring 21 are formed simultaneously. Thereafter, a SiC insulating film 4 is deposited. Next, as shown in FIG. 5B, after the first Low-k insulating film 5 is deposited, the first layer via hole 6 and the first layer dummy via hole 32 are dry-etched using the first SiC insulating film 4 as a stopper. Form. Next, as shown in FIG. 5C, after the second layer Cu wiring groove 9 and the second layer Cu dummy wiring groove 23 are simultaneously formed by dry etching, the first layer via hole 6 and the first layer via hole 6 are formed by dry etching. The SiC insulating film 4 at the bottom of the one-layer dummy via hole 32 is opened. Next, as shown in FIG. 6A, Cu is embedded in the trench and the hole, and the second layer Cu wiring 12, the first layer via 10, the second layer Cu dummy wiring 25, and the first layer dummy via 33 are simultaneously formed. After the formation, a second SiC insulating film 13 is deposited. Next, as shown in FIG. 6B, by repeating the same process described above, the second Low-k insulating film 14, the second layer via 15, the third layer Cu wiring 17, and the third layer Cu dummy wiring 27 are performed. After forming the second layer dummy via 34 at the same time, the third SiC insulating film 28 is deposited.

By repeating the above steps, dummy wirings and dummy vias can be formed in the low dielectric constant interlayer insulating film, and as a result, the interface of the low dielectric constant interlayer insulating film can be reduced, Since the dummy wirings and the dummy vias serve as pillars, it is possible to prevent peeling and cracking of the insulating film due to mechanical or thermal stress.
JP 2004-153015 A

  However, with the progress of miniaturization and multilayering of semiconductor integrated circuit devices, the wiring interval is reduced and the wiring forming process is lengthened, so that the charge-up in the wiring forming process impairs the insulation life of the low dielectric constant insulating film. Or the problem of dielectric breakdown occurs.

  Specifically, when the lowermost layer wiring is connected to the semiconductor substrate and the dummy wiring is arranged at the minimum distance from the wiring, in the case of the prior art, the dummy wiring and the dummy via are electrically connected to all layers. Because it is floating, excess voltage due to charge-up that occurs when forming each layer wiring / via is generated in the dummy wiring, and it is low dielectric between the lowermost wiring connected to the semiconductor substrate with the narrowest wiring interval The rate film is damaged many times. This damage becomes conspicuous with an increase in the number of wiring layers and a reduction in the wiring interval, which causes a decrease in the lifetime of the low dielectric constant film and a dielectric breakdown (see charge-up damage 35 in FIG. 6B).

  Therefore, in view of the above problems, the object of the present invention is to improve the resistance to process charging damage while improving the mechanical and thermal stress resistance of the low dielectric constant film, and to reduce the dielectric by charging up by the wiring formation process. An object of the present invention is to provide a semiconductor device in which the rate film is not damaged and a method for manufacturing the same.

  In order to solve the above-described problem, a semiconductor device according to claim 1 of the present invention is provided in first to fifth insulating films formed in order from below on a substrate and in the third insulating film. A first dummy via made of a first conductive material and a second dummy via made of a second conductive material provided in the fifth insulating film, and when seen in a plan view, The second dummy via is formed immediately above the first dummy via, and the first dummy via and the second dummy via are electrically insulated by the fourth insulating film.

  According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the semiconductor device according to the first aspect includes at least one laminated film including a pair of a lower insulating film and an upper insulating film on the fifth insulating film. An upper dummy via made of a conductive material is provided in the insulating film, and when viewed in plan, the upper dummy via is formed immediately above the second dummy via, and is disposed below the upper dummy via. The second dummy via is electrically insulated by the lower insulating film.

  The semiconductor device according to claim 3 is composed of first to fifth insulating films formed in order from below on a substrate, and a first conductive material provided on an upper portion in the first insulating film. A first dummy wiring; a first dummy via made of a second conductive material provided at a lower portion in the third insulating film; and an upper portion in the third insulating film. A second dummy wiring made of the second conductive material electrically connected to the first dummy via and a third conductive material made of a third conductive material provided in the lower portion of the fifth insulating film. A second dummy via and a third dummy wiring made of the third conductive material provided on the fifth insulating film and electrically connected to the second dummy via. As a matter of fact, the third dummy wiring is formed immediately above the second dummy wiring, The second dummy wiring is formed immediately above the first dummy wiring, and the first dummy via is formed in a region where the second dummy wiring is formed in a plan view. The dummy via is formed in a region where the third dummy wiring is formed in plan view, and the first dummy wiring and the first dummy via are electrically insulated by the second insulating film. The second dummy wiring and the second dummy via are electrically insulated by the fourth insulating film.

  The semiconductor device according to claim 4 is the semiconductor device according to claim 3, wherein a design value of the first dummy via is 95% or less of a design value of a via in the same layer, and the design of the second dummy via The value is 95% or less of the design value of the via in the same layer.

  The semiconductor device according to claim 5 is the semiconductor device according to claim 1 or 3, wherein the third insulating film and the fifth insulating film are films containing a low-k material, and the second insulating film The fourth insulating film is a film containing a SiC-based material.

  The semiconductor device according to claim 6 is the semiconductor device according to claim 1 or 3, wherein the third insulating film and the fifth insulating film are films containing a SiO-based material, and the second insulating film and The fourth insulating film is a film containing a SiN-based material.

  A semiconductor device according to a seventh aspect is the semiconductor device according to the first or third aspect, wherein at least one of the first to fifth insulating films is a multilayer film.

  9. The method of manufacturing a semiconductor device according to claim 8, wherein a first, second and third insulating films are formed on a substrate in order from the bottom, and a first via is formed in the third insulating film. Providing an opening, filling a first conductive material into the first via formation opening and embedding a first dummy via reaching the surface of the second insulating film; and the first dummy via Forming a fourth insulating film on the third insulating film including the upper part; forming a fifth insulating film on the fourth insulating film; and in the fifth insulating film A second via forming opening is provided, and the second conductive material is filled into the second via forming opening, and the second via forming opening is directly above the first dummy via in plan view. And a step of embedding and forming a second dummy via reaching the surface of the insulating film.

  The method of manufacturing a semiconductor device according to claim 9 is the method of manufacturing a semiconductor device according to claim 8, wherein at least a laminated film including a lower insulating film and an upper insulating film as a pair is formed on the fifth insulating film. A step of forming one layer, and in the upper insulating film, an opening in the upper layer reaching the surface of the lower insulating film is provided immediately above the second dummy via as viewed in plan, Filling the upper opening and filling the upper dummy via.

  The method for manufacturing a semiconductor device according to claim 10, wherein a first insulating film is formed on the substrate, and a first wiring forming opening is provided in an upper portion of the first insulating film. And filling the first wiring forming opening with the first conductive wiring and filling the first dummy wiring with the conductive material, and forming a second on the first insulating film including the first dummy wiring. Forming a second insulating film, forming a third insulating film on the second insulating film, providing a second wiring forming opening in the upper portion of the third insulating film, A first via forming opening is provided below the bottom surface of the second wiring forming opening, and a second conductive material is placed in the second wiring forming opening and in the first via forming opening. And in plan view, the second dummy wiring and the second dummy wiring are directly above and directly above the first dummy wiring. Embedding and forming first dummy vias reaching the surface of the edge film, forming a fourth insulating film on the third insulating film including the second dummy wiring, and the fourth Forming a fifth insulating film on the insulating film; providing a third wiring forming opening in an upper portion of the fifth insulating film; and forming a third wiring forming opening below the bottom surface of the third wiring forming opening. A second via forming opening is provided, and a third conductive material is filled in the third wiring forming opening and the second via forming opening, and the second via forming opening is viewed in plan view. And a step of embedding and forming a third dummy wiring and a second dummy via reaching the surface of the fourth insulating film immediately above the second dummy wiring.

  The semiconductor device manufacturing method according to claim 11 is the semiconductor device manufacturing method according to claim 10, wherein a design value of the size of the first dummy via is 95% or less of a design value of the size of the via in the same layer. The design value of the size of the second dummy via is 95% or less of the design value of the size of the via in the same layer.

  The method for manufacturing a semiconductor device according to claim 12 is the method for manufacturing a semiconductor device according to claim 8 or 10, wherein the third insulating film and the fifth insulating film are films containing a low-k material, The second insulating film and the fourth insulating film are films containing a SiC-based material.

  The method for manufacturing a semiconductor device according to claim 13 is the method for manufacturing a semiconductor device according to claim 8 or 10, wherein the third insulating film and the fifth insulating film are films containing a SiO-based material, The second insulating film and the fourth insulating film are films containing a SiN-based material.

  The method for manufacturing a semiconductor device according to claim 14 is the method for manufacturing a semiconductor device according to claim 8 or 10, wherein at least one of the first to fifth insulating films is a multilayer film.

  According to the semiconductor device of claim 1 of the present invention, the first dummy via made of the first conductive material provided in the third insulating film and the fifth insulating film provided in the fifth insulating film, A second dummy via made of a second conductive material, and the second dummy via is formed immediately above the first dummy via in plan view, and the first dummy via and the second dummy via are 4, even if low dielectric constant films are used for the third insulating film and the fifth insulating film in order to reduce the inter-wiring capacitance, the low dielectric constant interlayer insulating film By forming dummy vias inside, it is possible to reduce the interface of the low dielectric constant interlayer insulating film, and at the same time, the dummy vias formed in almost the same plane in different layers play the role of pillars. Or peeling of insulating film due to thermal stress, It is possible to prevent the rack.

  In addition, since the dummy vias in each layer are electrically insulated, the process charge-up damage that occurs in each layer is completed in each layer. Therefore, even if there is an arrangement where the distance between the dummy via and the wiring of a certain layer is minimized, the damage to that portion is completed only when the layer is formed, and an upper layer higher than that layer is formed as in the conventional case. Not all damage is accumulated. Therefore, it is possible to prevent the life deterioration and destruction of the low dielectric constant film due to the process charge-up damage. Furthermore, since the dummy is only the via, the dummy via can be effectively arranged in a stacked state even where the dummy wiring cannot be placed. As a result, the dummy via functions as a chip pillar and can further improve resistance to mechanical and thermal stress.

  As described above, while the mechanical and thermal stress resistance of the low dielectric constant film is improved, it is possible to prevent the life deterioration and destruction of the low dielectric constant film due to the charging damage in the process accompanying the miniaturization.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, at least one laminated film including a lower insulating film and an upper insulating film as a pair is provided on the fifth insulating film, and the conductive film is formed in the upper insulating film. An upper dummy via made of a conductive material is provided, and when viewed in plan, the upper dummy via is formed immediately above the second dummy via, and the upper dummy via and the second dummy via disposed below the lower dummy via are lower layers It is preferable that the insulating film is electrically insulated.

  According to the semiconductor device of the third aspect of the present invention, the first dummy wiring made of the first conductive material and the lower part in the third insulating film are provided in the upper part in the first insulating film. A first dummy via made of a second conductive material, and a second conductive material provided in an upper portion of the third insulating film and electrically connected to the first dummy via. A second dummy wiring, a second dummy via made of a third conductive material provided in the lower part of the fifth insulating film, and an upper part in the fifth insulating film, A third dummy wiring made of a third conductive material and electrically connected to the dummy via, and the third dummy wiring is formed immediately above the second dummy wiring in plan view, The second dummy wiring is formed immediately above the first dummy wiring, and the first dummy via is viewed in plan view. The second dummy via is formed in the region in which the second dummy wiring is formed, and the second dummy via is formed in the region in which the third dummy wiring is formed in plan view, and the first dummy wiring and the first dummy wiring are formed. The dummy via is electrically insulated by the second insulating film, and the second dummy wiring and the second dummy via are electrically insulated by the fourth insulating film. In addition to improving the mechanical and thermal stress resistance of the dielectric film, it is possible to prevent the life deterioration and destruction of the low dielectric constant film due to charging damage in the process accompanying the miniaturization.

  In this case, since the upper layer dummy via and the lower layer dummy wiring are electrically insulated, the charge-up damage of the process occurring in each layer is completed in the process of forming each layer dummy via and the upper layer dummy wiring. Therefore, even if there is an arrangement in which the distance between the dummy wiring of a certain layer and the wiring is minimized, the damage to that portion is completed only when the layer is formed, and an upper layer higher than that layer is formed as in the conventional case. Not all damage is accumulated.

  According to claim 4, in the semiconductor device according to claim 3, the design value of the first dummy via is 95% or less of the design value of the via in the same layer, and the design value of the second dummy via is in the same layer. It is preferably 95% or less of the design value of the via.

  According to claim 5, in the semiconductor device according to claim 1 or 3, the third insulating film and the fifth insulating film are films containing a low-k material, and the second insulating film and the fourth insulating film are A film containing a SiC-based material is preferable. A film containing a low-k material can be used as the low-melting interlayer insulating film, and a film containing a SiC-based material can be used as an etching stopper.

  6. The semiconductor device according to claim 1, wherein the third insulating film and the fifth insulating film are films containing a SiO-based material, and the second insulating film and the fourth insulating film are SiN. A film containing a system material is preferable.

  According to claim 7, in the semiconductor device according to claim 1 or 3, it is preferable that at least one of the first to fifth insulating films is a multilayer film.

  According to the method of manufacturing a semiconductor device according to claim 8 of the present invention, the first via forming opening is provided in the third insulating film, and the first conductive material is used as the first via forming opening. Embedding and forming a first dummy via that fills the portion and reaches the surface of the second insulating film; forming a fourth insulating film on the third insulating film including the first dummy via; A step of forming a fifth insulating film on the fourth insulating film; a second via forming opening in the fifth insulating film; and a second conductive material as the second via forming opening. 2. The semiconductor device according to claim 1, further comprising a step of filling in the portion and embedding and forming a second dummy via reaching the surface of the fourth insulating film immediately above the first dummy via in plan view. Can be produced, and similar effects can be obtained.

  According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eighth aspect, the step of forming at least one laminated film including a lower insulating film and an upper insulating film as a pair on the fifth insulating film; In the insulating film, when viewed in plan, an upper opening reaching the surface of the lower insulating film is provided immediately above the second dummy via, and a conductive material is filled in the upper opening to form the upper dummy via. And a step of embedding.

  According to the method of manufacturing a semiconductor device of the tenth aspect of the present invention, the second wiring formation opening is provided in the upper portion of the third insulating film, and is provided below the bottom surface of the second wiring formation opening. The first via forming opening is provided, and the second conductive material is filled in the second wiring forming opening and the first via forming opening, and the first dummy is seen in plan view. A step of burying and forming a second dummy wiring and a first dummy via reaching the surface of the second insulating film immediately above the wiring; and a fourth insulating film on the third insulating film including the second dummy wiring. A step of forming an insulating film; a step of forming a fifth insulating film on the fourth insulating film; a third wiring forming opening in the upper portion of the fifth insulating film; A second via forming opening is provided below the bottom surface of the wiring forming opening, and the third conductive material is disposed in the third arrangement. The second opening that fills the formation opening and the second via formation opening and reaches the surface of the third dummy wiring and the fourth insulating film immediately above the second dummy wiring in plan view. The dummy vias are embedded and formed, so that the semiconductor device according to claim 3 can be manufactured and the same effect can be obtained.

  According to claim 11, in the method of manufacturing a semiconductor device according to claim 10, the design value of the size of the first dummy via is 95% or less of the design value of the size of the via in the same layer. The design value of the size is preferably 95% or less of the design value of the size of the via in the same layer.

  The semiconductor device manufacturing method according to claim 12, wherein the third insulating film and the fifth insulating film are films containing a low-k material, and the second insulating film and the fourth insulating film The insulating film is preferably a film containing a SiC-based material. A film containing a low-k material can be used as the low-melting interlayer insulating film, and a film containing a SiC-based material can be used as an etching stopper.

  According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eighth or tenth aspect, the third insulating film and the fifth insulating film are films containing a SiO-based material, and the second insulating film and the fourth insulating film. The film is preferably a film containing a SiN-based material.

  According to a fourteenth aspect of the present invention, in the semiconductor device manufacturing method according to the eighth or tenth aspect, at least one of the first to fifth insulating films is preferably a multilayer film.

(First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2 are cross-sectional views of each step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

  First, as shown in FIG. 1A, a transistor or the like (not shown) is formed on the surface of a P-type semiconductor substrate 1 made of a silicon single crystal whose principal surface is a (100) plane having a specific resistance of 10 to 20 Ω · cm. BPSG film is formed with a thickness of about 1000 nm by the CVD method, and planarized by the CMP method to form the interlayer insulating film 2. Next, although not shown, a laminated film of Ti (15 nm) / TiN (10 nm) / W (100 nm) is formed by CVD, and a tungsten contact plug is formed by planarization by CMP. Next, a first layer Cu wiring groove is formed on the contact plug by dry etching of the resist mask. Next, after forming a TaN (10 nm) / Cu (10 nm) laminated film by sputtering, a Cu film is deposited by about 600 nm by electrolytic plating, and planarized by CMP to form the first layer Cu wiring 3. . Next, a first SiC film 4 of about 50 nm is deposited on the entire surface by CVD.

  Next, as shown in FIG. 1B, a SiLK film is deposited by about 450 nm by a spin coating method, and a SiCN film is deposited by about 50 nm by a CVD method to form a low-k film 5. Next, the first-layer via hole 6 is formed on the first-layer Cu wiring 3 and the first-layer dummy via hole 7 is formed in the Low-k film 5 as the first via formation opening by dry etching of the resist mask. Form. At this time, the first SiC film 4 is used as an etching stopper.

  Next, as shown in FIG. 1C, dry etching is performed using the resist 8 that covers the inside of the first-layer dummy via and the first-layer dummy via and opens the second-layer Cu wiring portion and the first-layer via portion as a mask. After forming the second layer Cu wiring groove 9, the first SiC film 4 at the bottom of the first layer via hole 6 at the bottom of the second layer Cu wiring groove 9 is removed by dry etching to remove the first layer Cu wiring 3. Expose the surface.

  Next, as shown in FIG. 2A, after a TaN (10 nm) / Cu (10 nm) laminated film is formed by sputtering, a Cu film is deposited by about 600 nm by electrolytic plating, and planarized by CMP. After forming the first layer via 10, the first layer dummy via 11, and the second layer Cu wiring 12, a second SiC film 13 of about 50 nm is deposited on the entire surface by CVD.

  Next, as shown in FIG. 2B, by repeating the same process as described above, a SiLK film is deposited by about 450 nm by a spin coating method, and a SiCN film is deposited by about 50 nm by a CVD method. A film 14 is formed. Next, as a second via formation opening by dry etching of the resist mask, a second layer via hole is formed on the second layer Cu wiring 12, and a second layer dummy via hole is formed on the first layer dummy via 11, respectively. Formed in the -k film 14 At this time, the SiC film 13 is used as an etching stopper. Next, after forming a third layer Cu wiring groove by dry etching of the resist mask, the second SiC film 13 at the bottom of the second layer via hole is removed by etching, for example, to expose the surface of the second layer Cu wiring 12. . Next, after a TaN (10 nm) / Cu (10 nm) laminated film is formed by sputtering, a Cu film is deposited by about 600 nm by electrolytic plating, and is planarized by CMP to form second layer via 15 and second layer. Dummy via 16 and third layer Cu wiring 17 are formed. Thereafter, the wiring layer can be increased by repeating the above steps.

  According to this embodiment, by forming dummy vias in the low dielectric constant interlayer insulating film, it is possible to reduce the interface of the low dielectric constant interlayer insulating film, and at the same time, the layers are formed in substantially the same position in different layers. Since the dummy via serves as a pillar, it is possible to prevent the insulating film from peeling and cracking due to mechanical or thermal stress.

  In addition, since the dummy vias in each layer are electrically insulated, the process charge-up damage that occurs in each layer is completed in each layer. Therefore, even if there is an arrangement where the distance between the dummy via and the wiring of a certain layer is minimized, the damage to that portion is completed only when the layer is formed, and an upper layer higher than that layer is formed as in the conventional case. Not all damage is accumulated.

Therefore, it is possible to prevent the life deterioration and destruction of the low dielectric constant film due to the process charge-up damage. Furthermore, since the dummy is only the via, the dummy via can be effectively arranged in a stacked state even where the dummy wiring cannot be placed. As a result, the dummy via functions as a chip pillar and can further improve resistance to mechanical and thermal stress.
(Second Embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to FIGS. 3 and 4 are cross-sectional views of the respective steps of the semiconductor device manufacturing method according to the second embodiment of the present invention.

  First, as shown in FIG. 3A, a transistor or the like (not shown) is formed on the surface of a P-type semiconductor substrate 1 made of a silicon single crystal having a specific surface of (100) having a specific resistance of 10 to 20 Ω · cm. BPSG film is formed with a thickness of about 1000 nm by the CVD method, and planarized by the CMP method to form the interlayer insulating film 2. Next, although not shown, a laminated film of Ti (15 nm) / TiN (10 nm) / W (100 nm) is formed by CVD, and a tungsten contact plug is formed by planarization by CMP. Next, a first-layer Cu wiring groove is formed on the contact plug and a first-layer Cu dummy wiring groove is formed on the contact plug as a first wiring formation opening by dry etching of the resist mask. . Next, after a TaN (10 nm) / Cu (10 nm) laminated film is formed by sputtering, a Cu film is deposited by about 600 nm by electrolytic plating, and is flattened by CMP to form the first layer Cu wiring 3 and the first layer. The layer Cu dummy wiring 21 is formed simultaneously. Next, a first SiC film 4 of about 50 nm is deposited on the entire surface by CVD.

  Next, as shown in FIG. 3B, a SiLK film is deposited by about 450 nm by a spin coating method, and a SiCN film is deposited by about 50 nm by a CVD method to form a low-k film 5. Next, a first layer via hole 6 is formed on the first layer Cu wiring 3 and the first layer via hole 6 is formed above the first layer Cu dummy wiring 21 as a first via formation opening by dry etching of the resist mask. The first-layer dummy via holes 22 having a design value of 80% of the size are formed in the Low-k film 5 respectively. At this time, the first layer via hole 6 is formed by etching up to the surface of the first SiC film 4 using the first SiC film 4 as an etching stopper, while the first layer dummy via hole 22 is different in design value from the first layer via hole 6 described above. The first via hole 6 and the first layer via hole 6 are formed under the etching conditions such that the etching stops in the middle of the low-k film 5.

  Next, as shown in FIG. 3C, after the second layer Cu wiring groove 9 and the second layer Cu dummy wiring groove 23 are formed as the second wiring formation opening by dry etching of the resist mask, the dry etching is performed. The first SiC film 4 at the bottom of the first layer via hole at the bottom of the second layer Cu wiring groove 9 is removed by etching to expose the surface of the first layer Cu wiring 3. At this time, the difference in residual film in the hole when the first SiC film 4 at the bottom of the first layer dummy via hole at the bottom of the second layer Cu dummy wiring groove 23 forms the first layer via hole 6 and the first layer dummy via hole 22. Therefore, a condition where etching is not removed is used.

  Next, as shown in FIG. 4A, after a TaN (10 nm) / Cu (10 nm) laminated film is formed by sputtering, a Cu film is deposited by about 600 nm by electrolytic plating, and planarized by CMP. After forming the first layer via 10, the second layer Cu wiring 12, the first layer dummy via 24, and the second layer Cu dummy wiring 25, a second SiC film 13 of about 50 nm is deposited on the entire surface by CVD. At this time, the second layer Cu wiring 12 and the first layer Cu wiring 3 are electrically connected by the first layer via 10, but the second layer Cu dummy wiring 25 and the first layer Cu dummy wiring 21 are Since there is the 1 SiC film 4, it is not electrically connected.

  Next, as shown in FIG. 4B, by repeating the same process as described above, a SiLK film is deposited by about 450 nm by the spin coating method, and a SiCN film is deposited by about 50 nm by the CVD method. A film 14 is formed. Next, the second layer via hole is formed on the second layer Cu wiring and the second layer dummy via hole is formed above the second layer Cu dummy wiring as a second via forming opening by dry etching of the resist mask. It is formed in the low-k film 14. At this time, the second SiC film 13 is used as an etching stopper, the second layer via hole is formed up to the surface of the second SiC film 13, and the second layer dummy via hole is formed to stop in the middle of the Low-k film 14. To do. Next, after forming a third layer Cu wiring groove and a third layer Cu dummy wiring groove as a third wiring formation opening by dry etching of the resist mask, the second SiC film 13 at the bottom of the second layer via hole is formed by dry etching. Is removed by etching to expose the surface of the second layer Cu wiring 12 and at the same time the SiC film 13 at the bottom of the second layer dummy via hole remains, and the surface of the second layer Cu dummy wiring 25 is not exposed. Next, after a TaN (10 nm) / Cu (10 nm) laminated film is formed by sputtering, a Cu film is deposited by about 600 nm by electrolytic plating, and is planarized by CMP to form second layer via 15 and third layer. A Cu wiring 17, a second layer dummy via 26, and a third layer Cu dummy wiring 27 are formed. Thereafter, the wiring layer can be increased by repeating the above steps.

  According to the present embodiment, it is possible to reduce the interface of the low dielectric constant interlayer insulating film by forming the dummy wiring and the dummy via in the low dielectric constant interlayer insulating film, and at the same time, in the same layer in different layers. Since the dummy wirings and dummy vias formed in this manner serve as pillars, it is possible to prevent peeling and cracking of the insulating film due to mechanical or thermal stress.

Further, since the upper dummy via and the lower Cu dummy wiring are electrically insulated, the charge-up damage of the process occurring in each layer is completed in the process of forming each layer dummy via and the upper Cu dummy wiring. Therefore, even if there is an arrangement where the distance between the Cu dummy wiring and the wiring of a certain layer is minimized, the damage to that part is completed only when the layer is formed, and an upper layer higher than that layer is formed as before. If you do, all damage will not be accumulated.
In addition, the lower layer dummy via connected to the layer is usually arranged inside the Cu dummy wiring (inside the Cu dummy wiring area in plan view), so that the distance from the actual wiring is widened and the influence of damage is also caused. Few.

  Therefore, it is possible to prevent the life deterioration and destruction of the low dielectric constant film due to the process charge-up damage. Furthermore, since the dummy can be arranged in a stacked manner of Cu dummy wirings and dummy vias, sufficient resistance to mechanical and thermal stress can be ensured as in the conventional case.

  The insulating films 2, 4, 5, 13 and 14 are first to fifth insulating films, respectively, the third and fifth insulating films 5 and 14 are films containing a SiO-based material, and the second and fourth insulating films. The films 4 and 13 may be films containing a SiN-based material. In addition, at least one of the first to fifth insulating films may be a multilayer film.

  A semiconductor device and a manufacturing method thereof according to the present invention provide a structure and a manufacturing method in which a low dielectric constant film is not damaged by charge-up by a wiring formation process, and mechanical and thermal stresses of the low dielectric constant film are provided. This is useful as a method for improving the charging damage resistance of the process while improving the resistance.

It is sectional drawing of each process of the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. It is sectional drawing of each process of the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. It is sectional drawing of each process of the manufacturing method of the semiconductor device of the 2nd Embodiment of this invention. It is sectional drawing of each process of the manufacturing method of the semiconductor device of the 2nd Embodiment of this invention. It is sectional drawing of each process of the manufacturing method of the semiconductor device of a prior art example. It is sectional drawing of each process of the manufacturing method of the semiconductor device of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2 Interlayer insulating film 3 1st layer Cu wiring 4 1st SiC insulating film 5 Low-k insulating film 6 1st layer via hole 7 1st layer dummy via hole 8 Resist 9 2nd layer Cu wiring groove 10 1st layer Via 11 First layer dummy via 12 Second layer Cu wiring 13 Second SiC insulating film 14 Low-k insulating film 15 Second layer via 16 Second layer dummy via 17 Third layer Cu wiring 21 First layer Cu dummy wiring 22 First layer Dummy via hole 23 Second layer Cu dummy wiring groove 24 First layer dummy via 25 Second layer Cu dummy wiring 26 Second layer dummy via 27 Third layer Cu dummy wiring 28 Third SiC insulating film 31 Contact 32 First layer dummy via hole 33 First Layer dummy via 34 Second layer dummy via 35 Charging damage

Claims (14)

First to fifth insulating films sequentially formed on the substrate from below;
A first dummy via made of a first conductive material provided in the third insulating film;
A second dummy via made of a second conductive material provided in the fifth insulating film;
In plan view, the second dummy via is formed immediately above the first dummy via,
The semiconductor device according to claim 1, wherein the first dummy via and the second dummy via are electrically insulated by the fourth insulating film. On the fifth insulating film, at least one layered film including a pair of a lower insulating film and an upper insulating film is provided,
In the upper insulating film, an upper dummy via made of a conductive material is provided,
In plan view, the upper dummy via is formed immediately above the second dummy via,
The semiconductor device according to claim 1, wherein the upper dummy via and the second dummy via disposed below the upper dummy via are electrically insulated by the lower insulating film. First to fifth insulating films sequentially formed on the substrate from below;
A first dummy wiring made of a first conductive material provided in an upper portion of the first insulating film;
A first dummy via made of a second conductive material provided in a lower portion in the third insulating film;
A second dummy wiring made of the second conductive material provided on the third insulating film and electrically connected to the first dummy via;
A second dummy via made of a third conductive material provided in a lower portion of the fifth insulating film;
A third dummy wiring made of the third conductive material provided on the fifth insulating film and electrically connected to the second dummy via;
In plan view, the third dummy wiring is formed directly above and above the second dummy wiring, and the second dummy wiring is formed directly above and above the first dummy wiring,
The first dummy via is formed in a region where the second dummy wiring is formed in plan view,
The second dummy via is formed in a region where the third dummy wiring is formed in plan view,
The first dummy wiring and the first dummy via are electrically insulated by the second insulating film,
The semiconductor device, wherein the second dummy wiring and the second dummy via are electrically insulated by the fourth insulating film. The design value of the first dummy via is 95% or less of the design value of the via in the same layer,
4. The semiconductor device according to claim 3, wherein a design value of the second dummy via is 95% or less of a design value of a via in the same layer. The third insulating film and the fifth insulating film are films containing a low-k material,
4. The semiconductor device according to claim 1, wherein the second insulating film and the fourth insulating film are films containing a SiC-based material. The third insulating film and the fifth insulating film are films containing a SiO-based material,
4. The semiconductor device according to claim 1, wherein the second insulating film and the fourth insulating film are films containing a SiN-based material.   4. The semiconductor device according to claim 1, wherein at least one of the first to fifth insulating films is a multilayer film. Forming first, second and third insulating films on the substrate in order from below;
A first via forming opening is provided in the third insulating film, and a first conductive material is filled in the first via forming opening to reach the surface of the second insulating film. A step of burying and forming one dummy via;
Forming a fourth insulating film on the third insulating film including the first dummy via; and
Forming a fifth insulating film on the fourth insulating film;
A second via formation opening is provided in the fifth insulating film, a second conductive material is filled in the second via formation opening, and the first via is viewed in plan view. And a step of embedding and forming a second dummy via reaching the surface of the fourth insulating film directly above the dummy via. Forming at least one layered film of a lower insulating film and an upper insulating film on the fifth insulating film;
In the upper insulating film, an upper opening reaching the surface of the lower insulating film is provided immediately above the second dummy via in a plan view, and a conductive material is filled in the upper opening. The method of manufacturing a semiconductor device according to claim 8, further comprising: embedding and forming an upper dummy via. Forming a first insulating film on the substrate;
A first wiring forming opening is provided above the first insulating film, and a first conductive material is filled in the first wiring forming opening to embed a first dummy wiring. And a process of
Forming a second insulating film on the first insulating film including the first dummy wiring;
Forming a third insulating film on the second insulating film;
A second wiring forming opening is provided in the upper portion of the third insulating film, and a first via forming opening is provided below the bottom surface of the second wiring forming opening, thereby providing a second conductive layer. The filling material is filled in the second wiring formation opening and the first via formation opening, and the second dummy wiring and the first dummy wiring are directly above the first dummy wiring in a plan view. Embedding and forming first dummy vias reaching the surface of the second insulating film,
Forming a fourth insulating film on the third insulating film including the second dummy wiring; and
Forming a fifth insulating film on the fourth insulating film;
A third wiring formation opening is provided in the upper portion of the fifth insulating film, and a second via formation opening is provided below the bottom surface of the third wiring formation opening to provide a third conductive layer. Filling the third wiring formation opening and the second via formation opening with a conductive material, and in plan view, directly above the second dummy wiring, the third dummy wiring and And a step of embedding and forming second dummy vias reaching the surface of the fourth insulating film. The design value of the size of the first dummy via is 95% or less of the design value of the size of the via in the same layer,
11. The method of manufacturing a semiconductor device according to claim 10, wherein a design value of the size of the second dummy via is 95% or less of a design value of the size of the via in the same layer. The third insulating film and the fifth insulating film are films containing a low-k material,
11. The method of manufacturing a semiconductor device according to claim 8, wherein the second insulating film and the fourth insulating film are films containing a SiC-based material. The third insulating film and the fifth insulating film are films containing a SiO-based material,
11. The method of manufacturing a semiconductor device according to claim 8, wherein the second insulating film and the fourth insulating film are films containing a SiN-based material.   11. The method of manufacturing a semiconductor device according to claim 8, wherein at least one of the first to fifth insulating films is a multilayer film.

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