JP2008140973A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable semiconductor integrated circuit, where damage or stress to a power transistor is reduced by clarifying the route of current flowing to the power transistor and by optimizing current flowing to the power transistor. <P>SOLUTION: The semiconductor integrated circuit has: the power transistor 100A; a plurality of first buses 140-142 formed immediately above the power transistor 100A; a plurality of second buses 150-152; and a contact pad 304 provided in each of the plurality of first and second buses 140-142, 150-152. The plurality of first and second buses 140-142, 150-152 are formed so that the area becomes smaller successively from the buses positioned at a side near an external connection member 307 to those positioned at a distance. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a manufacturing method thereof, and in particular, POE (Pad on Element) technology, that is, technology of providing a pad directly on a semiconductor device, and wire bonding is performed immediately above an active circuit region. The present invention relates to a power integrated circuit having a structure capable of satisfying the requirements and a manufacturing method thereof.

  In recent years, with the spread of information technology, demands for higher speed and lower power consumption are increasing as the capabilities of electronic devices such as computers, information storage devices, mobile phones, and mobile cameras.

  Those that greatly affect the performance of these electronic devices include core semiconductor electronic components such as power supplies, motor drivers, and audio amplifiers. Power devices are considered to have a large influence on the performance of these semiconductor electronic components. There is a power integrated circuit with built-in. For this reason, as the performance of the semiconductor elements constituting the power integrated circuit, there is an increasing demand for further higher speed and lower power consumption.

  By the way, as a general market demand, in addition to the above-mentioned high speed and low power consumption, a great improvement in power device and circuit characteristics is desired, and wires and solder directly above the active circuit area are desired. There is a great demand for low cost and reliable structures and methods due to the formation of ball bonds, and various proposals have been made.

  Here, first, the POE technique, that is, the conventional technique before the introduction of a technique for providing a pad directly on a semiconductor device will be briefly described.

  A connecting member between the pad and the external lead frame is a bonding wire. Materials used for bonding wires include pure or alloyed gold, copper, and aluminum. When gold is used as the material, the diameter of commonly used bonding wire is in the range of about 20-50 μm, and in wire ball bonding, the ball is usually attached to the chip. Therefore, during the bonding operation, when the ball is crushed into a typical nail head shape by the bonding capillary, the pad area must be large enough to secure the ball. Since the diameter of the ball in the free state is typically about 1.2 to 1.6 times the wire diameter, the contact pad shape can vary from about 50 × 50 μm to 150 ×, depending on the process parameters. It must be a square in the range of 150 μm. If the connecting member is a solder ball, the ball diameter is typically in the range of about 0.2 to 0.5 mm, and the contact pad area is in the range of about 0.3 to 0.7 mm. Must be square. Here, the expression “solder ball” does not necessarily mean that the solder contact is spherical, but it has various shapes such as a hemisphere, a half dome, a cut cone, or a general bump. There may be. The exact shape depends on the deposition technique, reflow technique, and material composition.

  Also, the contact pads are typically arranged in an essentially linear array around the periphery of the chip, and large area “silicon assets” (the chip is predominantly on a substrate made of silicon semiconductor material). To be made). Modern semiconductor integrated circuits require a large number of contact pads, often reaching hundreds of ground and power connections alone. In addition, the inclusion of signal connections requires more than 1000 contact pads and sacrifices a lot of valuable silicon assets.

  Also, the wire bonding process has been shown over several years of experience to exert significant stress on the underlying layers of metals and dielectrics. This is due to the impact of the bonding capillary (to crush the gold ball to form the nail head contact), the frequency and energy of the ultrasonic vibration of the bonding capillary and the gold ball (oxidation of the exposed metal layer surface). Time and temperature of the process (to initiate the formation of the gold / aluminum intermetallic compound). To avoid the risk of cracking or craters in the layers under the bonding pad due to stresses during the wire bonding process or due to multi-probe testing and post-assembly device operation Over the last few years, design rules have been established for the layout of semiconductor integrated circuits that prohibit the placement of circuit structures in the region and avoid the use of fragile and mechanically weak dielectric materials. For this reason, many silicon assets are required only by providing bonding pads.

  Against this background, along with the need for significant improvements in power device and circuit characteristics and the formation of wire and solder ball bonds directly above the active circuit area and a low cost and reliable structure and method. As described above, there is an increasing demand for higher speed and lower power consumption of semiconductor integrated circuits.

[High-speed semiconductor integrated circuits]
First, what hinders the speeding up of the semiconductor integrated circuit is the delay of the MOS transistor itself and the wiring delay due to the wiring above it. Conventionally, the delay of the MOS transistor itself has been reduced by a miniaturization technique for shortening the gate length. However, as the delay of the MOS transistor itself becomes smaller, the problem of wiring delay becomes more prominent.

  Therefore, in order to reduce the delay between wirings, an insulating film (low dielectric constant film) having a low dielectric constant is being adopted as the insulating film sandwiched between the wirings. However, a low dielectric constant film that achieves a dielectric constant of 3.0 or less has a mechanical strength that is significantly lower than that of a silicon oxide film that has been used in the past. Therefore, the diffusion process that forms the circuit of a semiconductor integrated circuit is completed. After that, there is a problem in the assembly process for packaging the semiconductor integrated circuit, particularly in the wire bonding process.

  Specifically, since the mechanical strength of the interlayer insulating film is not sufficient, when wire bonding is performed on a pad mounted on a semiconductor integrated circuit, the impact load of the wire bond is transmitted to the interlayer insulating film immediately below the pad through the pad. The interlayer insulating film is greatly deformed. As a result, a crack is generated in the interlayer insulating film, causing a reliability defect due to peeling of the pad or peeling of the interlayer insulating film. In recent years, as described above, a semiconductor element in which a pad is provided on a transistor constituting an active circuit region has been developed for the purpose of reducing the cost by reducing the size of the semiconductor element. In this case, if a low dielectric constant film with low mechanical strength is used between the wirings and the interlayer insulating film, the low dielectric constant film is deformed by the impact of wire bonding, and the impact is easily transmitted to the transistor, thereby damaging the transistor. Giving poor quality.

  On the other hand, in Patent Document 1, a metal layer is formed directly below a pad with an interlayer insulating film interposed therebetween, and the metal layer and the pad are connected by a via so that an impact applied to the interlayer insulating film by a wire bond is applied. The metal layer receives the metal layer and, further, the via supports the metal layer attempting to deform in the direction in which the shock is applied. As described above, Patent Document 1 has a pad structure that compensates for a decrease in mechanical strength of an interlayer insulating film formed immediately below the pad, thereby suppressing damage to the transistor due to wire bonding.

  By the way, when copper is used as a metal material, a copper wiring is formed by a damascene process, but chemical mechanical polishing (CMP) is performed for planarizing the plated copper after electrolytic plating of copper. ), The copper pattern having a soft property is dished such that when the area thereof is increased, the central portion is shaved and the film thickness becomes very thin. Furthermore, in order to form a fine via pattern in the lower layer, if the area of the copper pattern is increased by reducing the film thickness of the metal layer, there is a portion where copper is completely scraped by CMP. Arise.

  In this regard, in Patent Document 1 described above, the above phenomenon occurs when the second metal layer, that is, copper is formed. As described above, when the central portion of the copper pattern becomes thin or a portion where the copper is completely scraped out, the impact of the wire bond received by the interlayer insulating film is increased and the possibility of occurrence of cracks is increased.

  On the other hand, Patent Document 2 provides a pad structure that can prevent damage due to wire bonding to an insulating film and a transistor directly under the pad. In other words, the semiconductor device of Patent Document 2 includes a first electrode made of a conductive layer, an external connection electrode made of a conductive layer formed on the first electrode, and a first electrode below the first electrode. And at least one second electrode connected through a through-hole, and a plurality of convex shapes on the periphery of the second electrode.

  In this way, by adopting a structure in which a metal layer (hereinafter referred to as a lower layer metal) sandwiched between the uppermost layer metal and an interlayer insulating film is connected by a via, a wire bond impacts between the wirings immediately below the pads and between the layers. The deformation or crack of the low dielectric constant film employed in the insulating film can be prevented. That is, since the uppermost metal is supported by the lower layer metal with respect to the impact of the wire bond, it does not deform even when it receives the impact of the wire bond. As a result, it is possible to suppress the impact of wire bonds transmitted to the low dielectric constant film, which is an interlayer insulating film immediately below the pad, and to prevent the deformation of the low dielectric constant film and the occurrence of cracks.

  In addition, in order to prevent CMP dishing due to an increase in the area of the lower layer metal, a large number of convex shapes are provided in the peripheral portion of the lower layer metal, so that the surface area of the lower layer metal is expanded and adhesion to the interlayer film is increased. As a result, damage to the transistor due to the impact of the wire bond can be reduced, and cracks can be prevented from occurring in the interlayer insulating film.

  As described above, according to the pad structure adopted in Patent Document 2, damage to the insulating film and the transistor directly under the pad due to the wire bond is prevented, which contributes to speeding up of the semiconductor integrated circuit.

[Low power consumption of semiconductor integrated circuits]
Next, the obstacle to reducing the power consumption of semiconductor integrated circuits is to make the chip area as small as possible while effectively utilizing the chip area of semiconductor products by utilizing the miniaturized MOS process. To realize a built-in power integrated circuit. In such a power integrated circuit, a pulse width modulation (PWM) driving technique is usually used when driving a power device for the purpose of reducing power consumption. In this PWM drive, reducing the ON resistance of the power device is an important process technology that leads to lower power consumption.

  Patent Document 3 proposes a conventional related technique for making the ON resistance of a power device as small as possible by utilizing the POE technique. That is, a power integrated circuit in which wire bonding can be performed immediately above the active circuit region portion, and in this power integrated circuit, a plurality of contacts are directly above the bus connected to the electrode of the power transistor by utilizing POE technology. Pads are arranged and a plurality of contact pads and lead frames are connected by bonding wires. As a result, the resistance value and the current path from the connecting member to the electrode are minimized, so that the electrical characteristics of the power transistor can be improved.

  FIG. 14 shows an electric circuit diagram together with a simplified plan view of a part of the semiconductor integrated circuit described in Patent Document 3.

  As shown in the plan view of FIG. 14, an active region 2 of a power transistor is formed in the IC chip 1, and the active region 2 is made of a sheet metal and all source electrodes are formed. Are formed, and a second bus 4 connected to all the drain electrodes is formed. Three contact pads 5 are provided on each of the first bus 3 and the second bus 4, and are commonly connected to the respective buses. The three contact pads 5 on the first bus 3 are arranged so as to be bilaterally symmetrical with the three contact pads 5 on the second bus 3. Bonding wires 6 are provided to connect each contact pad 5 to an external lead frame 7.

  The electrical circuit diagram shown in FIG. 14 schematically shows electrical characteristics related to the power transistor operation brought about by arranging the connection member to the lead frame 7 on the power transistor. Note that the source / drain resistance Rs of the transistor itself, spreading resistances on the bus (bus resistance) Rn10, Rn20, Rn30, and various wire resistances Rb10, Rb20, Rb30 are shown in the electric circuit diagram.

As shown in FIG. 14, the electric circuit viewed from the lead frame 7 includes bus resistances Rn10, Rn20 in series with the wire resistances Rb10, Rb20, Rb30 of the three bonding wires 6 connected in parallel to the leadframe 7, respectively. , Rn30 are connected, and further, a resistance circuit is connected to the source-drain resistance Rs of the transistor itself. Thus, each of the bus resistors Rn (10-30) is connected in series with the various wire resistors Rb (10-30), and as a result, the bus resistors Rn (10-30) and the wire resistors Rb ( 10-30) are connected in parallel with each other, and the overall resistance composed of the source-drain resistance Rs, the bus resistance Rn (10-30), and the wire Rb (10-30) is reduced. That is, the voltage drop associated with the source-drain resistance Rs, the bus resistance Rn (10-30), and the wire resistance Rb (10-30) and the corresponding debiasing effect are reduced, so that the transistor characteristics are improved. .
Japanese Patent No. 2974022 Japanese Patent No. 3725527 US20020011674A1

  However, as shown in Patent Document 3, in a power integrated circuit in which wire bonding can be performed immediately above an active circuit region portion, a power transistor is used for the purpose of minimizing a resistance value and a current path from a connection member to an electrode. A plurality of contact pads are distributed and arranged so as to be located immediately above the power transistor on each of the bus connected to the source electrode and the bus connected to the drain electrode.

  For this reason, when a large current flows through the power transistor, the bus connected to the electrode of the power transistor is commonly connected to each of the plurality of contact pads. Depending on the type of the NPN transistor or the like, depending on the layout of the bus connected to the electrode, there is a problem that current concentration occurs in the power transistor and damages it, thereby impairing the reliability of the semiconductor integrated circuit.

  In view of the above, an object of the present invention is to clarify the route of the current flowing through the power transistor and to optimize the current flowing through the power transistor, thereby reducing damage or stress on the power transistor and It is to provide a semiconductor integrated circuit excellent in performance and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor integrated circuit according to one aspect of the present invention includes a power transistor formed on a semiconductor substrate, an interlayer insulating film formed on the power transistor, and an interlayer insulating film. A first metal layer formed directly above the power transistor, comprising a plurality of first metal patterns functioning as first electrodes of the power transistor, and a first metal layer, A plurality of second metal patterns functioning as second electrodes of the transistor, and a second metal layer formed in the interlayer insulating film and immediately above the first metal layer, A plurality of first buses electrically connected to a corresponding first metal pattern among the first metal patterns, and a second metal layer, and corresponding second of the plurality of second metal patterns. With metal pattern A plurality of second buses connected to each other; and a plurality of first buses and contact pads provided for each of the plurality of second buses, each of the plurality of first buses. And each of the plurality of second buses is formed so that the area decreases in order from one located closer to the external connection member to one farther away.

  According to the semiconductor integrated circuit of one aspect of the present invention, the current path of the power transistor is divided by providing one contact pad for each of the plurality of first buses and the plurality of second buses. Therefore, while avoiding damage or stress due to current concentration on the power transistor, the current route flowing to each power transistor can be clarified, and the current flowing to each power transistor can be optimized, so that The allowable current value of the transistor can be improved. Further, each of the plurality of first buses and each of the plurality of second buses are configured so that the area decreases in order from the one located closer to the external connection member to the one located farther. Thus, the resistance component due to the length of the bonding wire can be taken into consideration, and the area size of the divided buses can be adjusted by utilizing the design for the bus size. For this reason, the resistance component of each bonding wire viewed from the lead frame and the combined resistance value of the element resistance and bus resistance component of each power transistor are combined so that the current density is uniform for each power transistor. The wire length, the size design of each power transistor and the bus design can be realized, and the power generation amount per unit area of each power transistor element itself can be made uniform. As a result, a semiconductor integrated circuit with excellent reliability can be realized.

  In the semiconductor integrated circuit according to one aspect of the present invention, the external connection member preferably includes at least a lead frame.

  In this way, by using an external connection member as a lead frame, the cost of new capital investment can be avoided by using only the designs and processes that are commonly used and accepted in the manufacture of IC devices. A manufacturing equipment base can be used.

  In the semiconductor integrated circuit according to one aspect of the present invention, the power transistor is preferably divided into a plurality of parts by a separation layer so as to correspond to each of the plurality of buses and each of the plurality of second buses. .

  As described above, since the power transistors having one contact pad distributed on each of the buses are surrounded by the isolation, the latch and parasitic malfunctions are less likely to occur, and the reliability can be improved. Can play.

  In the semiconductor integrated circuit according to one aspect of the present invention, the size of the power transistor is preferably larger than the size of each contact pad in plan view.

  As described above, the semiconductor integrated circuit supplies the power transistors arranged in the lateral direction, the arrangement of the power supply contact pads distributed over the transistors, and the distributed vertical current from the contact pads to the transistors. By placing a power supply contact pad directly over the power transistor, valuable silicon assets are further saved. That is, by reducing the silicon area consumed in the entire circuit design, the cost of the IC chip can be reduced. In other words, the chip area of the IC can be reduced, and the cost of the IC can be reduced.

  In the semiconductor integrated circuit according to one aspect of the present invention, each of the contact pads is preferably included in a region where the power transistor is formed in plan view.

  By doing this, it is possible to achieve substantially the same effect as the effect of reducing the chip area.

  In the semiconductor integrated circuit according to one aspect of the present invention, it is preferable that each of the contact pads protrudes partially from the region where the power transistor is formed in plan view.

  In this way, although slightly inferior to the above effect, it is possible to achieve substantially the same effect as the effect of reducing the chip area.

  In the semiconductor integrated circuit according to one aspect of the present invention, it is preferable that all of the contact pads protrude from the region where the power transistor is formed in a plan view.

  In this way, although slightly inferior to the above effect, it is possible to achieve substantially the same effect as the effect of reducing the chip area.

  In the semiconductor integrated circuit according to one aspect of the present invention, the power transistor is preferably a DMOS transistor.

  In this way, since the ON resistance can be reduced, it is possible to achieve the effect of speeding up and reducing power consumption.

  In the semiconductor integrated circuit according to one aspect of the present invention, the power transistor is preferably a CMOS transistor.

  In this way, since the ON resistance can be reduced, it is possible to achieve the effect of speeding up and reducing power consumption.

  In the semiconductor integrated circuit according to one aspect of the present invention, the power transistor is preferably a bipolar transistor.

  This makes it difficult for latch or parasitic malfunctions to occur and improves reliability.

  In the semiconductor integrated circuit according to one aspect of the present invention, the semiconductor substrate is preferably an SOI substrate.

  In this way, complete insulation isolation is realized, latch or parasitic malfunction is less likely to occur, and reliability is improved.

  In the semiconductor integrated circuit according to one aspect of the present invention, the semiconductor substrate is preferably an epitaxial substrate.

  This improves the current capability of the power transistor.

  In the semiconductor integrated circuit according to one aspect of the present invention, the thickness of each contact pad is preferably at least twice the thickness of each of the plurality of first buses and the plurality of second buses.

  In this way, cracks can be reduced by increasing the speed and power consumption by reducing the ON resistance of the power transistor and absorbing the stress during wire bonding.

  In the semiconductor integrated circuit according to one aspect of the present invention, the contact pad and the first bus or the second bus are preferably connected through a single via.

  In this way, since the ON resistance of the power transistor can be reduced, high speed and low power consumption can be realized.

  In the semiconductor integrated circuit according to one aspect of the present invention, the diameter of the single via is preferably 50 μm or more.

  In this way, by providing a minimum value restriction on the diameter of a single via, the allowable value of the load current flowing through the single via can be clarified, and reliability can be ensured.

  In the semiconductor integrated circuit according to one aspect of the present invention, the connection between the contact pad and the first bus or the second bus is preferably performed via a plurality of via arrays.

  Thus, by forming the contact pad openings as a plurality of via arrays, the stress during wire bonding can be absorbed and cracks can be reduced.

  According to the semiconductor integrated circuit of one aspect of the present invention, the current path of the power transistor is divided by providing one contact pad for each of the plurality of first buses and the plurality of second buses. Therefore, while avoiding damage or stress due to current concentration on the power transistor, the current route flowing to each power transistor can be clarified, and the current flowing to each power transistor can be optimized, so that The allowable current value of the transistor can be improved. Further, each of the plurality of first buses and each of the plurality of second buses are configured so that the area decreases in order from the one located closer to the external connection member to the one located farther. Thus, the resistance component due to the length of the bonding wire can be taken into consideration, and the area size of the divided buses can be adjusted by utilizing the design for the bus size. For this reason, the resistance component of each bonding wire viewed from the lead frame and the combined resistance value of the element resistance and bus resistance component of each power transistor are combined so that the current density is uniform for each power transistor. The wire length, the size design of each power transistor and the bus design can be realized, and the power generation amount per unit area of each power transistor element itself can be made uniform. As a result, a semiconductor integrated circuit with excellent reliability can be realized.

  Hereinafter, specific embodiments of a power integrated circuit and method in which bonding and current distribution are distributed according to the present invention will be described with reference to the drawings.

(First embodiment)
A semiconductor integrated circuit and a manufacturing method thereof according to a first embodiment of the present invention will be described below with reference to the drawings.

  FIG. 1 shows an electric circuit diagram together with a simplified plan view of a part of the semiconductor integrated circuit according to the first embodiment of the present invention.

  As shown in the plan view of FIG. 1, an active region 100 </ b> A of a power transistor is formed in the IC chip 100. Relatively wide buses 140 to 142 and 150 to 152 are formed on the active region 100A so as to cover the source and drain regions of the power transistor. As a result, the integration density of the IC can be improved and the chip can be saved. The three buses 140 to 142 are the uppermost metal layer (third metal layer) made of sheet-like metal, and each of them is connected to the source electrode and is divided by an insulating layer. . Further, the three buses 150 to 152 are the uppermost metal layer (third metal layer) made of sheet metal, and are positioned so as to be symmetrical with the three buses 140, 141, 142, Each of them is connected to the drain electrode and is divided by an insulating layer. One contact pad 304 is formed on each of the buses 140 to 142 and 150 to 152, and each contact pad 304 and an external lead frame 307 (power source) are connected to each other. Bonding wires 306 are provided.

  Further, as shown in the plan view of FIG. 1, the areas of the buses 140 to 142 and 150 to 152 are different from each other. Similarly, the buses 150 to 152 are formed so that the areas of the buses 150 to 152 become smaller as the distance from the side closer to the lead frame 307 increases.

  Here, the semiconductor integrated circuit according to the present embodiment having the structure shown in FIG. 1 has the electrical characteristics shown in the electrical circuit diagram in the lower part of FIG.

  That is, the electrical circuit diagram shown in the lower part of FIG. 1 schematically shows electrical characteristics related to the power transistor operation brought about by arranging the connection member to the lead frame 307 on the power transistor. In this electrical circuit, the source-drain resistances of the three transistors themselves are Rs1, Rs2, and Rs3, and the spreading resistances on the six buses 140 to 142 and 150 to 152 are resistances to the current flowing through each bus. Since the three buses 140 to 142 are symmetrical with the three buses 150 to 152, the three symmetrical bus resistances are Rn1, Rn2, and Rn3, and various wire resistances that are also symmetrical with each other are Rb1, Rb2, Shown as Rb3.

  As shown in FIG. 1, the electric circuit viewed from the lead frame 307 includes bus resistances Rn1, Rn2 in series with wire resistances Rb1, Rb2, Rb3 of three bonding wires 306 connected in parallel to the lead frame 307, respectively. , Rn3 are connected to each other, and further, three parallel resistance circuits that are symmetrical to each other are connected to the source-drain resistances Rs1, Rs2, and Rs3 of the transistor itself.

  As is apparent from a comparison between the electric circuit shown in FIG. 1 and the electric circuit shown in FIG. 14 described in the conventional example, in the conventional example, a plurality of contact pads are commonly connected to the bus of the uppermost metal layer. Thus, the power transistor itself has one current path. However, in this embodiment, the plurality of buses have different surface areas, that is, the buses 140 to 142 and 150 to 152 are Each area is formed so as to become smaller as the distance from the side closer to the lead frame 307 increases. Therefore, taking into account the resistance component due to the length of the bonding wire, it is possible to adjust the area size of the divided bus utilizing the design of the bus size, the first electrode side of the power transistor itself is divided, Since the current path of the power transistor itself is also divided, the current route flowing through each power transistor itself can be clarified and the current density flowing through each power transistor element itself can be optimized.

  The semiconductor integrated circuit shown in FIG. 1 can be used when the allowable current value of each bonding wire 307 is larger than the large current flowing through the actual power transistor. The combined resistance value of the resistance component of each power transistor and the element resistance of each power transistor and the bus resistance component, the wire length of the bonding wire and the size design of each power transistor so that the current density is uniform for each power transistor A bus design can be realized, and the load of each power transistor element itself can be made uniform.

  Further, a large bus area is divided into appropriate sizes, and a first bus group (for example, bus 140) including a plurality of buses (for example, buses 140 to 142 and 150 to 152) for connecting the first and second electrodes. 142) and the second bus group (for example, 150 to 152), by arranging one contact pad 304 that forms a current path for each bus, the current path that flows is divided and unexpected current concentration occurs. Damage to the power transistor can be prevented, the amount of heat generated per unit area of the power transistor element itself can be made uniform, and the power transistor element can be prevented from being destroyed by local heat generation.

For example, when the resistance value per unit length of the bonding wire is 50 mΩ / mm, the wire length of each bonding wire 306 is designed as 1 mm, 1.5 mm, and 2 mm, and depends on the wire length of each bonding wire 306. Three wire resistors are designed as Rb1 = 0.05Ω, Rb2 = 0.075Ω, Rb3 = 0.1Ω, and three bus resistors (spread resistors) Rn1 = 0.09Ω, Rn2 = 0.1Ω, Rn3 = 0 .11Ω and the source-drain resistance of the transistor itself is designed as Rs1 = 0.1Ω, Rs2 = 0.13Ω, and Rs3 = 0.16Ω, the resistance component of each bonding wire 306 and the power transistor Each series resistance value of the element resistance and the bus resistance component is as shown in the following formula.
Rb1 × 2 + Rn1 × 2 + Rs1 = 0.38Ω
Rb2 × 2 + Rn2 × 2 + Rs2 = 0.48Ω
Rb3 × 2 + Rn3 × 2 + Rs3 = 0.58Ω
Therefore, assuming that the current flowing through each power transistor element is I1, I2, and I3, the loss voltage due to the resistance component of each bonding wire 306, the element resistance of each power transistor, and the series resistance value of the bus resistance component is as follows: The following equation holds.
(Rb1 × 2 + Rn1 × 2 + Rs1) × I1
= (Rb2 × 2 + Rn2 × 2 + Rs2) × I2
= (Rb3 × 2 + Rn3 × 2 + Rs3) × I3
The ratio of the currents I1, I2, and I3 flowing through each power transistor element is a value roughly proportional to each power transistor area ratio (size ratio), and is as shown in the following relational expression.
I1: I2: I3 = 1.526: 1.208: 1
The resistance of the power transistor between the two terminals of the lead frame 307 is 0.155Ω.

  As described above, since each bus is divided for each contact pad 304, the resistance component due to the length of the bonding wire is taken into consideration and utilized for bus size design to reduce the area size of the divided bus. Can be adjusted. For this reason, by adjusting the current path for each power transistor so that current can flow according to the size of each power transistor, the current density flowing through each divided power transistor itself flows almost uniformly. In addition, the current flowing through each power transistor flows according to the size of each power transistor element itself without concentrating the current even at a large current. Therefore, the load on the power transistor element itself, bonding wires, metal layer buses and vias is evenly distributed, and the amount of heat generated per unit area of the power transistor element itself can be made uniform. The destruction of the power transistor element due to heat generation is prevented, and the current allowable value of the power transistor element as a whole is improved. As a result, the reliability improvement of the semiconductor integrated circuit is improved.

  Further, in FIG. 1, a description has been given of a double configuration in which three buses are arranged symmetrically and six buses are provided. The same effect can be obtained even when it is not symmetrically divided in a substantially vertical or oblique manner.

For example, the wire resistance Rb1 due to the wire length of each bonding wire 306 is Rb1A, Rb1B, the wire resistance Rb2 is Rb2A, Rb2B, the wire resistance Rb3 is Rb3A, Rb3B, and the bus resistance (expansion resistance) Rn1 is Rn1A, Rn1B, bus resistance Rn2 is Rn2A, Rn2B, bus resistance Rn3 is Rn3A, Rn3B, and the source-drain resistance of the transistor itself is Rs1, Rs2, Rs3, and the numerical parameters of each resistor are appropriately designed And In this case, the resistance of the power transistor between the two terminals of the lead frame 307 including the resistance component of each bonding wire 306, the series resistance value of the element resistance component of each power transistor, and the bus resistance component is expressed by the following equation: It becomes as shown in.
Power transistor resistance between two lead frame terminals
= ((Rb1A + Rn1A + Rs1 + Rb1B + Rn1B) ×
(Rb2A + Rn2A + Rs2 + Rb2B + Rn2B) ×
(Rb3A + Rn3A + Rs3 + Rb3B + Rn3B))
/ ((Rb1A + Rn1A + Rs1 + Rb1B + Rn1B) ×
(Rb2A + Rn2A + Rs2 + Rb2B + Rn2B)
+ (Rb2A + Rn2A + Rs2 + Rb2B + Rn2B) ×
(Rb3A + Rn3A + Rs3 + Rb3B + Rn3B)
+ (Rb3A + Rn3A + Rs3 + Rb3B + Rn3B) ×
(Rb1A + Rn1A + Rs1 + Rb1B + Rn1B))
In this way, by providing one contact pad 304 for each divided bus, the resistance component due to the bonding wire length is taken into consideration, and the area size of the divided bus is reduced by utilizing it for bus size design. Can be adjusted. For this reason, by adjusting the current path for each power transistor so that the current can flow according to the size of each power transistor, the current density flowing through each divided power transistor itself flows almost uniformly, and The current that flows through each power transistor flows according to the size of each power transistor element without concentrating the current even at a large current. Therefore, the load on the power transistor element itself, bonding wires, metal layer buses and vias is evenly distributed, and the amount of heat generated per unit area of the power transistor element itself can be made uniform. The destruction of the power transistor element due to heat generation is prevented, and the current allowable value of the power transistor element as a whole is improved. As a result, the reliability of the semiconductor integrated circuit is improved.

  In addition, as shown in the plan view of FIG. 2, the buses 140 to 142, 150 to 152, which are the uppermost metal layers in the semiconductor integrated circuit shown in FIG. It can also be set as the structure where the area of 150-152 becomes equal. Other structures are the same as those of the semiconductor integrated circuit shown in FIG.

  According to the semiconductor integrated circuit shown in FIG. 2, unlike the conventional example in which a plurality of contact pads are commonly connected to one bus, each bus is divided and one contact pad 304 is provided for each divided bus. In addition to obtaining the effect of the semiconductor integrated circuit shown in FIG. 1 described above, the areas of the respective buses 140 to 142 and 150 to 152, which are the third metal layers of the uppermost layer, are uniform. Thus, the following effects can be further obtained.

  That is, the six buses 140 to 142 and 150 to 152 that are divided from each other are formed so as to have substantially the same area, and one contact pad 304 is provided for each of the buses 140 to 142 and 150 to 152. As a result, the ESD energy is distributed by the six buses 140 to 142 and 150 to 152 divided from each other through the bonding wire 306 from the lead frame 307 to which the ESD energy is directly applied. The peak value of the ESD energy applied to the transistor element is reduced by the amount of dispersion. Therefore, the ESD tolerance of the power transistor can be improved, and a semiconductor integrated circuit with higher reliability can be realized.

For example, three bus resistances (spreading resistances) are designed as Rn1 = 0.1Ω, Rn2 = 0.1Ω, Rn3 = 0.1Ω, and the source-drain resistance of the transistor itself is Rs1 = 0.13Ω, Rs2 = 0 When designed to be .13Ω and Rs3 = 0.13Ω, the series resistance values of the element resistance component and the bus resistance component of each power transistor are as shown in the following equation.
Rn1 × 2 + Rs1
= Rn2 × 2 + Rs2
= Rn3 × 2 + Rs3
= 0.33Ω
As described above, when the ESD energy is applied from the lead frame 307 through the bonding wire 306, the peak values of the ESD energy applied to the power transistor elements having the equally divided resistance components are divided from each other. Since the ESD energy is distributed according to the number of buses formed, the ESD tolerance of the power transistor determined by the peak value of the ESD energy can be improved. Further, by dividing the large-sized bus of the power transistor evenly, the stress due to the stress of the metal layer of the large-sized bus can be reduced. This eliminates the large area metal layer and reduces warpage in the power transistor. In this way, a semiconductor integrated circuit with higher reliability can be realized.

  Here, the positional relationship between the buses 140 to 142 and 150 to 152 which are the uppermost metal layers in the semiconductor integrated circuit shown in FIGS. 1 and 2 described above and the two metal layers provided therebelow will be described. Keep it. In the following, the case of the semiconductor integrated circuit shown in FIG. 2 will be described as an example in FIGS. 1 and 2. However, even in the case of the semiconductor integrated circuit shown in FIG. Can be conceived.

  3 and 4 are plan views schematically showing a positional relationship with the lower metal layer of the buses 140 to 142 and 150 to 152 shown in FIG. 3 and 4, each of the buses 140 to 142 and 150 to 152 is shown in perspective, and in FIG. 4, the second layer bus is shown in perspective.

  First, as shown in FIG. 3, the buses 140 to 142 and 150 to 152, which are the third layer in the present embodiment, have elongated stripes in the horizontal direction and are parallel to each other at a constant pitch. So that the metal layer 11, 12, 13, 14, 15, 16 of the source line (first metal pattern) as the second layer bus (second metal layer) and the second layer The metal layers 21, 22, 23, 24, 25, and 26 of the drain line (second metal pattern) as the bus are alternately formed. The third layer buses 140, 141 and 142 are connected to the source lines 11 and 12, 13 and 14, 15 and 16 as the second layer buses via a plurality of vias X1 filled with metal. The third-layer buses 150, 151, and 152 are connected to the drain lines 21 and 22, 23 and 24, 25, and 26 through a plurality of vias Y1 filled with metal, respectively. Yes.

  Further, as shown in FIG. 4, the metal layers 11 to 16 and 21 to 26 of the source line and the drain line as the second layer bus are directly connected to these second layer buses. And a source electrode line (first metal pattern) as a first-layer bus (first metal layer) so as to have an elongated vertical stripe shape and be parallel to each other at a constant pitch. ) And the metal layers D1 to D15 of the drain electrode line (second metal pattern) as the first-layer bus are alternately formed. The metal layers S1 to S15 of the source electrode line of the first layer bus are electrically connected to the source lines 11 to 16 which are the second layer buses, respectively, through a plurality of vias X filled with metal. The metal layers D1 to D15 of the drain electrode line of the first-layer bus are connected to the vias Y filled with metal, respectively. 21 to 26 are electrically connected. 1 to 4 are mainly for explaining the positional relationship among the first to third buses, vias, contact pads, and bonding wires formed on the semiconductor substrate. FIG. 5 is an interlayer insulating film (not shown) formed between the buses (for example, the first to fourth interlevel insulator layers in the second embodiment), an opening, and other specific configurations. Will be described using a specific example in the second embodiment.

-First modification-
FIG. 5 shows a simplified plan view of a first modification of the semiconductor integrated circuit according to the first embodiment of the present invention. The first modification is an example applicable to both of the semiconductor integrated circuits shown in FIGS. 1 and 2 described above. Hereinafter, the semiconductor integrated circuit shown in FIG. 1 will be described as the first modification. The circuit, that is, the buses 140 to 142 and 150 to 152 are applied to a semiconductor integrated circuit having a configuration in which each area is formed so as to gradually decrease from the side closer to the lead frame 307. This will be described as an example.

  In the first modification shown in FIG. 5, the active region of the power transistor is divided into three active regions 100a1, 100a2, 100a3, and the three active regions 100a1, 100a2, 100a3 are separated. It differs from the semiconductor integrated circuit shown in FIG. 1 in that three power transistors are formed which are electrically separated from each other by a film. Other structures are the same as those of the semiconductor integrated circuit shown in FIG.

  In this way, each of the buses 140 and 150, the buses 141 and 151, and the buses 142 and 153, which are symmetrical, is one power transistor that is electrically isolated from the adjacent transistor via the contact pad 304. Therefore, latch and parasitic malfunctions are less likely to occur, and the reliability can be improved.

  In the configuration of FIG. 5, even when the areas of the buses 140, 141, 142, 150, 151, and 152 are equal to each other, the same effect can be obtained.

-Second modification-
6 and 7 are simplified plan views showing a second modification of the semiconductor integrated circuit according to the first embodiment of the present invention. Similarly, the first modification is an example applicable to both of the semiconductor integrated circuits shown in FIGS. 1 and 2 described above, and is shown in FIG. 1 as the second modification. The semiconductor integrated circuit, that is, the buses 140 to 142 and 150 to 152 are applied to a semiconductor integrated circuit having a configuration in which each area is formed so as to gradually decrease from the side closer to the lead frame 307. This will be described as an example.

  In the second modification shown in FIGS. 6 and 7, as shown in FIGS. 6 and 7, the active regions 100B and 100C of the power transistor are narrow, and the buses 140c and 140d formed thereon are formed. When the areas of 141c and 141d, 142c and 142d, 150c and 150d, 151c and 151d, 152c and 152d are small, the contact pad 304 is formed on the buses 142c and 152c, 142d and 152d farthest from the lead frame 307 side. Is different from the semiconductor integrated circuit shown in FIG. Other structures are the same as those of the semiconductor integrated circuit shown in FIG.

  In this manner, the six buses 140 to 142 and 150 to 152 as described with reference to FIG. 1 are connected to the lead frame 307 while preventing the bonding wires 306 from contacting each other and preventing a short circuit between outputs. The effect of the case where they are formed so as to have different areas as they are separated, and the effect of the case where the six buses 140 to 142 and 150 to 152 as described with reference to FIG. Obtainable.

  Recent advances in wire bonding technology have made it possible to produce reliable ball contacts, long wires, and tightly controlled wire loop shapes. For example, a computer-controlled movement of the capillary in the air as defined in advance can produce a wire loop with a precisely defined shape, creating a round, trapezoidal, straight, or custom loop path Therefore, the semiconductor integrated circuit according to this embodiment described above is more useful.

(Second Embodiment)
Hereinafter, an example in which the semiconductor integrated circuit described in the first embodiment described above is specifically applied to each transistor to be described later will be described as a semiconductor integrated circuit according to the second embodiment of the present invention, and contact pads will be described. And the modification of a connection member is demonstrated. In addition, in this embodiment, since the content demonstrated in 1st Embodiment is the same also in this embodiment, the description is abbreviate | omitted.

-First embodiment-
The first example of the second embodiment of the present invention is an example in which a DMOS transistor is applied to the semiconductor integrated circuit according to the first embodiment described above.

  FIG. 8 is a simplified cross-sectional view for explaining the configuration of the semiconductor integrated circuit of the first example and the manufacturing method thereof in the second embodiment of the present invention.

  As shown in FIG. 8, a DMOS transistor is formed on a p-type silicon substrate 911 by a known method. That is, a DMOS transistor including an n-type buried region 913, an n-type well region 917, a body region 905, a source region 919, a drain contact region 921, a back gate region 922, a gate oxide 930, and a polysilicon gate 931 is formed. . A p-type well 916 is formed on the p-type silicon substrate 911 so as to be adjacent to the n-type well region 917, and a substrate contact region 927 is formed in the p-type well 916. An element isolation insulator layer 928 is formed so as to partition an element formation region on the p-type silicon substrate 911.

  Next, after the first interlevel insulator layer 941 is deposited on the entire surface of the p-type silicon substrate 911 so as to cover the above-described DMOS transistor and the like, the first level is formed by using a photolithography technique and an etching technique. A first via 942 a whose lower end reaches the back gate region 922 and the source region 919 and a first via 942 b whose lower end reaches the drain region 921 are formed in the intermediate insulator layer 941.

  Next, after depositing a metal layer (first metal layer) on the first inter-level insulator layer 941, patterning is performed by etching, whereby the lower surface is connected to the upper end of the first via 942a. Metal layer 943a (first metal pattern: first layer bus) and first metal layer 943b (second metal pattern: first layer bus) whose lower surface is connected to the upper end of first via 942b. Bus). Thus, the first metal layer 943a functions as a source electrode of the transistor, and the first metal layer 943b functions as a drain electrode of the transistor.

  Next, after depositing a second interlevel insulator layer 944 over the first interlevel insulator layer 941 so as to cover the first metal layers 943a and 943b, a photolithography technique and an etching technique are used. Thus, a second via 945a whose lower end reaches the first metal layer 943a and a second via 945b whose lower end reaches the first metal layer 943b are formed in the second inter-level insulator layer 944. .

  Next, after depositing a metal layer (second metal layer) on the second interlevel insulator layer 944, patterning is performed by etching, whereby the lower surface is connected to the upper end of the second via 945a. Metal layer 946a (first metal pattern: second layer bus) and second metal layer 946b (second metal pattern: second layer bus) whose lower surface is connected to the upper end of second via 945b. Bus). Thus, the second metal layer 946a functions as an extension of the source electrode of the transistor, and the second metal layer 946b functions as an extension of the drain electrode of the transistor.

  Next, after depositing a third inter-level insulator layer 947 over the second inter-level insulator layer 944 so as to cover the second metal layers 946a and 946b, a photolithography technique and an etching technique are used. Thus, a third via 948a whose lower end reaches the first metal layer 946a is formed in the third inter-level insulator layer 947. Note that the plurality of third vias 948a are electrically connected to the source electrode of the transistor and are not illustrated, but a plurality of vias electrically connected to the drain electrode of the transistor are formed in the same manner.

  Next, after depositing a metal layer (third metal layer) on the third inter-level insulator layer 947, patterning is performed by etching, whereby the lower surface is connected to the upper end of the third via 948a. The metal layer 949a (third layer bus) is formed. The third metal layer 949a electrically connected to the second metal layer 946a and the first metal layer 943a functions as a bus for the source electrode of the transistor. Note that although not illustrated, a third via and a third metal layer which are electrically connected to the second metal layer 946b and the first metal layer 943b are formed in the same manner, and these are formed in the drain of the transistor. Functions as a bus for electrodes.

  Next, after depositing a fourth interlevel insulator layer 950 on the third interlevel insulator layer 947 so as to cover the third metal layer 949a and a third metal layer (not shown), photolithography is performed. An opening 956 is formed in the fourth interlevel insulator layer 950 using techniques and etching techniques. Thus, the opening 956 is formed so as to be positioned vertically above at least one third via 948a for electrically connecting the third metal layer 949a to the source electrode. An opening (not shown) is formed so as to be positioned vertically above at least one third via that electrically connects the third metal layer to the drain electrode.

  Next, after depositing a metal layer having a thickness more than twice the thickness of the third metal layer 949a over the opening 956 exposing the third metal layer 949a, patterning is performed by etching. A contact pad 951 having a film thickness twice or more that of the third metal layer 949a is formed. In this way, the connection between the contact pad 951 and the third metal layer 949a as the third-layer bus is made by a portion of the contact pad 951 located at the lower part of the opening 956, that is, a single via. Has been done. The diameter of the single via is preferably 50 μm or more. Subsequently, a protective coating layer 955 is deposited on the fourth interlevel insulator layer 950 and the contact pad 951, and then patterned by etching to form an opening exposing the contact pad 951. Then, a ball 961 and a bonding wire 962 are formed on the contact pad 951. In FIG. 8, the contact pad 951 is provided on the third metal layer 949a functioning as a source bus, and although not shown, the contact pad 951 is also in contact with the third metal layer functioning as a drain bus. • Pads are provided as well.

  As described above, according to the first example of the second embodiment of the present invention, the first to third metal layers 943a as the first to third layer buses are directly above the DMOS transistors. , 946a and 949a and the contact pad 951 improve the integration density of the IC, so that the chip can be saved. Further, a third metal layer 949a (including a third metal layer not shown) serving as a third-layer bus is provided at least in the third via 948a (including a third metal layer not shown). A contact pad 951 having a thickness that is at least twice the thickness of the third-layer bus is formed in the opening 956 that is formed so as to be positioned vertically above one and exposes the third metal layer 949a. By forming, the ON resistance can be reduced, so that high speed and low power consumption can be achieved, and at the same time, the stress at the time of wire bonding can be absorbed and the generation of cracks can be reduced.

  In the present embodiment, the case where the semiconductor integrated circuit is an N-channel type DMOS transistor has been described. However, the semiconductor integrated circuit may be a P-channel type DMOS transistor. The structure is not limited.

-First modification of the first embodiment-
A first modification of the first example of the present embodiment is an example in which a DMOS transistor integrated on an SOI substrate is applied to the semiconductor integrated circuit according to the first example described above.

  FIG. 9A is a simplified cross-sectional view for explaining the configuration of a semiconductor integrated circuit according to a first modification of the first example of the present embodiment and the method for manufacturing the semiconductor integrated circuit. This modification is different from the configuration and manufacturing method of the first embodiment shown in FIG. 8 described above in that the DMOS transistor is integrated on the SOI substrate, and the other configuration and manufacturing method are the same. is there.

  As shown in FIG. 9A, a DMOS transistor is formed on a p-type silicon substrate 911 and a buried insulator layer 912 by a known method. That is, a DMOS including a p-type well region 916, an n-type well region 917, a body region 918, a source region 919, a drain region 920, a drain contact region 921, a back gate region 922, a gate oxide 930, and a polysilicon gate 931. A transistor is formed. A trench isolation insulator layer 929 is formed in part of the p-type silicon substrate 911 and the p-type well region 916.

  As described above, according to the first modification of the first example of the present embodiment, in addition to the effects of the first example described above, complete isolation is achieved when an SOI substrate is used as the semiconductor substrate. Therefore, latch and parasitic malfunctions are less likely to occur, and reliability can be improved.

-Second modification of the first embodiment-
The second modification of the first example of the present embodiment is an example in which a DMOS transistor integrated on an epitaxial substrate is applied to the semiconductor integrated circuit according to the first example described above.

  FIG. 9B is a simplified cross-sectional view for explaining the configuration of the semiconductor integrated circuit according to the second modification of the first example of the present embodiment and the manufacturing method thereof. This modification is different from the configuration and manufacturing method of the first embodiment shown in FIG. 8 described above in that the DMOS transistor is integrated on the epitaxial substrate, and the other configuration and manufacturing method are the same. is there.

  As shown in FIG. 9B, a DMOS transistor is formed on a p-type silicon substrate 911 by a known method. That is, a DMOS transistor including an n-type buried region 913, an epitaxial region 915, a body region 918, a source region 919, a drain region 920, a drain contact region 921, a back gate region 922, a gate oxide 930, and a polysilicon gate 931 is formed. Form. A p-type buried region 914 and a p-type well region 916 are formed so as to be adjacent to the epitaxial region 915.

  As described above, according to the second modification of the first example of the present embodiment, in addition to the effect of the first example described above, when an epitaxial substrate is used as the semiconductor substrate, the power The current capability of the transistor can be improved.

-Third modification of the first embodiment-
A third modification of the first embodiment of the present embodiment is an example in which the semiconductor integrated circuit according to the first embodiment described above is applied to a DMOS transistor, and includes a contact pad and a third layer bus. This is an example in which the connection to is made with a plurality of vias.

  FIG. 10A is a simplified cross-sectional view for explaining the configuration of a semiconductor integrated circuit according to a third modification of the first example of the present embodiment and the manufacturing method thereof. This modification is different from the configuration and manufacturing method of the first embodiment shown in FIG. 8 in that the contact pad and the third layer bus are connected by a plurality of vias. Other configurations and manufacturing methods are the same. That is, in the configuration of FIG. 8, the connection between the contact pad and the third layer bus is made by a single via.

  In this modification, as shown in FIG. 10A, as a connection between the third metal layer 949a and the contact pad 951, a fourth inter-level insulation is provided at a position corresponding to the opening 956 shown in FIG. A plurality of via arrays 950a provided through the body layer 950 are used.

  As described above, according to the third modified example of the first example of the present embodiment, in addition to the effects of the first example described above, the use of the plurality of via arrays 950a makes it possible to perform wire bonding. It is possible to reduce the occurrence of cracks by absorbing the stress.

-Fourth modification of the first embodiment-
A fourth modification of the first example of the present embodiment is an example in which a DMOS transistor is applied as the semiconductor integrated circuit according to the first example described above, and the contact pad is formed by a plating method. It is an example.

  FIG. 10B is a simplified cross-sectional view for explaining the configuration of the semiconductor integrated circuit according to the fourth modification of the first example of the present embodiment and the method for manufacturing the semiconductor integrated circuit. This modification is different from the configuration and manufacturing method of the first embodiment shown in FIG. 8 described above in that the contact pads are formed by plating, and the other configurations and manufacturing methods are the same. .

  As shown in FIG. 10B, a contact pad 951b is formed by plating within the opening 956 exposing the third metal layer 949a and on the fourth interlevel insulator layer 950.

  As described above, according to the fourth modification example of the first example of the present embodiment, in addition to the effects of the first example described above, it is easy to increase the thickness of the third metal layer 949a. Therefore, it is possible to increase the speed and reduce the power consumption by reducing the ON resistance of the power transistor, and it is possible to absorb the stress during wire bonding and reduce the occurrence of cracks.

-Fifth modification of the first embodiment-
A fifth modification of the first example of the present embodiment is an example in which a DMOS transistor is applied as the semiconductor integrated circuit according to the first example described above, and a case where a solder ball is used as a connection member. It is an example.

  FIG. 11A is a simplified cross-sectional view for explaining a configuration of a semiconductor integrated circuit according to a fifth modification of the first example of the present embodiment and a manufacturing method thereof. In addition, as described above, the present modification is different from the first embodiment shown in FIG. 8 described above in that solder balls are formed instead of the balls 961 and the bonding wires 962 (see FIG. 8). The configuration and the manufacturing method are different, and the other configuration and the manufacturing method are the same.

  As shown in FIG. 11A, solder balls 963 are formed inside the third metal layer 949a and on the protective coating layer 955.

  As described above, according to the fifth modification of the first example of the present embodiment, in addition to the effects of the first example described above, the solder ball 963 is used as a member connected to the contact pad 951. As a result, a chip size package can be used, so that the IC package size can be reduced.

-Sixth modification of the first embodiment-
A sixth modification of the first example of the present embodiment is an example in which a DMOS transistor is applied as the semiconductor integrated circuit according to the first example described above, and a plated metal layer is used as a connection member. It is an example.

  FIG. 11B is a simplified cross-sectional view for explaining the configuration of the semiconductor integrated circuit according to the fifth modification of the first example of the present embodiment and the method for manufacturing the same. Note that, as described above, the present modified example is the first embodiment shown in FIG. 8 described above in that a plated metal layer is formed instead of the balls 961 and the bonding wires 962 (see FIG. 8) as connecting members. Unlike the configuration and manufacturing method of the example, other configurations and manufacturing methods are the same.

  As shown in FIG. 11B, a plated metal layer 964 is formed inside the third metal layer 949a and on the protective coating layer 955.

  As described above, according to the sixth modification of the first example of the present embodiment, in addition to the effects of the first example described above, the plated metal layer 964 is used as a member connected to the contact pad 951. By using this, it becomes easy to increase the thickness of the third metal layer 949a, so that the speed and power consumption can be reduced by reducing the ON resistance of the power transistor, and the stress at the time of wire bonding can be absorbed. It is possible to reduce the occurrence of cracks.

  In the second to sixth modifications of the first embodiment described above, the case where the semiconductor integrated circuit is an N-channel DMOS transistor has been described. However, if the connection to the wiring metal layer is the same, the power -It does not limit the kind and structure of a transistor.

-Second embodiment-
The second example of the second embodiment of the present invention is an example in which a CMOS transistor is applied to the semiconductor integrated circuit according to the first embodiment described above.

  FIG. 12 is a simplified cross-sectional view for explaining the configuration of the semiconductor integrated circuit of the second example and the manufacturing method thereof in the second embodiment of the present invention. This embodiment is different from the first embodiment in which the DMOS transistors shown in FIG. 8 are integrated in that CMOS transistors are integrated, and the other configuration and manufacturing method are the same.

  As shown in FIG. 12, a CMOS transistor is formed on a p-type silicon substrate 911, an n-type buried region 913, and a p-type well region 916 by a known method. That is, a CMOS transistor including a source region 919, a drain contact region 921, a back gate region 922, a gate oxide 930, and a polysilicon gate 931 is formed.

  As described above, according to the second example of the second embodiment of the present invention, it is possible to obtain the same effect as the effect of the DMOS transistor in the first example. That is, IC integration is performed by disposing first to third metal layers 943a, 946a and 949a as first to third layer buses and contact pads 949a immediately above the CMOS transistors. Since the degree is improved, the chip can be saved. In addition, a third metal layer 946a (including a third metal layer not shown) serving as a third-layer bus is provided at least in the third via 948a (including a third metal layer not shown). A contact pad 951 having a thickness more than twice the thickness of the third-layer bus is formed in an opening 956 that is formed so as to be positioned one vertically upward and exposes the third metal layer 946a. By forming, the ON resistance can be reduced, so that high speed and low power consumption can be achieved, and at the same time, the stress at the time of wire bonding can be absorbed and the generation of cracks can be reduced.

  In the second example of the present embodiment, the case where the semiconductor integrated circuit is an N-channel type MOS transistor has been described. However, the semiconductor integrated circuit may be a P-channel type MOS transistor, and the connection with the wiring metal layer may be performed. If it is the same, it is not limited to the above-mentioned structure.

-Third embodiment-
A third example of the second embodiment of the present invention is an example in which a bipolar transistor is applied to the semiconductor integrated circuit according to the first embodiment described above.

  FIG. 13 is a simplified cross-sectional view for explaining the configuration of the semiconductor integrated circuit according to the third example and the manufacturing method thereof in the second embodiment of the present invention.

  As shown in FIG. 13, a bipolar transistor is formed on a p-type silicon substrate 911 by a known method. That is, a bipolar transistor including an n-type buried region 913, an n-type well region 917, an emitter region 923, a base region 924, a base contact region 925, and a collector contact region 926 is formed. A p-type well 916 is formed on the p-type silicon substrate 911 so as to be adjacent to the n-type well region 917, and a substrate contact region 927 is formed in the p-type well 916. An element isolation insulator layer 928 is formed so as to partition an element formation region on the p-type silicon substrate 911.

  Next, a first interlevel insulator layer 941 is deposited on the entire surface of the p-type silicon substrate 911 so as to cover the above-described bipolar transistor and the like, and then the first level is formed by using a photolithography technique and an etching technique. A first via 942 a whose lower end reaches the emitter region 923 and a first via 942 b whose lower end reaches the collector region 926 are formed in the intermediate insulator layer 941.

  Next, after depositing a metal layer (first metal layer) on the first inter-level insulator layer 941, patterning is performed by etching, whereby the lower surface is connected to the upper end of the first via 942a. Metal layer 943a (first metal pattern: first layer bus) and first metal layer 943b (second metal pattern: first layer bus) whose lower surface is connected to the upper end of first via 942b. Bus). Thus, the first metal layer 943a is electrically connected to the emitter region 923 and functions as an emitter electrode of the transistor, and the first metal layer 943b is electrically connected to the collector contact region 926 and is connected to the collector electrode of the transistor. Function as.

  Next, after depositing a second interlevel insulator layer 944 over the first interlevel insulator layer 941 so as to cover the first metal layers 943a and 943b, a photolithography technique and an etching technique are used. Thus, a second via 945a whose lower end reaches the first metal layer 943a and a second via 945b whose lower end reaches the first metal layer 943b are formed in the second inter-level insulator layer 944. .

  Next, after depositing a metal layer (second metal layer) on the second interlevel insulator layer 944, patterning is performed by etching, whereby the lower surface is connected to the upper end of the second via 945a. Metal layer 946a (first metal pattern: second layer bus) and second metal layer 946b (second metal pattern: second layer bus) whose lower surface is connected to the upper end of second via 945b. Bus). Thus, the second metal layer 946a functions as an extension of the emitter electrode of the transistor, and the second metal layer 946b functions as an extension of the collector electrode of the transistor.

  Next, after depositing a third inter-level insulator layer 947 over the second inter-level insulator layer 944 so as to cover the second metal layers 946a and 946b, a photolithography technique and an etching technique are used. Thus, a third via 948a having a lower end reaching the second metal layer 946a is formed in the third inter-level insulator layer 947. Note that the plurality of third vias 948a are electrically connected to the emitter electrode of the transistor, and although not shown, a plurality of vias electrically connected to the collector electrode of the transistor are formed in the same manner.

  Next, after depositing a metal layer (third metal layer) on the third inter-level insulator layer 947, patterning is performed by etching, whereby the lower surface is connected to the upper end of the third via 948a. The metal layer 949a (third layer bus) is formed. The third metal layer 949a electrically connected to the second metal layer 946a and the first metal layer 943a functions as a bus for the emitter electrode of the transistor. Although not shown, a third via and a third metal layer electrically connected to the second metal layer 946b and the first metal layer 943b are also formed in the same manner, and these are the collector of the transistor. Functions as a bus for electrodes.

  Next, after depositing a fourth interlevel insulator layer 950 on the third interlevel insulator layer 947 so as to cover the third metal layer 949a and a third metal layer (not shown), photolithography is performed. An opening 956 is formed in the fourth interlevel insulator layer 950 using techniques and etching techniques. Thus, the opening 956 is formed so as to be positioned vertically above at least one third via 948a for electrically connecting the third metal layer 949a to the emitter electrode. An opening (not shown) is formed so as to be positioned vertically above at least one third via that electrically connects the third metal layer to the collector electrode.

  Next, after depositing a metal layer having a thickness more than twice the thickness of the third metal layer 949a over the opening 956 exposing the third metal layer 949a, patterning is performed by etching. A contact pad 951 having a film thickness twice or more that of the third metal layer 949a is formed. Subsequently, a protective coating layer 955 is deposited on the fourth interlevel insulator layer 950 and the contact pad 951, and then patterned by etching to form an opening exposing the contact pad 951. Then, a ball 961 and a bonding wire 962 are formed on the contact pad 951. In FIG. 13, the contact pad 951 is provided on the third metal layer 949a that functions as an emitter bus. Although not shown, the contact pad 951 is also in contact with the third metal layer that functions as a collector bus. • Pads are provided as well.

  As described above, according to the second example of the second embodiment of the present invention, even in the present example using the bipolar transistor as the power transistor, the first example using the DMOS transistor as the power transistor. The effect similar to the effect by can be obtained. That is, IC integration is performed by disposing first to third metal layers 943a, 946a, and 949a as first to third-layer buses and contact pads 951 immediately above the bipolar transistor. Since the degree is improved, the chip can be saved. Further, a third metal layer 949a (including a third metal layer not shown) serving as a third-layer bus is provided at least in the third via 948a (including a third metal layer not shown). A contact pad 951 having a thickness that is at least twice the thickness of the third-layer bus is formed in the opening 956 that is formed so as to be positioned vertically above one and exposes the third metal layer 949a. By forming, the ON resistance can be reduced, so that high speed and low power consumption can be achieved, and at the same time, the stress at the time of wire bonding can be absorbed and the generation of cracks can be reduced.

  In the second example of the present embodiment, the case where the semiconductor integrated circuit is an NPN transistor has been described. However, the semiconductor integrated circuit may be a PNP transistor, and if the connection to the wiring metal layer is the same, the above-described case is possible. The structure is not limited.

  Further, the first to fifth modifications described in the first example can be similarly applied to the second and third examples of the present embodiment.

  It should also be pointed out that in the first and second embodiments described above, the arrangement of contact pads 951 can also be used to improve the dissipation of thermal energy released by the active components of the IC. This is particularly true when solder bumps are employed as external connection means for the purpose of minimizing the thermal resistance and heat path for heat dissipation.

  In addition, the first inter-level insulator layer 941, the second inter-level insulator layer 944, the third inter-level insulator layer 947, and the fourth inter-level insulator layer 950 are formed of, for example, a nitride or an oxide A combination of nitride / oxide, SOG, BPSG, or a low dielectric constant gel may be used, and the material and thickness are not particularly limited.

  Similarly, the protective coating layer 955 may be, for example, silicon nitride, silicon oxynitride, silicon-carbon alloy, oxide / nitridation as long as it is mechanically strong and electrically insulating and cannot pass moisture. A combination of objects, polyimide, and a sandwich structure film thereof may be used, and the material and thickness are not particularly limited.

  Also, first metal layers (first-layer buses) 943a and 943b, second metal layers (second-layer buses) 946a and 946b, and third metal layer (third-layer bus) 949a. Similarly, the contact pad 951 (304) may be made of, for example, a metal such as aluminum or copper, or a metal alloy, and the material and thickness thereof are not particularly limited.

  In addition, as a configuration of the bus, the case where three metal layers (buses), that is, the first metal layers 943a and 943b, the second metal layers 946a and 946b, and the third metal layer 949a are described. The metal layer (bus) may be a single layer or two layers, or more than three metal layers (buses) may be formed. Furthermore, the pattern formation of these metal layers (buses) is not limited to etching, and a damascene method in which grooves are formed in the inter-level insulator layers and a metal material is embedded may be employed.

  In addition, the present invention should not be construed as being limited to the description in each embodiment described above. It will be apparent to those skilled in the art from reference to the present description that various modifications and combinations to the exemplary embodiments are possible with other embodiments of the invention. By way of example, the present invention includes contact pads located over active components, the positions of which are selected to provide control and distribution of power to the active components under the pads. The semiconductor integrated circuit is generally covered. As yet another example, the present invention includes contact pads located over active components, the pads corresponding to a selected pad and one or more pads to be powered. Covers semiconductor ICs arranged to minimize the distance of power distribution to active components. Accordingly, the appended claims are intended to encompass all such modifications and embodiments.

  A semiconductor integrated circuit and a method for manufacturing the same according to the present invention utilize a pad technology immediately above a device and devise a power integrated circuit that performs wire bonding directly above an active circuit region portion, thereby providing a power source, a motor driver, Alternatively, it contributes to both lower power consumption and improved reliability in the performance of core semiconductor electronic components such as audio amplifiers. Therefore, the present invention can be easily realized at low cost because existing equipment is utilized in manufacturing, and is extremely useful for an inexpensive, high-quality and high-performance power integrated circuit.

The main part of the semiconductor integrated circuit according to the first embodiment of the present invention has a configuration in which one contact pad is arranged on each of six bus metal layers (third-layer buses) having different areas in order. FIG. 2 is a simplified plan view schematically showing a part of an IC chip having an electric circuit diagram representing an electric resistance along a current flow at a lower portion thereof. 1 is a schematic view of a part of an IC chip, which is a main part of a semiconductor integrated circuit according to a first embodiment of the present invention, and has a configuration in which one contact pad is arranged on each of six equally divided bus metal layers. FIG. 6 is a main part of the semiconductor integrated circuit according to the first embodiment of the present invention, and is divided into six equally divided bus metal layers (third-layer bus), and source and drain electrode lines in the one lower layer; It is the simplified top view which showed typically a part of IC chip which shows the arrangement | positioning relationship between the metal layer (2nd layer bus | bath) used and via | veer. 6 is a main part of the semiconductor integrated circuit according to the first embodiment of the present invention, in which six equally divided bus metal layers (third-layer bus) and lines for source and drain electrodes in one lower layer A part of the IC chip showing the positional relationship between the metal layer (second layer bus) to be used and the metal layer (first layer bus) to be the source and drain electrodes in the lower layer and vias. FIG. The main part of the semiconductor integrated circuit according to the first modified example of the first embodiment of the present invention, in which one contact pad is arranged on each of six bus metal layers having different areas in order and divided. FIG. 5 is a simplified plan view schematically showing a part of an IC chip having a configuration in which three power transistors are each surrounded by a separation film. 11 is a main part of a semiconductor integrated circuit according to a second modification of the first embodiment of the present invention, in which one contact pad is arranged on each of six bus metal layers having different areas in order and immediately above the device. The pad is a simplified plan view schematically showing a part of an IC chip having a configuration in which the pad partially protrudes from the bus immediately below. 11 is a main part of a semiconductor integrated circuit according to a second modification of the first embodiment of the present invention, in which one contact pad is arranged on each of six bus metal layers having different areas in order and immediately above the device. The pad is a simplified plan view schematically showing a part of an IC chip having a configuration in which the entire pad protrudes from the bus immediately below. FIG. 10 is a simplified cross-sectional view showing a main part of an integrated DMOS transistor, which is a semiconductor integrated circuit according to a first example of the second embodiment of the present invention. (A) is a semiconductor integrated circuit which concerns on the 1st modification of the 1st Example in the 2nd Embodiment of this invention, Comprising: The simplification which shows the principal part of the DMOS transistor integrated on the SOI substrate It is sectional drawing, (b) is a semiconductor integrated circuit which concerns on the 2nd modification of the 1st Example in the 2nd Embodiment of this invention, Comprising: DMOS transistor integrated on the epitaxial substrate It is a simplified sectional view showing an important section. (A) is the semiconductor integrated circuit which concerns on the 3rd modification of the 1st Example in the 2nd Embodiment of this invention, Comprising: A contact pad and a 3rd-layer bus | bath are comprised by several vias. It is a simplified sectional view showing the important section of an integrated DMOS transistor which has the connected composition, and (b) is a semiconductor concerning the 4th modification of the 1st example in a 2nd embodiment of the present invention. FIG. 2 is a simplified cross-sectional view showing a main part of an integrated DMOS transistor which is an integrated circuit and has a configuration in which contact pads are formed by plating. (A) is the semiconductor integrated circuit which concerns on the 5th modification of the 1st Example in the 2nd Embodiment of this invention, Comprising: It integrated with the structure to which the solder ball was attached as a connection member It is a simplified sectional view showing the principal part of a DMOS transistor, and (b) is a semiconductor integrated circuit concerning the 6th modification of the 1st example in the 2nd embodiment of the present invention, Comprising: It is a simplified sectional view showing a main part of an integrated DMOS transistor having a configuration to which a plated metal layer is attached. FIG. 10 is a simplified cross-sectional view showing a main part of an integrated CMOS transistor, which is a semiconductor integrated circuit according to a first example of the second embodiment of the present invention. FIG. 10 is a simplified cross-sectional view showing a main part of an integrated bipolar transistor, which is a semiconductor integrated circuit according to a first example of the second embodiment of the present invention. In the prior art, a simplified plane schematically showing a main part of an IC chip including a power transistor having a plurality of contact pads arranged on each bus metal layer and commonly connected on the bus metal layer. FIG.

Explanation of symbols

100 IC (integrated circuit) chips 110A, 100B, 100C Active region (power transistor)
140, 141, 142, 150, 151, 152 Metal layer (third bus: second metal layer)
11-16 Source line Metal layer (second layer bus: first metal pattern)
21 to 26 Drain line Metal layer (second layer bus: second metal pattern)
S1 to S15 Line for source electrode Metal layer (first layer bus: first metal pattern)
D1 to D15 Drain electrode line Metal layer (first layer bus: second metal pattern)
X Via for connecting source electrode line (first layer bus) and source line (second layer bus) Y drain electrode line (first layer bus) and drain line (second layer bus) Via X1 that connects the bus) Bus Y1 that connects the source line (second layer bus) and the bus (third layer bus) Drain line (second layer bus) and the bus (third layer bus) Via 304 connecting contact pad 306 bonding wire 307 active region 140c, 140d, 141c, 141d, 142c, 142d, 150d, 150c, 151c, 151d, 152c, divided by separation of lead frame 100a1, 100a2, 100a3, 152d metal layer (third layer bus)
911 p-type silicon substrate 912 buried insulator layer 913 n-type buried region 914 p-type buried region 915 epitaxial region 916 p-type well region 917 n-type well region 918 body region 919 source region 920 drain region 921 drain contact region 922 back gate region 923 Emitter region 924 Base region 925 Base contact region 926 Collector contact region 927 Substrate contact region 928 Element isolation insulator layer 929 Trench isolation insulator layer 930 Gate oxide 931 Polysilicon gate 941 First inter-level insulator layer 942 One via 943a, 943b first metal layer (first layer bus: first and second metal patterns)
944 Second inter-level insulator layer 945 Second via 946a, 946b Second metal layer (second layer bus: first and second metal patterns)
947 Third interlevel insulator layer 948 Third via 949a Third metal layer (third layer bus)
950 Fourth inter-level insulator layer 951 Contact pad 955 Protective coating layer 956 Opening 961 Ball 962 Bonding wire 963 Solder ball 964 Plating metal layer

Claims (16)

A power transistor formed on a semiconductor substrate;
An interlayer insulating film formed on the power transistor;
A plurality of first metal patterns comprising a first metal layer formed in the interlayer insulating film and immediately above the power transistor, and functioning as a first electrode of the power transistor;
A plurality of second metal patterns comprising the first metal layer and functioning as second electrodes of the power transistor;
The second metal layer is formed in the interlayer insulating film and immediately above the first metal layer, and the first metal pattern corresponding to the first metal pattern is electrically connected to the first metal pattern. A plurality of first buses connected to each other,
A plurality of second buses made of the second metal layer and electrically connected to a corresponding second metal pattern among the plurality of second metal patterns;
A contact pad provided for each of the plurality of first buses and the plurality of second buses,
Each of the plurality of first buses and each of the plurality of second buses are formed so that the area decreases in order from the one located closer to the external connection member to the one located farther. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1,
A semiconductor integrated circuit, wherein the external connection member includes at least a lead frame. The semiconductor integrated circuit according to claim 1,
2. The semiconductor integrated circuit according to claim 1, wherein the power transistor is divided into a plurality by a separation layer so as to correspond to each of the plurality of buses and each of the plurality of second buses. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit according to claim 1, wherein the size of the power transistor is larger than the size of each of the contact pads in plan view. The semiconductor integrated circuit according to claim 4,
Each of the contact pads is included in a region where the power transistor is formed in a plan view. The semiconductor integrated circuit according to claim 4,
Each of the contact pads protrudes partly from the region where the power transistor is formed in plan view. The semiconductor integrated circuit according to claim 4,
Each of the contact pads protrudes entirely from the region where the power transistor is formed in plan view. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit according to claim 1, wherein the power transistor is a DMOS transistor. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit according to claim 1, wherein the power transistor is a CMOS transistor. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit according to claim 1, wherein the power transistor is a bipolar transistor. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit, wherein the semiconductor substrate is an SOI substrate. The semiconductor integrated circuit according to claim 1,
A semiconductor integrated circuit, wherein the semiconductor substrate is an epitaxial substrate. The semiconductor integrated circuit according to claim 1,
The thickness of each of the contact pads is at least twice the thickness of each of the plurality of first buses and the plurality of second buses. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit according to claim 1, wherein the contact pad is connected to the first bus or the second bus through a single via. The semiconductor integrated circuit according to claim 14, wherein
The semiconductor integrated circuit according to claim 1, wherein the diameter of the single via is 50 μm or more. The semiconductor integrated circuit according to claim 1,
A connection between the contact pad and the first bus or the second bus is made through a plurality of via arrays.

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