TWI576976B - Coreless package structure - Google Patents
Coreless package structure Download PDFInfo
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- TWI576976B TWI576976B TW104128470A TW104128470A TWI576976B TW I576976 B TWI576976 B TW I576976B TW 104128470 A TW104128470 A TW 104128470A TW 104128470 A TW104128470 A TW 104128470A TW I576976 B TWI576976 B TW I576976B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明是有關於一種無核心層封裝結構。 The present invention relates to a coreless package structure.
隨著電子產業的蓬勃發展,電子產品亦逐漸進入多功能、高性能的研發方向。為滿足半導體元件高積集度(Integration)以及微型化(Miniaturization)的要求,半導體封裝結構的各項要求亦越來越高。舉例來說,封裝結構中定義封裝基板的線寬、線距的關鍵尺寸(critical dimension)要求越來越小,封裝結構的整體厚度亦要求越小越好。 With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the requirements of high integration and miniaturization of semiconductor components, the requirements for semiconductor package structures are becoming higher and higher. For example, in the package structure, the critical dimension of the line width and the line pitch of the package substrate is required to be smaller and smaller, and the overall thickness of the package structure is required to be as small as possible.
習知之半導體封裝結構是將半導體晶片黏貼於基板頂面,進行打線接合(Wire Bonding)或覆晶接合(Flip Chip)封裝。覆晶技術之特徵在於半導體晶片與封裝基板間的電性連接係直接以焊料凸塊為之而非一般之金線,此種覆晶技術之優點在於能提高電性接點密度,並降低封裝元件尺寸;同時,該種覆晶技術不需使用長度較長之金線,而能降低阻抗及雜訊,提高電性表現以滿足高頻訊號傳輸所需。 The conventional semiconductor package structure is to adhere a semiconductor wafer to the top surface of the substrate for wire bonding or Flip Chip packaging. The flip chip technology is characterized in that the electrical connection between the semiconductor wafer and the package substrate is directly solder bump instead of the general gold wire. The advantage of the flip chip technology is that the electrical contact density can be improved and the package can be reduced. Component size; at the same time, this kind of flip chip technology does not need to use a long length of gold wire, but can reduce impedance and noise, improve electrical performance to meet the needs of high-frequency signal transmission.
為了進一步改善半導體封裝結構的各項特 性,相關領域莫不費盡心思開發。如何能提供一種具有較佳特性的半導體封裝結構,實屬當前重要研發課題之一,亦成為當前相關領域亟需改進的目標。 In order to further improve the various features of the semiconductor package structure Sex, related fields do not bother to develop. How to provide a semiconductor package structure with better characteristics is one of the current important research and development topics, and it has become an urgent need for improvement in related fields.
本發明之一技術態樣是在提供一種無核心層封裝結構,以降低其線路的線寬與線距,且結合散熱元件以增加散熱能力。 One aspect of the present invention provides a coreless package structure to reduce the line width and line spacing of the lines, and to combine heat dissipating components to increase heat dissipation capability.
根據本發明一實施方式,一種無核心層封裝結構包含基礎線路層、增層線路結構、複數個凸塊、晶片、至少一第一導電柱以及封裝膠體。增層線路結構包含設置於基礎線路層上的介電層、設置於介電層上的圖案化金屬層以及形成於介電層中的複數個導電盲孔,基礎線路層的線寬與線距小於約5微米,圖案化金屬層具有供覆晶接合之第一部分與供封裝堆疊之第二部分,導電盲孔電性連接基礎線路層與圖案化金屬層。凸塊設置於第一部分上。晶片設置於凸塊上。第一導電柱設置於第二部分上。封裝膠體設置於增層線路結構上,並至少部分覆蓋晶片。 According to an embodiment of the invention, a coreless package structure includes a base circuit layer, a build-up line structure, a plurality of bumps, a wafer, at least one first conductive pillar, and an encapsulant. The build-up line structure comprises a dielectric layer disposed on the base circuit layer, a patterned metal layer disposed on the dielectric layer, and a plurality of conductive blind vias formed in the dielectric layer, and a line width and a line pitch of the base circuit layer Less than about 5 microns, the patterned metal layer has a first portion for flip chip bonding and a second portion for the package stack, the conductive vias electrically connecting the base circuit layer and the patterned metal layer. The bump is disposed on the first portion. The wafer is disposed on the bump. The first conductive pillar is disposed on the second portion. The encapsulant is disposed on the build-up wiring structure and at least partially covers the wafer.
於本發明之一或多個實施方式中,基礎線路層的線寬與線距小於約2微米。 In one or more embodiments of the invention, the line width and line pitch of the base layer are less than about 2 microns.
於本發明之一或多個實施方式中,第一導電柱為環狀結構,環狀結構圍繞形成中央區域,封裝膠體設置於中央區域中。 In one or more embodiments of the present invention, the first conductive pillar is a ring structure, the annular structure surrounds the central region, and the encapsulant is disposed in the central region.
於本發明之一或多個實施方式中,第一導電柱的數量為複數個,且第一導電柱的設置位置定義出圍繞中央區域的環形區域,封裝膠體設置於中央區域中。 In one or more embodiments of the present invention, the number of the first conductive pillars is plural, and the disposed position of the first conductive pillar defines an annular region surrounding the central region, and the encapsulant is disposed in the central region.
於本發明之一或多個實施方式中,無核心層封裝結構更包含設置於晶片上的散熱元件。 In one or more embodiments of the present invention, the coreless package structure further includes a heat dissipating component disposed on the wafer.
於本發明之一或多個實施方式中,無核心層封裝結構更包含設置於第一導電柱上的封裝結構。 In one or more embodiments of the present invention, the coreless package structure further includes a package structure disposed on the first conductive pillar.
於本發明之一或多個實施方式中,封裝膠體圍繞第一導電柱。 In one or more embodiments of the invention, the encapsulant surrounds the first conductive pillar.
於本發明之一或多個實施方式中,第一導電柱的數量為複數個,封裝結構包含封裝本體與設置於封裝本體上的複數個第二導電柱。無核心層封裝結構更包含複數個導電墊。導電墊設置於封裝膠體上,並分別電性連接第一導電柱與第二導電柱。 In one or more embodiments of the present invention, the number of the first conductive pillars is plural, and the package structure includes a package body and a plurality of second conductive pillars disposed on the package body. The coreless package structure further includes a plurality of conductive pads. The conductive pads are disposed on the encapsulant and electrically connected to the first conductive pillar and the second conductive pillar, respectively.
於本發明之一或多個實施方式中,第一導電柱的數量為複數個,第一導電柱凸出於封裝膠體,封裝結構包含封裝本體與設置於封裝本體上的複數個導電墊,導電墊分別電性連接第一導電柱。 In one or more embodiments of the present invention, the number of the first conductive pillars is plural, the first conductive pillar protrudes from the package colloid, and the package structure comprises a package body and a plurality of conductive pads disposed on the package body, and is electrically conductive. The pads are electrically connected to the first conductive pillars, respectively.
本發明上述實施方式藉由將基礎線路層的線寬與線距做得較小,因而滿足半導體元件高積集度以及微型化的要求。另外,藉由設置散熱元件於晶片上,將能增強晶片的散熱能力。 The above-described embodiment of the present invention satisfies the requirements for high integration and miniaturization of semiconductor elements by making the line width and the line pitch of the basic wiring layer small. In addition, by providing a heat dissipating component on the wafer, the heat dissipation capability of the wafer can be enhanced.
100‧‧‧無核心層封裝結構 100‧‧‧No core layer package structure
110‧‧‧基礎線路層 110‧‧‧Basic circuit layer
12、13‧‧‧增層線路結構 12.13‧‧‧Additional line structure
120、130‧‧‧介電層 120, 130‧‧‧ dielectric layer
121、131‧‧‧圖案化金屬層 121, 131‧‧‧ patterned metal layer
122、132‧‧‧導電盲孔 122, 132‧‧‧ conductive blind holes
131a‧‧‧第一部分 131a‧‧‧Part I
131b‧‧‧第二部分 131b‧‧‧Part II
151‧‧‧凸塊 151‧‧‧Bumps
152‧‧‧導電柱 152‧‧‧conductive column
160‧‧‧封裝膠體 160‧‧‧Package colloid
171‧‧‧導電墊 171‧‧‧Electrical mat
191‧‧‧絕緣保護層 191‧‧‧Insulation protective layer
192‧‧‧開口 192‧‧‧ openings
193、196、197、304‧‧‧焊料球 193, 196, 197, 304‧‧‧ solder balls
194‧‧‧底膠 194‧‧‧Bottom
195‧‧‧散熱元件 195‧‧‧Heat components
198‧‧‧環形區域 198‧‧‧ring area
199‧‧‧中央區域 199‧‧‧Central area
200‧‧‧晶片 200‧‧‧ wafer
300‧‧‧封裝結構 300‧‧‧Package structure
301‧‧‧封裝本體 301‧‧‧Package body
302‧‧‧導電柱 302‧‧‧conductive column
303‧‧‧導電墊 303‧‧‧Electrical mat
400‧‧‧母板 400‧‧‧ mother board
第1圖繪示依照本發明一實施方式之無核心層封裝結構的剖面圖。 1 is a cross-sectional view showing a coreless package structure in accordance with an embodiment of the present invention.
第2圖繪示依照本發明另一實施方式之無核心層封裝結構的剖面圖。 2 is a cross-sectional view showing a coreless package structure in accordance with another embodiment of the present invention.
第3圖繪示依照本發明又一實施方式之無核心層封裝結構的剖面圖。 3 is a cross-sectional view showing a coreless package structure according to still another embodiment of the present invention.
第4圖繪示依照本發明再一實施方式之無核心層封裝結構的剖面圖。 4 is a cross-sectional view showing a coreless package structure according to still another embodiment of the present invention.
第5圖繪示依照本發明再一實施方式之無核心層封裝結構的剖面圖。 FIG. 5 is a cross-sectional view showing a coreless package structure according to still another embodiment of the present invention.
第6圖繪示依照本發明再一實施方式之無核心層封裝結構的剖面圖。 6 is a cross-sectional view showing a coreless package structure according to still another embodiment of the present invention.
以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。 The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.
本發明不同實施方式提供一種無核心層封裝結構。由於無核心層封裝基板不具有核心層,因此無核心層 封裝結構的厚度得以有效減少。本發明不同實施方式之無核心層封裝結構另外具有其他優於習知技術之優點,以下將分別一一說明。 Different embodiments of the present invention provide a coreless package structure. Since the coreless package substrate does not have a core layer, there is no core layer The thickness of the package structure is effectively reduced. The coreless package structure of the different embodiments of the present invention additionally has other advantages over the prior art, which will be separately described below.
如第1圖所繪示,無核心層封裝結構100包含 基礎線路層110、增層線路結構12、13、複數個凸塊151、晶片200、至少一導電柱152以及封裝膠體160。增層線路結構12包含設置於基礎線路層110上的介電層120、設置於介電層120上的圖案化金屬層121以及形成於介電層120中的複數個導電盲孔122。增層線路結構13包含設置於圖案化金屬層121與介電層120上的介電層130、設置於介電層130上的圖案化金屬層131以及形成於介電層130中的複數個導電盲孔132。圖案化金屬層131具有供覆晶接合之第一部分131a與供封裝堆疊之第二部分131b。導電盲孔122電性連接基礎線路層110與圖案化金屬層121,導電盲孔132電性連接圖案化金屬層121與圖案化金屬層131。凸塊151設置於第一部分131a上。晶片200設置於凸塊151上。導電柱152設置於第二部分131b上。封裝膠體160設置於增層線路結構13上,並至少部分覆蓋晶片200。 As shown in FIG. 1 , the coreless package structure 100 includes The basic circuit layer 110, the build-up wiring structures 12, 13, the plurality of bumps 151, the wafer 200, the at least one conductive pillar 152, and the encapsulant 160. The build-up line structure 12 includes a dielectric layer 120 disposed on the base layer 110, a patterned metal layer 121 disposed on the dielectric layer 120, and a plurality of conductive vias 122 formed in the dielectric layer 120. The build-up wiring structure 13 includes a dielectric layer 130 disposed on the patterned metal layer 121 and the dielectric layer 120, a patterned metal layer 131 disposed on the dielectric layer 130, and a plurality of conductive layers formed in the dielectric layer 130. Blind hole 132. The patterned metal layer 131 has a first portion 131a for flip chip bonding and a second portion 131b for package stacking. The conductive vias 122 are electrically connected to the ground trace layer 110 and the patterned metal layer 121 , and the conductive vias 132 are electrically connected to the patterned metal layer 121 and the patterned metal layer 131 . The bump 151 is disposed on the first portion 131a. The wafer 200 is disposed on the bump 151. The conductive post 152 is disposed on the second portion 131b. The encapsulant 160 is disposed on the build-up wiring structure 13 and at least partially covers the wafer 200.
基礎線路層110與圖案化金屬層121、131的線 寬與線距小於約5微米,或者基礎線路層110與圖案化金屬層121、131的線寬與線距小於約2微米。應了解到,以上所舉之基礎線路層110與圖案化金屬層121、131的具體實施方式僅為例示,並非用以限制本發明,本發明所屬技術領域中 具有通常知識者,應視實際需要,彈性選擇基礎線路層110與圖案化金屬層121、131的具體實施方式。 Line of the basic circuit layer 110 and the patterned metal layers 121, 131 The width and line spacing are less than about 5 microns, or the line width and line spacing of the base layer 110 and the patterned metal layers 121, 131 are less than about 2 microns. It should be understood that the specific embodiments of the basic circuit layer 110 and the patterned metal layers 121 and 131 are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge should flexibly select a specific embodiment of the basic circuit layer 110 and the patterned metal layers 121, 131 according to actual needs.
藉由將基礎線路層110與圖案化金屬層121、 131的線寬與線距做得較小,將能滿足半導體元件高積集度以及微型化的要求。 By the basic circuit layer 110 and the patterned metal layer 121, The line width and line spacing of 131 are made smaller, which will satisfy the requirements for high integration and miniaturization of semiconductor components.
基礎線路層110、圖案化金屬層121、131、導 電盲孔122、132、凸塊151與導電柱152之材質為銅、鎢、鋁或前述金屬之合金。應了解到,以上所舉之基礎線路層110、圖案化金屬層121、131、導電盲孔122、132、凸塊151與導電柱152之材質僅為例示,並非用以限制本發明,本發明所屬技術領域中具有通常知識者,應視實際需要,彈性選擇基礎線路層110、圖案化金屬層121、131、導電盲孔122、132、凸塊151與導電柱152之材質。 Basic circuit layer 110, patterned metal layer 121, 131, guide The material of the electric blind holes 122, 132, the bumps 151 and the conductive pillars 152 is copper, tungsten, aluminum or an alloy of the foregoing metals. It should be understood that the materials of the basic circuit layer 110, the patterned metal layers 121 and 131, the conductive blind holes 122, 132, the bumps 151 and the conductive pillars 152 are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge in the art should flexibly select the materials of the basic circuit layer 110, the patterned metal layers 121 and 131, the conductive blind holes 122, 132, the bumps 151 and the conductive pillars 152 according to actual needs.
無核心層封裝結構100更包含絕緣保護層 191。絕緣保護層191設置於介電層130與圖案化金屬層131上,以保護圖案化金屬層131。絕緣保護層191具有複數個開口192,分別裸露圖案化金屬層131的第一部分131a與第二部分131b。 The coreless package structure 100 further includes an insulating protective layer 191. The insulating protective layer 191 is disposed on the dielectric layer 130 and the patterned metal layer 131 to protect the patterned metal layer 131. The insulating protective layer 191 has a plurality of openings 192 that expose the first portion 131a and the second portion 131b of the patterned metal layer 131, respectively.
無核心層封裝結構100更包含底膠194。底膠 194設置於晶片200與絕緣保護層191之間。另外,可以在設置晶片200前先於凸塊151上形成焊料球193,之後再設置晶片200於焊料球193上。晶片200可藉由焊接等方式與凸塊151形成電性連接。於是,具體而言,封裝膠體160為設置於絕緣保護層191與底膠194上。 The coreless encapsulation structure 100 further includes a primer 194. Primer 194 is disposed between the wafer 200 and the insulating protective layer 191. In addition, the solder balls 193 may be formed on the bumps 151 before the wafers 200 are disposed, and then the wafers 200 may be disposed on the solder balls 193. The wafer 200 can be electrically connected to the bumps 151 by soldering or the like. Therefore, in particular, the encapsulant 160 is disposed on the insulating protective layer 191 and the underfill 194.
藉由形成封裝膠體160於絕緣保護層191與底 膠194上,並至少部分覆蓋晶片200。將可增加無核心層封裝結構100的結構強度,使無核心層封裝結構100更不容易因為承受外力而損壞。 Forming the encapsulant 160 on the insulating protective layer 191 and the bottom The glue 194 is over and at least partially covers the wafer 200. The structural strength of the coreless package structure 100 will be increased, making the coreless package structure 100 less susceptible to damage due to external forces.
絕緣保護層191之材質可為防焊材料或樹脂比 如環氧樹脂。應了解到,以上所舉之絕緣保護層191之材質僅為例示,並非用以限制本發明,本發明所屬技術領域中具有通常知識者,應視實際需要,彈性選擇絕緣保護層191之材質。 The material of the insulating protective layer 191 may be a solder resist material or a resin ratio Such as epoxy resin. It is to be understood that the materials of the insulating protective layer 191 are merely illustrative and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains, the material of the insulating protective layer 191 should be elastically selected according to actual needs.
封裝膠體160的高度低於導電柱152,且封 裝膠體160裸露晶片200。導電柱152為環狀結構,環狀結構圍繞形成中央區域199,封裝膠體160設置於中央區域199中。 The encapsulant 160 has a lower height than the conductive post 152 and is sealed The colloid 160 is exposed to the wafer 200. The conductive pillars 152 are annular structures, the annular structure surrounds the central region 199, and the encapsulant 160 is disposed in the central region 199.
利用導電柱152以限制封裝膠體160僅形成 於中央區域199中,將可避免封裝膠體160四處溢散的問題,同時可以減少封裝膠體160的使用量。 The conductive pillars 152 are utilized to limit the formation of the encapsulant 160 only In the central region 199, the problem of the overflow of the encapsulant 160 can be avoided, and the amount of the encapsulant 160 can be reduced.
無核心層封裝結構100更包含設置於晶片 200上的散熱元件195。因為封裝膠體160至少部分覆蓋晶片200,晶片200的散熱能力可能會因此減弱。藉由設置散熱元件195於晶片200上,將能增強晶片200的散熱能力。 The coreless package structure 100 further includes a chip disposed on the chip Heat sink element 195 on 200. Since the encapsulant 160 at least partially covers the wafer 200, the heat dissipation capability of the wafer 200 may be reduced. By providing the heat dissipating component 195 on the wafer 200, the heat dissipation capability of the wafer 200 can be enhanced.
散熱元件195為散熱鰭片。應了解到,以上 所舉之散熱元件195的具體實施方式僅為例示,並非用以限制本發明,本發明所屬技術領域中具有通常知識者,應視實際需要,彈性選擇散熱元件195的具體實施方式。 The heat dissipating component 195 is a heat dissipating fin. It should be understood that the above The specific embodiments of the heat dissipating component 195 are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge in the technical field of the present invention should flexibly select a specific embodiment of the heat dissipating component 195 according to actual needs.
介電層120、130之材質為樹脂、氧化矽或 光敏電介材料。應了解到,以上所舉之介電層120、130之材質僅為例示,並非用以限制本發明,本發明所屬技術領域中具有通常知識者,應視實際需要,彈性選擇介電層120、130之材質。 The dielectric layers 120, 130 are made of resin, yttrium oxide or Photosensitive dielectric material. It should be understood that the materials of the above-mentioned dielectric layers 120, 130 are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge in the technical field of the present invention should flexibly select the dielectric layer 120 according to actual needs. 130 material.
在本實施方式中,無核心層封裝結構100包含 增層線路結構12、13,但並不限於此。在其他實施方式中,無核心層封裝結構100可以僅具有一層增層線路結構,或者三層以上的增層線路結構。 In the present embodiment, the coreless package structure 100 includes The layer structure 12, 13 is layered, but is not limited thereto. In other embodiments, the coreless package structure 100 may have only one build-up line structure, or three or more build-up line structures.
第2圖繪示依照本發明另一實施方式之無 核心層封裝結構100的剖面圖。本實施方式的無核心層封裝結構100與第1圖的無核心層封裝結構100大致相同,以下主要描述其相異處。 2 is a diagram showing no other embodiment of the present invention. A cross-sectional view of the core layer package structure 100. The coreless layer package structure 100 of the present embodiment is substantially the same as the coreless layer package structure 100 of FIG. 1, and the differences are mainly described below.
如第2圖所繪示,封裝膠體160的高度與導 電柱152的高度相同。具體而言,在形成封裝膠體160時,首先形成高於導電柱152的封裝膠體160,且封裝膠體160覆蓋晶片200,接著再平坦化封裝膠體160,使封裝膠體160的高度與導電柱152的高度相同,並使封裝膠體160裸露晶片200。 As shown in Figure 2, the height and guide of the encapsulant 160 The height of the electric posts 152 is the same. Specifically, when the encapsulant 160 is formed, the encapsulant 160 is formed higher than the conductive pillars 152, and the encapsulant 160 covers the wafer 200, and then the encapsulant 160 is planarized to make the height of the encapsulant 160 and the conductive pillars 152. The height is the same and the encapsulant 160 is exposed to the wafer 200.
平坦化的方法可為洗床、刷磨、研磨或化學機械研磨(Chemical-Mechanical Polishing,CMP)等方法。 The method of planarization may be a method such as washing, brushing, grinding, or chemical-mechanical polishing (CMP).
第3圖繪示依照本發明又一實施方式之無核心層封裝結構100的剖面圖。本實施方式的無核心層封 裝結構100與第1圖的無核心層封裝結構100大致相同,以下主要描述其相異處。 3 is a cross-sectional view of a coreless package structure 100 in accordance with yet another embodiment of the present invention. Coreless layer seal of the present embodiment The package structure 100 is substantially the same as the coreless package structure 100 of FIG. 1, and the differences are mainly described below.
如第3圖所繪示,導電柱152的數量為複數 個,且導電柱152的設置位置定義出圍繞中央區域199的環形區域198,封裝膠體160設置於中央區域199中。 As shown in FIG. 3, the number of conductive pillars 152 is plural And the arrangement position of the conductive pillars 152 defines an annular region 198 surrounding the central region 199, and the encapsulant 160 is disposed in the central region 199.
此處需要注意的是,因為導電柱152並沒有 完全環繞中央區域199,因此會有部分的封裝膠體160透過導電柱152之間的縫隙流出中央區域199。然而,只要導電柱152的設置位置足夠密集,流出中央區域199之封裝膠體160的份量便能控制在可接受的範圍內。 It should be noted here that because the conductive posts 152 are not The central region 199 is completely surrounded, so that a portion of the encapsulant 160 exits the central region 199 through the gap between the conductive posts 152. However, as long as the placement of the conductive posts 152 is sufficiently dense, the portion of the encapsulant 160 exiting the central region 199 can be controlled to an acceptable extent.
第4圖繪示依照本發明再一實施方式之無 核心層封裝結構100的剖面圖。本實施方式的無核心層封裝結構100與第2圖的無核心層封裝結構100大致相同,以下主要描述其相異處。 FIG. 4 is a view showing still another embodiment of the present invention. A cross-sectional view of the core layer package structure 100. The coreless layer package structure 100 of the present embodiment is substantially the same as the coreless layer package structure 100 of FIG. 2, and the differences are mainly described below.
如第4圖所繪示,導電柱152的數量為複數 個,且導電柱152的設置位置定義出圍繞中央區域199的環形區域198,封裝膠體160設置於中央區域199中。 As shown in FIG. 4, the number of conductive pillars 152 is plural And the arrangement position of the conductive pillars 152 defines an annular region 198 surrounding the central region 199, and the encapsulant 160 is disposed in the central region 199.
第5圖繪示依照本發明再一實施方式之無 核心層封裝結構100的剖面圖。本實施方式的無核心層封裝結構100與第3圖的無核心層封裝結構100大致相同,以下主要描述其相異處。 Figure 5 is a diagram showing no further embodiment of the present invention. A cross-sectional view of the core layer package structure 100. The coreless layer package structure 100 of the present embodiment is substantially the same as the coreless layer package structure 100 of FIG. 3, and the differences are mainly described below.
如第5圖所繪示,無核心層封裝結構100為 設置於母板400上。無核心層封裝結構100更可包含複數個 焊料球196,基礎線路層110可藉由焊料球196電性連接母板400。 As shown in FIG. 5, the coreless package structure 100 is It is disposed on the motherboard 400. The coreless encapsulation structure 100 can further include a plurality of The solder ball 196, the base circuit layer 110 can be electrically connected to the motherboard 400 by solder balls 196.
無核心層封裝結構100更包含設置於導電 柱152上的封裝結構300。具體而言,封裝結構300包含封裝本體301與設置於封裝本體301上的複數個導電柱302。 無核心層封裝結構100更包含複數個導電墊171。導電墊171設置於封裝膠體160上,並分別電性連接導電柱152與導電柱302。無核心層封裝結構100更可包含複數個焊料球197,導電墊171藉由焊料球197電性連接導電柱302。 The coreless package structure 100 further includes a conductive layer The package structure 300 on the pillars 152. Specifically, the package structure 300 includes a package body 301 and a plurality of conductive pillars 302 disposed on the package body 301. The coreless package structure 100 further includes a plurality of conductive pads 171. The conductive pads 171 are disposed on the encapsulant 160 and electrically connected to the conductive pillars 152 and the conductive pillars 302, respectively. The coreless package structure 100 further includes a plurality of solder balls 197 electrically connected to the conductive pillars 302 by solder balls 197.
於是,無核心層封裝結構100成為堆疊式封裝 (Package on Package,PoP)結構,因而得以提升無核心層封裝結構100的元件密度。 Thus, the coreless package structure 100 becomes a stacked package The (Package on Package, PoP) structure, thereby increasing the component density of the coreless package structure 100.
在其他實施方式中,封裝結構300亦可為晶片。 In other embodiments, the package structure 300 can also be a wafer.
另外,如第5圖所繪示,封裝膠體160圍繞導電柱152。由於導電柱152電性連接封裝結構300,藉由將封裝膠體160圍繞導電柱152,將可增加不同導電柱152之間的電阻,因而避免不同導電柱152互相電性導通而短路的問題。 In addition, as illustrated in FIG. 5, the encapsulant 160 surrounds the conductive pillars 152. Since the conductive pillars 152 are electrically connected to the package structure 300, by enclosing the encapsulant 160 around the conductive pillars 152, the electrical resistance between the different conductive pillars 152 can be increased, thereby avoiding the problem that the different conductive pillars 152 are electrically connected to each other and short-circuited.
第6圖繪示依照本發明再一實施方式之無核心層封裝結構100的剖面圖。本實施方式的無核心層封裝結構100與第5圖的無核心層封裝結構100大致相同,以下主要描述其相異處。 FIG. 6 is a cross-sectional view showing a coreless package structure 100 in accordance with still another embodiment of the present invention. The coreless layer package structure 100 of the present embodiment is substantially the same as the coreless layer package structure 100 of FIG. 5, and the differences are mainly described below.
如第6圖所繪示,導電柱152凸出於封裝膠 體160。封裝結構300包含封裝本體301與設置於封裝本體301上的複數個導電墊303,導電墊303分別電性連接導電柱152。封裝結構300更可包含複數個焊料球304,導電墊303藉由焊料球304電性連接導電柱152。 As shown in FIG. 6, the conductive post 152 protrudes from the encapsulant Body 160. The package structure 300 includes a package body 301 and a plurality of conductive pads 303 disposed on the package body 301. The conductive pads 303 are electrically connected to the conductive posts 152, respectively. The package structure 300 further includes a plurality of solder balls 304 electrically connected to the conductive pillars 152 by solder balls 304.
本發明上述實施方式藉由將基礎線路層110 與圖案化金屬層121、131的線寬與線距做得較小,因而滿足半導體元件高積集度以及微型化的要求。另外,藉由設置散熱元件195於晶片200上,將能增強晶片200的散熱能力。 The above embodiment of the present invention by the basic circuit layer 110 The line width and the line pitch of the patterned metal layers 121 and 131 are made smaller, and thus the requirements for high integration and miniaturization of the semiconductor element are satisfied. In addition, by providing the heat dissipating component 195 on the wafer 200, the heat dissipation capability of the wafer 200 can be enhanced.
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.
100‧‧‧無核心層封裝結構 100‧‧‧No core layer package structure
110‧‧‧基礎線路層 110‧‧‧Basic circuit layer
12、13‧‧‧增層線路結構 12.13‧‧‧Additional line structure
120、130‧‧‧介電層 120, 130‧‧‧ dielectric layer
121、131‧‧‧圖案化金屬層 121, 131‧‧‧ patterned metal layer
122、132‧‧‧導電盲孔 122, 132‧‧‧ conductive blind holes
131a‧‧‧第一部分 131a‧‧‧Part I
131b‧‧‧第二部分 131b‧‧‧Part II
151‧‧‧凸塊 151‧‧‧Bumps
152‧‧‧導電柱 152‧‧‧conductive column
160‧‧‧封裝膠體 160‧‧‧Package colloid
191‧‧‧絕緣保護層 191‧‧‧Insulation protective layer
192‧‧‧開口 192‧‧‧ openings
193‧‧‧焊料球 193‧‧‧ solder balls
194‧‧‧底膠 194‧‧‧Bottom
195‧‧‧散熱元件 195‧‧‧Heat components
199‧‧‧中央區域 199‧‧‧Central area
200‧‧‧晶片 200‧‧‧ wafer
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