TWI576976B - Coreless package structure - Google Patents

Description

Coreless package structure

The present invention relates to a coreless package structure.

With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the requirements of high integration and miniaturization of semiconductor components, the requirements for semiconductor package structures are becoming higher and higher. For example, in the package structure, the critical dimension of the line width and the line pitch of the package substrate is required to be smaller and smaller, and the overall thickness of the package structure is required to be as small as possible.

The conventional semiconductor package structure is to adhere a semiconductor wafer to the top surface of the substrate for wire bonding or Flip Chip packaging. The flip chip technology is characterized in that the electrical connection between the semiconductor wafer and the package substrate is directly solder bump instead of the general gold wire. The advantage of the flip chip technology is that the electrical contact density can be improved and the package can be reduced. Component size; at the same time, this kind of flip chip technology does not need to use a long length of gold wire, but can reduce impedance and noise, improve electrical performance to meet the needs of high-frequency signal transmission.

In order to further improve the various features of the semiconductor package structure Sex, related fields do not bother to develop. How to provide a semiconductor package structure with better characteristics is one of the current important research and development topics, and it has become an urgent need for improvement in related fields.

One aspect of the present invention provides a coreless package structure to reduce the line width and line spacing of the lines, and to combine heat dissipating components to increase heat dissipation capability.

According to an embodiment of the invention, a coreless package structure includes a base circuit layer, a build-up line structure, a plurality of bumps, a wafer, at least one first conductive pillar, and an encapsulant. The build-up line structure comprises a dielectric layer disposed on the base circuit layer, a patterned metal layer disposed on the dielectric layer, and a plurality of conductive blind vias formed in the dielectric layer, and a line width and a line pitch of the base circuit layer Less than about 5 microns, the patterned metal layer has a first portion for flip chip bonding and a second portion for the package stack, the conductive vias electrically connecting the base circuit layer and the patterned metal layer. The bump is disposed on the first portion. The wafer is disposed on the bump. The first conductive pillar is disposed on the second portion. The encapsulant is disposed on the build-up wiring structure and at least partially covers the wafer.

In one or more embodiments of the invention, the line width and line pitch of the base layer are less than about 2 microns.

In one or more embodiments of the present invention, the first conductive pillar is a ring structure, the annular structure surrounds the central region, and the encapsulant is disposed in the central region.

In one or more embodiments of the present invention, the number of the first conductive pillars is plural, and the disposed position of the first conductive pillar defines an annular region surrounding the central region, and the encapsulant is disposed in the central region.

In one or more embodiments of the present invention, the coreless package structure further includes a heat dissipating component disposed on the wafer.

In one or more embodiments of the present invention, the coreless package structure further includes a package structure disposed on the first conductive pillar.

In one or more embodiments of the invention, the encapsulant surrounds the first conductive pillar.

In one or more embodiments of the present invention, the number of the first conductive pillars is plural, and the package structure includes a package body and a plurality of second conductive pillars disposed on the package body. The coreless package structure further includes a plurality of conductive pads. The conductive pads are disposed on the encapsulant and electrically connected to the first conductive pillar and the second conductive pillar, respectively.

In one or more embodiments of the present invention, the number of the first conductive pillars is plural, the first conductive pillar protrudes from the package colloid, and the package structure comprises a package body and a plurality of conductive pads disposed on the package body, and is electrically conductive. The pads are electrically connected to the first conductive pillars, respectively.

The above-described embodiment of the present invention satisfies the requirements for high integration and miniaturization of semiconductor elements by making the line width and the line pitch of the basic wiring layer small. In addition, by providing a heat dissipating component on the wafer, the heat dissipation capability of the wafer can be enhanced.

100‧‧‧No core layer package structure

110‧‧‧Basic circuit layer

12.13‧‧‧Additional line structure

120, 130‧‧‧ dielectric layer

121, 131‧‧‧ patterned metal layer

122, 132‧‧‧ conductive blind holes

131a‧‧‧Part I

131b‧‧‧Part II

151‧‧‧Bumps

152‧‧‧conductive column

160‧‧‧Package colloid

171‧‧‧Electrical mat

191‧‧‧Insulation protective layer

192‧‧‧ openings

193, 196, 197, 304‧‧‧ solder balls

194‧‧‧Bottom

195‧‧‧Heat components

198‧‧‧ring area

199‧‧‧Central area

200‧‧‧ wafer

300‧‧‧Package structure

301‧‧‧Package body

302‧‧‧conductive column

303‧‧‧Electrical mat

400‧‧‧ mother board

1 is a cross-sectional view showing a coreless package structure in accordance with an embodiment of the present invention.

2 is a cross-sectional view showing a coreless package structure in accordance with another embodiment of the present invention.

3 is a cross-sectional view showing a coreless package structure according to still another embodiment of the present invention.

4 is a cross-sectional view showing a coreless package structure according to still another embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a coreless package structure according to still another embodiment of the present invention.

6 is a cross-sectional view showing a coreless package structure according to still another embodiment of the present invention.

The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

Different embodiments of the present invention provide a coreless package structure. Since the coreless package substrate does not have a core layer, there is no core layer The thickness of the package structure is effectively reduced. The coreless package structure of the different embodiments of the present invention additionally has other advantages over the prior art, which will be separately described below.

As shown in FIG. 1 , the coreless package structure 100 includes The basic circuit layer 110, the build-up wiring structures 12, 13, the plurality of bumps 151, the wafer 200, the at least one conductive pillar 152, and the encapsulant 160. The build-up line structure 12 includes a dielectric layer 120 disposed on the base layer 110, a patterned metal layer 121 disposed on the dielectric layer 120, and a plurality of conductive vias 122 formed in the dielectric layer 120. The build-up wiring structure 13 includes a dielectric layer 130 disposed on the patterned metal layer 121 and the dielectric layer 120, a patterned metal layer 131 disposed on the dielectric layer 130, and a plurality of conductive layers formed in the dielectric layer 130. Blind hole 132. The patterned metal layer 131 has a first portion 131a for flip chip bonding and a second portion 131b for package stacking. The conductive vias 122 are electrically connected to the ground trace layer 110 and the patterned metal layer 121 , and the conductive vias 132 are electrically connected to the patterned metal layer 121 and the patterned metal layer 131 . The bump 151 is disposed on the first portion 131a. The wafer 200 is disposed on the bump 151. The conductive post 152 is disposed on the second portion 131b. The encapsulant 160 is disposed on the build-up wiring structure 13 and at least partially covers the wafer 200.

Line of the basic circuit layer 110 and the patterned metal layers 121, 131 The width and line spacing are less than about 5 microns, or the line width and line spacing of the base layer 110 and the patterned metal layers 121, 131 are less than about 2 microns. It should be understood that the specific embodiments of the basic circuit layer 110 and the patterned metal layers 121 and 131 are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge should flexibly select a specific embodiment of the basic circuit layer 110 and the patterned metal layers 121, 131 according to actual needs.

By the basic circuit layer 110 and the patterned metal layer 121, The line width and line spacing of 131 are made smaller, which will satisfy the requirements for high integration and miniaturization of semiconductor components.

Basic circuit layer 110, patterned metal layer 121, 131, guide The material of the electric blind holes 122, 132, the bumps 151 and the conductive pillars 152 is copper, tungsten, aluminum or an alloy of the foregoing metals. It should be understood that the materials of the basic circuit layer 110, the patterned metal layers 121 and 131, the conductive blind holes 122, 132, the bumps 151 and the conductive pillars 152 are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge in the art should flexibly select the materials of the basic circuit layer 110, the patterned metal layers 121 and 131, the conductive blind holes 122, 132, the bumps 151 and the conductive pillars 152 according to actual needs.

The coreless package structure 100 further includes an insulating protective layer 191. The insulating protective layer 191 is disposed on the dielectric layer 130 and the patterned metal layer 131 to protect the patterned metal layer 131. The insulating protective layer 191 has a plurality of openings 192 that expose the first portion 131a and the second portion 131b of the patterned metal layer 131, respectively.

The coreless encapsulation structure 100 further includes a primer 194. Primer 194 is disposed between the wafer 200 and the insulating protective layer 191. In addition, the solder balls 193 may be formed on the bumps 151 before the wafers 200 are disposed, and then the wafers 200 may be disposed on the solder balls 193. The wafer 200 can be electrically connected to the bumps 151 by soldering or the like. Therefore, in particular, the encapsulant 160 is disposed on the insulating protective layer 191 and the underfill 194.

Forming the encapsulant 160 on the insulating protective layer 191 and the bottom The glue 194 is over and at least partially covers the wafer 200. The structural strength of the coreless package structure 100 will be increased, making the coreless package structure 100 less susceptible to damage due to external forces.

The material of the insulating protective layer 191 may be a solder resist material or a resin ratio Such as epoxy resin. It is to be understood that the materials of the insulating protective layer 191 are merely illustrative and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains, the material of the insulating protective layer 191 should be elastically selected according to actual needs.

The encapsulant 160 has a lower height than the conductive post 152 and is sealed The colloid 160 is exposed to the wafer 200. The conductive pillars 152 are annular structures, the annular structure surrounds the central region 199, and the encapsulant 160 is disposed in the central region 199.

The conductive pillars 152 are utilized to limit the formation of the encapsulant 160 only In the central region 199, the problem of the overflow of the encapsulant 160 can be avoided, and the amount of the encapsulant 160 can be reduced.

The coreless package structure 100 further includes a chip disposed on the chip Heat sink element 195 on 200. Since the encapsulant 160 at least partially covers the wafer 200, the heat dissipation capability of the wafer 200 may be reduced. By providing the heat dissipating component 195 on the wafer 200, the heat dissipation capability of the wafer 200 can be enhanced.

The heat dissipating component 195 is a heat dissipating fin. It should be understood that the above The specific embodiments of the heat dissipating component 195 are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge in the technical field of the present invention should flexibly select a specific embodiment of the heat dissipating component 195 according to actual needs.

The dielectric layers 120, 130 are made of resin, yttrium oxide or Photosensitive dielectric material. It should be understood that the materials of the above-mentioned dielectric layers 120, 130 are merely illustrative and are not intended to limit the present invention. Those having ordinary knowledge in the technical field of the present invention should flexibly select the dielectric layer 120 according to actual needs. 130 material.

In the present embodiment, the coreless package structure 100 includes The layer structure 12, 13 is layered, but is not limited thereto. In other embodiments, the coreless package structure 100 may have only one build-up line structure, or three or more build-up line structures.

2 is a diagram showing no other embodiment of the present invention. A cross-sectional view of the core layer package structure 100. The coreless layer package structure 100 of the present embodiment is substantially the same as the coreless layer package structure 100 of FIG. 1, and the differences are mainly described below.

As shown in Figure 2, the height and guide of the encapsulant 160 The height of the electric posts 152 is the same. Specifically, when the encapsulant 160 is formed, the encapsulant 160 is formed higher than the conductive pillars 152, and the encapsulant 160 covers the wafer 200, and then the encapsulant 160 is planarized to make the height of the encapsulant 160 and the conductive pillars 152. The height is the same and the encapsulant 160 is exposed to the wafer 200.

The method of planarization may be a method such as washing, brushing, grinding, or chemical-mechanical polishing (CMP).

3 is a cross-sectional view of a coreless package structure 100 in accordance with yet another embodiment of the present invention. Coreless layer seal of the present embodiment The package structure 100 is substantially the same as the coreless package structure 100 of FIG. 1, and the differences are mainly described below.

As shown in FIG. 3, the number of conductive pillars 152 is plural And the arrangement position of the conductive pillars 152 defines an annular region 198 surrounding the central region 199, and the encapsulant 160 is disposed in the central region 199.

It should be noted here that because the conductive posts 152 are not The central region 199 is completely surrounded, so that a portion of the encapsulant 160 exits the central region 199 through the gap between the conductive posts 152. However, as long as the placement of the conductive posts 152 is sufficiently dense, the portion of the encapsulant 160 exiting the central region 199 can be controlled to an acceptable extent.

FIG. 4 is a view showing still another embodiment of the present invention. A cross-sectional view of the core layer package structure 100. The coreless layer package structure 100 of the present embodiment is substantially the same as the coreless layer package structure 100 of FIG. 2, and the differences are mainly described below.

As shown in FIG. 4, the number of conductive pillars 152 is plural And the arrangement position of the conductive pillars 152 defines an annular region 198 surrounding the central region 199, and the encapsulant 160 is disposed in the central region 199.

Figure 5 is a diagram showing no further embodiment of the present invention. A cross-sectional view of the core layer package structure 100. The coreless layer package structure 100 of the present embodiment is substantially the same as the coreless layer package structure 100 of FIG. 3, and the differences are mainly described below.

As shown in FIG. 5, the coreless package structure 100 is It is disposed on the motherboard 400. The coreless encapsulation structure 100 can further include a plurality of The solder ball 196, the base circuit layer 110 can be electrically connected to the motherboard 400 by solder balls 196.

The coreless package structure 100 further includes a conductive layer The package structure 300 on the pillars 152. Specifically, the package structure 300 includes a package body 301 and a plurality of conductive pillars 302 disposed on the package body 301. The coreless package structure 100 further includes a plurality of conductive pads 171. The conductive pads 171 are disposed on the encapsulant 160 and electrically connected to the conductive pillars 152 and the conductive pillars 302, respectively. The coreless package structure 100 further includes a plurality of solder balls 197 electrically connected to the conductive pillars 302 by solder balls 197.

Thus, the coreless package structure 100 becomes a stacked package The (Package on Package, PoP) structure, thereby increasing the component density of the coreless package structure 100.

In other embodiments, the package structure 300 can also be a wafer.

In addition, as illustrated in FIG. 5, the encapsulant 160 surrounds the conductive pillars 152. Since the conductive pillars 152 are electrically connected to the package structure 300, by enclosing the encapsulant 160 around the conductive pillars 152, the electrical resistance between the different conductive pillars 152 can be increased, thereby avoiding the problem that the different conductive pillars 152 are electrically connected to each other and short-circuited.

FIG. 6 is a cross-sectional view showing a coreless package structure 100 in accordance with still another embodiment of the present invention. The coreless layer package structure 100 of the present embodiment is substantially the same as the coreless layer package structure 100 of FIG. 5, and the differences are mainly described below.

As shown in FIG. 6, the conductive post 152 protrudes from the encapsulant Body 160. The package structure 300 includes a package body 301 and a plurality of conductive pads 303 disposed on the package body 301. The conductive pads 303 are electrically connected to the conductive posts 152, respectively. The package structure 300 further includes a plurality of solder balls 304 electrically connected to the conductive pillars 152 by solder balls 304.

The above embodiment of the present invention by the basic circuit layer 110 The line width and the line pitch of the patterned metal layers 121 and 131 are made smaller, and thus the requirements for high integration and miniaturization of the semiconductor element are satisfied. In addition, by providing the heat dissipating component 195 on the wafer 200, the heat dissipation capability of the wafer 200 can be enhanced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧No core layer package structure

110‧‧‧Basic circuit layer

12.13‧‧‧Additional line structure

120, 130‧‧‧ dielectric layer

121, 131‧‧‧ patterned metal layer

122, 132‧‧‧ conductive blind holes

131a‧‧‧Part I

131b‧‧‧Part II

151‧‧‧Bumps

152‧‧‧conductive column

160‧‧‧Package colloid

191‧‧‧Insulation protective layer

192‧‧‧ openings

193‧‧‧ solder balls

194‧‧‧Bottom

195‧‧‧Heat components

199‧‧‧Central area

200‧‧‧ wafer

Claims (9)

A coreless package structure comprising: a base circuit layer; a build-up line structure, wherein the build-up line structure comprises a dielectric layer disposed on the base circuit layer, and a pattern disposed on the dielectric layer And a plurality of conductive blind vias formed in the dielectric layer, the base wiring layer having a line width and a line pitch of less than about 5 microns, the patterned metal layer having a first portion for the flip chip bonding and a supply a second portion of the package, the conductive vias are electrically connected to the base layer and the patterned metal layer; a plurality of bumps are disposed on the first portion; and a wafer is disposed on the bumps; a first conductive pillar disposed on the second portion; and an encapsulant disposed on the build-up wiring structure and at least partially covering the wafer. The coreless package structure of claim 1, wherein the base line layer has a line width and line spacing of less than about 2 microns. The coreless encapsulation structure of claim 1, wherein the first conductive pillar is a ring structure, and the annular structure surrounds a central region, and the encapsulant is disposed in the central region. The coreless encapsulation structure of claim 1, wherein the number of the at least one first conductive pillar is plural, and the first The position of the conductive post defines an annular region surrounding a central region in which the encapsulant is disposed. The coreless package structure of claim 1, further comprising: a heat dissipating component disposed on the wafer. The coreless package structure of claim 1, further comprising: a package structure disposed on the first conductive pillar. The coreless package structure of claim 6, wherein the encapsulant surrounds the first conductive pillar. The coreless encapsulation structure of claim 7, wherein the number of the at least one first conductive pillar is plural, and the package structure comprises a package body and a plurality of second conductive pillars disposed on the package body; The method further includes: a plurality of conductive pads disposed on the encapsulant and electrically connecting the first conductive pillars and the second conductive pillars respectively. The coreless encapsulation structure of claim 7, wherein the number of the at least one first conductive pillar is plural, the first conductive pillars are protruded from the encapsulant, and the encapsulation structure comprises a package body and And a plurality of conductive pads disposed on the package body, the conductive pads being electrically connected to the first conductive pillars respectively.