JPWO2005101476A1 - Semiconductor element and method of manufacturing semiconductor element - Google Patents

Semiconductor element and method of manufacturing semiconductor element Download PDF

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JPWO2005101476A1
JPWO2005101476A1 JP2006512396A JP2006512396A JPWO2005101476A1 JP WO2005101476 A1 JPWO2005101476 A1 JP WO2005101476A1 JP 2006512396 A JP2006512396 A JP 2006512396A JP 2006512396 A JP2006512396 A JP 2006512396A JP WO2005101476 A1 JPWO2005101476 A1 JP WO2005101476A1
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electrode
semiconductor
semiconductor substrate
semiconductor element
substrate
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洋 川本
洋 川本
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Japan Science and Technology Agency
National Institute of Japan Science and Technology Agency
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Abstract

【課題】 従来の貫通電極の構造を変えることにより、製造時間を短縮すると共に、歩留まり、コスト及び信頼性を改善し、半導体素子内のスペースを有効活用してチップ自体を小型にし、高速動作が可能な半導体素子を提供する。
【解決手段】 単結晶半導体基板１の表面から裏面までを貫通した貫通電極３１、３２が形成され、当該貫通電極３１、３２が半導体基板表面より上層の多層金属配線層に到達せずに形成されているので、容易な構成で製造時間を短縮し、歩留まり、コスト及び信頼性を改善すると共に、半導体基板１の表面以上の上層部分のうち貫通電極の直上部分を有効に使用することができる。
【選択図】 図１PROBLEM TO BE SOLVED: To shorten the manufacturing time by improving the structure of a conventional through electrode, improve the yield, cost and reliability, effectively utilize the space in a semiconductor element to miniaturize the chip itself, and achieve high-speed operation. A possible semiconductor device is provided.
Through electrodes 31, 32 penetrating from the front surface to the back surface of a single crystal semiconductor substrate 1 are formed, and the through electrodes 31, 32 are formed without reaching a multilayer metal wiring layer above the surface of the semiconductor substrate. Therefore, the manufacturing time can be shortened with a simple structure, the yield, the cost and the reliability can be improved, and the portion directly above the through electrode in the upper layer portion above the surface of the semiconductor substrate 1 can be effectively used.
[Selection diagram]

Description

本発明は、半導体素子の貫通電極に関し、特に、かかる貫通電極の構造及びその製造方法に関する。   The present invention relates to a through electrode of a semiconductor device, and more particularly to a structure of such a through electrode and a manufacturing method thereof.

背景技術となる従来の貫通電極を有する半導体基板は、基板表面プロセスが完成した後（多層金属配線層８の加工後）に表面から深孔を半導体基板表面に堆積させた絶縁物９を貫通し更に半導体基板１まで貫通するように開口し、開口して形成された孔周り（半導体素子の貫通電極孔部分の内壁）に酸化膜６（熱酸化、絶縁物デポ）を形成後、孔の中に金属７（銅等）をメッキプロセス等で埋め込み、表面に付着した埋め込み金属除去後、追加絶縁膜１２を形成、加工し、その上に追加金属配線１４を堆積、加工し、貫通電極金属７とボンヂングパット１１を結線、その上に追加保護絶縁膜１３を形成、加工することにより、半導体基板１の表面と裏面を結線する（図１３を参照）。   A conventional semiconductor substrate having a through electrode, which is a background art, penetrates an insulator 9 having deep holes deposited on the surface of the semiconductor substrate from the surface after the substrate surface process is completed (after processing the multilayer metal wiring layer 8). Further, an opening is formed so as to penetrate to the semiconductor substrate 1, and an oxide film 6 (thermal oxidation, an insulator depot) is formed around the hole formed by the opening (inner wall of the through electrode hole portion of the semiconductor element). The metal 7 (copper or the like) is embedded in the surface by a plating process or the like, the embedded metal adhered to the surface is removed, and then the additional insulating film 12 is formed and processed, and the additional metal wiring 14 is deposited and processed thereon, and the through electrode metal 7 And the bonding pad 11 are connected, and an additional protective insulating film 13 is formed and processed thereon to connect the front surface and the back surface of the semiconductor substrate 1 (see FIG. 13).

図１３に記載されたその他の項目を以下に説明する。半導体基板１（例としてSi単結晶でP型とする）の表面上にトランジスター（以下Tr.とする）２が形成され、そのTr.２は、高融点金属材料（ポリシリコン等）のケ゛ート３と、半導体基板１と逆型（半導体基板１の例としてP型としたのでN型）の高濃度拡散層４で形成されたソース、ドレインとで構成される。半導体基板１上には複数層の金属配線層８を持ち、使用される金属材料は、ゲートと同じ高融点金属材料の高融点金属配線５、低抵抗の金属配線（Al、Cu等）等が積層構造になっている。これ等の配線層間を絶縁する絶縁膜９が金属配線層８間に形成されており、この絶縁膜９の材料はSiO2が使われる場合が多い（その他金属酸化膜、有機材料でもできる）。信号の取り出し・入力は、表面の取り出し電極１５、及び裏面からは裏面絶縁膜１６を開口して貫通電極との間に裏面取り出し電極金属を形成して行う。   The other items described in FIG. 13 will be described below. A transistor (hereinafter referred to as Tr.) 2 is formed on the surface of a semiconductor substrate 1 (for example, Si single crystal of P type), and the Tr. 2 is a gate 3 of a refractory metal material (polysilicon or the like). And a source and a drain formed of the high-concentration diffusion layer 4 of the opposite type to the semiconductor substrate 1 (N-type because the semiconductor substrate 1 is P-type). The semiconductor substrate 1 has a plurality of metal wiring layers 8, and the metal materials used include a high melting point metal wiring 5 of the same high melting point metal material as that of the gate, a low resistance metal wiring (Al, Cu, etc.). It has a laminated structure. An insulating film 9 that insulates these wiring layers is formed between the metal wiring layers 8, and SiO2 is often used as the material of the insulating film 9 (other metal oxide films or organic materials can also be used). The extraction and input of a signal is performed by opening the extraction electrode 15 on the front surface and the back surface insulating film 16 from the back surface, and forming a back extraction electrode metal between the through electrode and the through electrode.

図１４に従来の高速CPU等の半導体素子の組み立て実装構造を示す。半導体素子２２は半導体表面２５（図では下面）のボンヂングパッド１１に取り付けられた金属バンプ２１を介してパッケージ２０と繋がれており、パッケージ２０は半田バンプ１９によってボード１８に繋がれている。半導体裏面２４はパッケージの放熱板２３に（直接又は有機材等の接着剤を通して）接している。   FIG. 14 shows an assembled mounting structure of a semiconductor element such as a conventional high-speed CPU. The semiconductor element 22 is connected to the package 20 via the metal bumps 21 attached to the bonding pads 11 on the semiconductor surface 25 (the lower surface in the figure), and the package 20 is connected to the board 18 by the solder bumps 19. The semiconductor back surface 24 is in contact with the heat sink 23 of the package (directly or through an adhesive such as an organic material).

図１５に従来の半導体センサー（CCD、MOS等）等の半導体素子の組み立て実装構造を示す。半導体素子２２は半導体表面２５（図では上面）のボンヂングパッド１１からボンヂングワイア２６で電気信号がパッケージ２０上に取り出され、半導体裏面（図では下面）はパッケージ２０に機械的に貼り付けられている。この半導体センサーが光を受光する場合、光源２８からレンズ２９を通してパッケージ２０表面の透過材料２７を通して半導体表面の受光部に達する。
富坂学、「３次元実装に用いるチップ管通電極形成技術」、デンソーテクニカルレビュー、２００１、Vol．６、No．２、ｐ７８〜８３ 白井 優之、「SIPソリューションとしての三次元積層LSI」、２００３年電子情報通信学会エレクトロニクスソサイエティ大会、２００３、SS−１６〜SS−１７ 特開２００２−２３７４６８号公報 FIG. 15 shows an assembled mounting structure of a semiconductor element such as a conventional semiconductor sensor (CCD, MOS, etc.). In the semiconductor element 22, an electrical signal is taken out from the bonding pad 11 on the semiconductor surface 25 (upper surface in the drawing) to the package 20 by the bonding wire 26, and the back surface of the semiconductor (lower surface in the drawing) is mechanically attached to the package 20. .. When the semiconductor sensor receives light, it reaches the light receiving portion on the semiconductor surface through the lens 29 and the transparent material 27 on the surface of the package 20 from the light source 28.
Tomisaka Manabu, “Technology for forming chip tube through electrodes used for three-dimensional mounting”, Denso Technical Review, 2001, Vol. 6, No. 2, p78-83 Yoshiyuki Shirai, "Three-dimensional Stacked LSI as SIP Solution", 2003 IEICE Electronics Society Conference, 2003, SS-16 to SS-17 JP, 2002-237468, A

従来構造の貫通電極半導体素子では、多層配線プロセス完成後に貫通電極孔を開口しており、基板Si貫通電極回りに基板−貫通電極間の絶縁膜６を形成するには、熱酸化（１０００度Ｃ以上）が出来ない。その理由は多層配線金属（Al、Cu等）の融点が低い（１０００度Ｃ以下）からである。従って、絶縁膜６にはデポジション等のプロセスを使用せざる得なく、絶縁膜６の膜質が悪くて歩留まり低下、コスト上昇、信頼度劣化の問題点が山積しているという課題を有する。また、従来の貫通電極孔開口エッチングプロセス工程では、基板表面に積層された厚い絶縁膜９（SiO2）を開口してその下の半導体基板１も開口エッチングする必要があった。エッチング時、絶縁膜９のエッチングレートと半導体基板１のエッチングレートが異なるために、エッチング側面形状が悪くなったり、孔径や深さの制御が大変難しくなり、歩留まり低下の原因となっているという課題を有する。また、従来の貫通電極半導体素子では、深孔への貫通電極金属７（Cu）の融点が低いため、基板表面の結線金属形成後の孔開口プロセスとなるため、貫通電極部は他の配線領域として使えないデッドスペースとなり、チップ面積が必要以上に大きくなって肥大するという課題を有する。また、従来の貫通電極半導体素子では、貫通電極の基板表面側からの取り出し口が表面最上層となり、基板上の配線、トランジスタ（Tr.）２への接続距離が長くなり、高速動作の妨げとなるという課題を有する。また、従来の貫通電極半導体素子では、貫通電極の基板表面側からの取り出し口を形成するために、新たに追加金属配線１４、追加絶縁膜１２及び追加保護絶縁膜１３の形成プロセスが追加で必要となり、製造工程が長くなると共に、歩留まり低下、コスト上昇及び信頼度劣化等の問題が生じているという課題を有する。また、従来の貫通電極半導体素子では、深孔開口プロセス及び孔への金属埋め込みメッキプロセスがあるため、孔の大きさ、形状は同じである必要が有り、断面積が異なったり、形状が異なったりした貫通電極を同時に形成することができなかったという課題を有する。また、従来の貫通電極半導体素子の組み立て実装方法では、半導体素子表面２５から電極を取り出すために、放熱板とは半導体素子裏面２４としか接着できず、熱放熱の効率が著しく悪いという課題を有する。また、従来の貫通電極半導体素子の組み立て実装方法では、MOS（Metal Oxide Semiconductor）、CCD（Charge Coupled Devices）のような光センサー半導体素子では、電気信号をやり取りする電極は、半導体素子表面２５のボンヂングパッドからボンヂングワイヤ２６を介する以外無かった。したがって、かかるボンヂングワイヤ２６の高さが弊害となって光センサー半導体素子の受光面とレンズ２９との間隔を短くできずに、焦点深度を浅くすることができないという課題を有する。   In the through-electrode semiconductor element having the conventional structure, the through-electrode hole is opened after the completion of the multi-layer wiring process. To form the insulating film 6 between the substrate and the through-electrode around the substrate Si through-electrode, thermal oxidation (1000° C. Above) is not possible. The reason is that the melting point of the multilayer wiring metal (Al, Cu, etc.) is low (1000° C. or less). Therefore, there is no choice but to use a process such as deposition for the insulating film 6, and there are problems that the film quality of the insulating film 6 is poor and the yield, the cost, and the reliability deteriorate. Further, in the conventional through electrode hole opening etching process step, it is necessary to open the thick insulating film 9 (SiO2) laminated on the surface of the substrate and open the semiconductor substrate 1 thereunder. At the time of etching, since the etching rate of the insulating film 9 and the etching rate of the semiconductor substrate 1 are different from each other, the shape of the side surface of the etching is deteriorated, and it becomes very difficult to control the hole diameter and the depth, which causes a decrease in yield. Have. Further, in the conventional through electrode semiconductor element, since the melting point of the through electrode metal 7 (Cu) into the deep hole is low, the hole opening process is performed after the connection metal is formed on the substrate surface. It becomes a dead space that cannot be used as a chip, and has a problem that the chip area becomes larger than necessary and enlarges. Further, in the conventional through electrode semiconductor element, the take-out electrode from the substrate surface side is the uppermost surface layer, and the wiring on the substrate and the connection distance to the transistor (Tr.) 2 become long, which hinders high-speed operation. Has the problem of becoming. In addition, in the conventional through electrode semiconductor element, in order to form an opening for taking out the through electrode from the substrate surface side, an additional forming process of the additional metal wiring 14, the additional insulating film 12, and the additional protective insulating film 13 is additionally required. Therefore, there is a problem that the manufacturing process becomes long and there are problems such as a decrease in yield, an increase in cost, and deterioration of reliability. Further, in the conventional through electrode semiconductor element, since there is a deep hole opening process and a metal burying plating process in the hole, it is necessary that the size and shape of the hole are the same, and the cross-sectional area is different or the shape is different. However, there is a problem that the through electrodes cannot be simultaneously formed. Further, in the conventional method of assembling and mounting a through electrode semiconductor element, since the electrodes are taken out from the semiconductor element front surface 25, the heat radiating plate can be bonded only to the semiconductor element rear surface 24, and there is a problem that the efficiency of heat radiation is extremely poor. .. Further, in the conventional method of assembling and mounting a through electrode semiconductor element, in an optical sensor semiconductor element such as a MOS (Metal Oxide Semiconductor) or a CCD (Charge Coupled Devices), an electrode for exchanging an electrical signal is a bond on the surface 25 of the semiconductor element. There was nothing other than through the bonding wire 26 from the bonding pad. Therefore, there is a problem that the height of the bonding wire 26 becomes an adverse effect and the distance between the light receiving surface of the optical sensor semiconductor element and the lens 29 cannot be shortened, and the depth of focus cannot be made shallow.

本発明は前記課題を解決するためになされたものであり、従来の貫通電極の構造を変えることにより、製造時間を短縮すると共に、歩留まり、コスト及び信頼性を改善し、半導体素子内のスペースを有効活用してチップ自体を小型にし、高速動作が可能な半導体素子を提供することを目的とする。   The present invention has been made to solve the above problems, by changing the structure of the conventional through electrode, while shortening the manufacturing time, improve the yield, cost and reliability, the space in the semiconductor element It is an object of the present invention to provide a semiconductor element that can be operated at high speed by effectively utilizing it to reduce the size of the chip itself.

本発明に係る半導体素子は、単結晶半導体基板の表面から裏面までを貫通した貫通電極が形成され、当該貫通電極が半導体基板表面より上層の多層金属配線層に到達せずに形成されているものである。このように本発明においては、単結晶半導体基板の表面から裏面までを貫通した貫通電極が形成され、当該貫通電極が半導体基板表面より上層の多層金属配線層に到達せずに形成されているので、容易な構成で製造時間を短縮し、歩留まり、コスト及び信頼性を改善すると共に、半導体基板の表面以上の上層部分のうち貫通電極の直上部分を有効に使用することができる。具体的に単結晶半導体基板としては、SiまたはGaAs等を含むものが挙げられ、多層金属配線層の金属配線としてはAlまたはCu等が挙げられる。多層金属配線層に到達せずにとは、完全に多層金属配線層に到達するものを排除するのではなく、おおよそ到達しない程度の意味である。これは貫通電極を形成する場合に若干多層金属配線層にまで貫通電極が形成されてしまう場合、また、冗長に貫通電極を形成する場合が想定されるからである。   The semiconductor element according to the present invention is formed with a through electrode penetrating from the front surface to the back surface of the single crystal semiconductor substrate, and the through electrode is formed without reaching the multilayer metal wiring layer above the semiconductor substrate surface. Is. Thus, in the present invention, the through electrode penetrating from the front surface to the back surface of the single crystal semiconductor substrate is formed, and since the through electrode is formed without reaching the multilayer metal wiring layer above the semiconductor substrate surface. In addition, the manufacturing time can be shortened with a simple structure, the yield, the cost and the reliability can be improved, and the portion directly above the through electrode in the upper layer portion above the surface of the semiconductor substrate can be effectively used. Specific examples of the single crystal semiconductor substrate include those containing Si or GaAs, and examples of the metal wiring of the multilayer metal wiring layer include Al or Cu. Not reaching the multilayer metal wiring layer does not mean that the multilayer metal wiring layer is completely reached, but does not almost reach the multilayer metal wiring layer. This is because when the through electrode is formed, the through electrode may be formed even in the multilayer metal wiring layer, and the through electrode may be redundantly formed.

また、本発明に係る半導体素子は、単結晶半導体基板の表面から裏面までを貫通した貫通電極が形成され、当該貫通電極が半導体基板表面より上層の多層金属配線層を貫通することなく形成されているものである。   Further, in the semiconductor element according to the present invention, a through electrode penetrating from the front surface to the back surface of the single crystal semiconductor substrate is formed, and the through electrode is formed without penetrating the multilayer metal wiring layer above the semiconductor substrate surface. There is something.

また、本発明に係る半導体素子は必要に応じて、前記貫通電極が前記多層金属配線層の金属材料よりも高い融点の金属材料からなり、当該貫通電極と半導体基板間に絶縁膜が形成されているものである。このように本発明においては、貫通電極が前記多層金属配線層の金属材料よりも高い融点の金属材料からなり、当該貫通電極と半導体基板間に絶縁膜が形成されているので、貫通電極を形成した後に半導体基板の表面より上層に多層金属配線層等を形成することができ、本構造の貫通電極を形成することができる。具体的に高融点金属材料としては、W、Ti、Poly-Si等、または、これらのポリサイド、シリサイド、サリサイド等が該当する。   Further, in the semiconductor element according to the present invention, the through electrode is made of a metal material having a melting point higher than that of the metal material of the multilayer metal wiring layer, and an insulating film is formed between the through electrode and the semiconductor substrate, if necessary. There is something. As described above, in the present invention, since the through electrode is made of a metal material having a melting point higher than that of the metal material of the multilayer metal wiring layer, and the insulating film is formed between the through electrode and the semiconductor substrate, the through electrode is formed. After that, a multilayer metal wiring layer or the like can be formed above the surface of the semiconductor substrate, and the through electrode of this structure can be formed. Specifically, the refractory metal material corresponds to W, Ti, Poly-Si, or the like, or polycide, silicide, salicide, or the like thereof.

また、本発明に係る半導体素子は必要に応じて、前記貫通電極は同一チップ内に複数あり、一の貫通電極が他の貫通電極の表面形状と異なるものである。このように本発明においては、貫通電極は同一チップ内に複数あり、一の貫通電極が他の貫通電極の表面形状と異なるので、目的に合わせて、電極配線などの貫通電極の抵抗を下げたり、チップ上のレイアウト制限を少なくしたり、自由な場所に自由な大きさの貫通電極を形成でき、動作の安定化、チップ面積の減少にも繋がる。   Further, in the semiconductor element according to the present invention, a plurality of the through electrodes are provided in the same chip as necessary, and one through electrode has a surface shape different from that of another through electrode. As described above, in the present invention, since there are a plurality of through electrodes in the same chip and one through electrode is different from the surface shape of the other through electrode, the resistance of the through electrode such as the electrode wiring can be reduced according to the purpose. Further, it is possible to reduce layout restrictions on the chip and to form through electrodes of any size in any place, which leads to stabilization of operation and reduction of chip area.

また、本発明に係る半導体素子は必要に応じて、前記半導体基板の表面上部に貫通電極埋め込み金属材料と異なる金属配線が形成され、半導体の配線領域又は周辺領域に貫通電極が形成されているものである。このように本発明においては、前記半導体基板の表面上部に貫通電極埋め込み金属材料と異なる金属配線が形成され、半導体の配線領域又は周辺領域に貫通電極が形成されているので、貫通電極の上部を、他の信号線、電源線として金属の配線が重なっている構造となって、チップ面積の減少が計られコストが安くなると同時に配線長が短くなり、高速化が計れる。   Further, in the semiconductor element according to the present invention, a metal wiring different from the through electrode embedded metal material is formed on the upper surface of the semiconductor substrate, and a through electrode is formed in a wiring region or a peripheral region of the semiconductor, if necessary. Is. As described above, in the present invention, since the metal wiring different from the through electrode embedded metal material is formed on the upper surface of the semiconductor substrate and the through electrode is formed in the wiring region or the peripheral region of the semiconductor, the upper portion of the through electrode is formed. Since the other signal lines and the power source lines are overlapped with metal wiring, the chip area can be reduced and the cost can be reduced, and at the same time, the wiring length can be shortened and the speed can be increased.

また、本発明に係る半導体素子は必要に応じて、前記貫通電極から半導体基板の表面及び／又は裏面で電極取り出しを行うための取り出し口が１つの貫通電極につき複数の取り出し口又は電極を有するものである。このように本発明においては、前記取り出し口が１つの貫通電極につき複数の取り出し口又は電極を有するので、例えば電源配線用の貫通電極は、複数取り出し電極を繋いで抵抗値を下げることが出来るし、信号線用の貫通電極から１つの信号を複数場所から取り出すことが出来るし、分岐結線として信号線の選択をする事が可能になる。   In addition, the semiconductor element according to the present invention has a plurality of extraction ports or electrodes for one penetration electrode for extracting electrodes from the penetration electrode on the front surface and/or the back surface of the semiconductor substrate, if necessary. Is. As described above, in the present invention, since the lead-out port has a plurality of lead-out electrodes or electrodes per one through-electrode, for example, the through-electrode for power supply wiring can reduce the resistance value by connecting the plurality of lead-out electrodes. One signal can be taken out from a plurality of places through the through electrode for the signal line, and the signal line can be selected as a branch connection.

また、本発明に係る半導体素子は必要に応じて、前記半導体基板裏面の貫通電極に金（Au）等の基板とオーミック接続の良い金属ボールを配設するものである。このように本発明においては、半導体基板裏面の貫通電極に金属ボールを配設するので、貫通電極からの裏面電極取り出し抵抗が下がり、信頼度向上と高速動作が可能となる。   Further, in the semiconductor element according to the present invention, a metal ball having good ohmic contact with a substrate such as gold (Au) is provided in the through electrode on the back surface of the semiconductor substrate, if necessary. As described above, in the present invention, since the metal ball is provided on the through electrode on the back surface of the semiconductor substrate, the resistance of the back electrode extraction from the through electrode is reduced, and the reliability is improved and the high speed operation is possible.

また、本発明に係る半導体素子は必要に応じて、半導体素子表面のパッドの他に前記半導体基板裏面を貫通した貫通電極に導通したパッドを半導体基板裏面に形成するものである。このように本発明においては、両面から接続することができるため、小さなチップ面積で、沢山の端子をもつことが出来て、コスト低減、チップ面積縮小、高速動作が可能となる。   Further, in the semiconductor element according to the present invention, in addition to the pads on the front surface of the semiconductor element, pads which are electrically connected to the through electrodes penetrating the rear surface of the semiconductor substrate are formed on the rear surface of the semiconductor substrate, if necessary. As described above, in the present invention, since connections can be made from both sides, a large number of terminals can be provided with a small chip area, enabling cost reduction, chip area reduction, and high-speed operation.

また、本発明に係る半導体素子は必要に応じて、前記半導体素子表面のパッドを形成しないものである。このように本発明においては、信号、電源などの端子を全て、基板裏面からの本発明貫通電極から供給することにより、基板表面にはボンヂングパッド等の絶縁物開口が無く、電極、ボンヂングワイア等の積層物が無い構造となり、半導体素子表面に直接熱放散板を取り付けることができ発熱を効率よく逃がすことができる。また、CCD、MOS等のセンサーを本半導体素子で実装すれば、従来のようにボンヂングワイヤがないため半導体表面とレンズなどの距離を短く出来てシステムの小型化を計ることができる。   Further, the semiconductor element according to the present invention does not have the pad on the surface of the semiconductor element, if necessary. As described above, in the present invention, all terminals for signals, power supplies, etc. are supplied from the through electrode of the present invention from the back surface of the substrate, so that there is no insulator opening such as a bonding pad on the front surface of the substrate and electrodes, bonding wires, etc. In this structure, the heat dissipation plate can be directly attached to the surface of the semiconductor element, and the heat generation can be efficiently released. Also, if a sensor such as CCD or MOS is mounted on this semiconductor device, the distance between the semiconductor surface and the lens can be shortened because there is no bonding wire as in the past, and the system can be downsized.

また、本発明に係る積層構造半導体システムは、前記所定の半導体素子を最上層に配置し、下層に前記半導体素子を配置して積層構造としているものである。このように本発明においては、複数の本半導体素子を縦に積層して、半導体素子間の信号のやりとり、若しくは上（下）に位置する半導体素子に繋がる配線を、貫通電極を通して行わせることもでき、簡単に積層構造半導体が実現し、コスト低減、高密度実装、高速動作、高信頼度のシステムが実現できる。   Further, the laminated structure semiconductor system according to the present invention has a laminated structure in which the predetermined semiconductor element is arranged in the uppermost layer and the semiconductor element is arranged in the lower layer. As described above, in the present invention, a plurality of the present semiconductor elements may be vertically stacked, and signals may be exchanged between the semiconductor elements or wirings connected to the upper (lower) semiconductor elements may be provided through the through electrodes. Therefore, it is possible to easily realize a laminated structure semiconductor and realize a system of cost reduction, high-density mounting, high-speed operation, and high reliability.

また、本発明に係る半導体インターポーザーは、前記半導体素子表面にTr.を形成することなく金属配線のみ形成し、半導体基板裏面に貫通電極の取り出し電極のみ形成された構成であるものである。このように本発明においては、半導体インターポーザーはその半導体基板の表面にはTr.が形成されずに金属配線だけが形成されており、表面（裏面）上に、半導体素子が実装された構造にすることができ、すなわち、半導体インターポーザーに本発明貫通電極を用いた構造となっており、これによりインターポーザーからの電極取出しが簡単になり、低コスト、システムの小型化が可能になる。このインターポーザーにより、半導体素子同士を結線することができる。   Further, the semiconductor interposer according to the present invention has a structure in which only the metal wiring is formed without forming the Tr. on the surface of the semiconductor element and only the lead electrode of the through electrode is formed on the back surface of the semiconductor substrate. As described above, in the present invention, the semiconductor interposer has the structure in which the semiconductor element is mounted on the front surface (back surface) without Tr. being formed on the surface of the semiconductor substrate. That is, the through electrode of the present invention is used for the semiconductor interposer, which makes it easy to take out the electrode from the interposer, and enables cost reduction and system miniaturization. The interposer can connect the semiconductor elements to each other.

また、本発明に係る半導体システムは、前記半導体インターポーザーの表面と裏面に、前記半導体素子が配置されて実装されているものである。このように本発明においては、半導体インターポーザーの表面と裏面に、前記記載の半導体素子が配置されて実装された半導体システムとすることで、半導体インターポーザーの表面と裏面を貫通する貫通電極を持つことにより、インターポーザーの表面と裏面に半導体素子を実装することが可能となり、実装密度の向上が計れる。すなわち、この半導体システムは、貫通電極で電気的に繋がれた複数の半導体素子が実装されているものということができる。   In the semiconductor system according to the present invention, the semiconductor element is arranged and mounted on the front surface and the back surface of the semiconductor interposer. As described above, in the present invention, a semiconductor system in which the above-described semiconductor element is arranged and mounted on the front surface and the back surface of the semiconductor interposer has a through electrode penetrating the front surface and the back surface of the semiconductor interposer. As a result, semiconductor elements can be mounted on the front surface and the back surface of the interposer, and the mounting density can be improved. That is, it can be said that this semiconductor system is mounted with a plurality of semiconductor elements electrically connected by the through electrodes.

また、本発明に係る半導体素子製造方法は、半導体基板表面より上層の多層金属配線層の形成する前に、半導体基板を開孔し、孔周りの半導体基板の内壁に酸化膜を成膜し、高融点金属を当該貫通電極孔に充填することにより貫通電極を形成するものである。このように本発明においては、半導体基板表面より上層の多層金属配線層の形成する前に、半導体基板を開孔し、孔周りの半導体基板の内壁に酸化膜を成膜し、高融点金属を当該貫通電極孔に充填することにより貫通電極を形成するので、容易に貫通電極が多層金属配線層に到達しない半導体素子を形成することができる。   Further, the semiconductor element manufacturing method according to the present invention, before forming the multilayer metal wiring layer above the semiconductor substrate surface, the semiconductor substrate is opened, an oxide film is formed on the inner wall of the semiconductor substrate around the hole, The through electrode is formed by filling the through electrode hole with a refractory metal. As described above, in the present invention, before forming the multilayer metal wiring layer above the surface of the semiconductor substrate, the semiconductor substrate is opened, an oxide film is formed on the inner wall of the semiconductor substrate around the hole, and a refractory metal is formed. Since the through electrode is formed by filling the through electrode hole, it is possible to easily form a semiconductor element in which the through electrode does not reach the multilayer metal wiring layer.

また、本発明に係る半導体素子製造方法は必要に応じて、前記半導体基板を開孔するための開口エッチングプロセス処理は、半導体基板表面のトランジスタ構成要素形成前の基板に対して行われるものである。このように本発明においては、前記半導体基板を開孔するための開口エッチングプロセス処理が、半導体基板の表面のトランジスタ構成要素形成前の基板に対して行われるので、貫通電極形成時に絶縁膜をエッチングすることなく、貫通電極孔のみに高融点金属を充填して貫通電極が形成され、無駄なく迅速に半導体素子を製造することができる。   In the semiconductor element manufacturing method according to the present invention, if necessary, the opening etching process for opening the semiconductor substrate is performed on the substrate on the surface of the semiconductor substrate before forming the transistor constituent elements. .. As described above, in the present invention, since the opening etching process for opening the semiconductor substrate is performed on the substrate on the surface of the semiconductor substrate before forming the transistor components, the insulating film is etched when the through electrode is formed. Without doing so, the through electrode is formed by filling only the through electrode hole with the refractory metal, and the semiconductor element can be rapidly manufactured without waste.

また、本発明に係る半導体素子製造方法は必要に応じて、前記半導体基板を開孔するための開口エッチングプロセス処理は、半導体基板表面のトランジスタ構成要素形成後前記多層金属配線層形成前の基板に対して行われるものである。このように本発明においては、開口エッチングプロセス処理は、半導体基板表面のトランジスタ構成要素形成後前記多層金属配線層形成前の基板に対して行われるので、一部の絶縁層に高融点金属が配設されるものの、かかる高融点金属は貫通電極のための配線として用いることができ、また、多層金属配線層を貫通した貫通電極が形成されることなく、貫通電極の上層に多層金属配線層を形成することができる。   Further, in the semiconductor element manufacturing method according to the present invention, if necessary, the opening etching process for opening the semiconductor substrate is performed on the substrate after the formation of the transistor components on the surface of the semiconductor substrate and before the formation of the multilayer metal wiring layer. It is done to the contrary. As described above, in the present invention, since the opening etching process is performed on the substrate after the formation of the transistor constituent elements on the surface of the semiconductor substrate and before the formation of the multilayer metal wiring layer, refractory metal is partially distributed on some insulating layers. Although provided, such a refractory metal can be used as wiring for a through electrode, and a multilayer metal wiring layer is formed on the through electrode without forming a through electrode penetrating the multilayer metal wiring layer. Can be formed.

また、本発明に係る半導体素子製造方法は必要に応じて、前記貫通電極形成時に半導体基板裏面まで貫通させずに所定の深さまでの貫通電極穴を形成し、後で半導体基板裏面を研削又は研磨するものである。このように本発明においては、貫通電極穴を所定の深さ程度形成しかかる貫通電極穴に高融点金属を充填し、半導体基板表面プロセス処理完了後基板表面を研削、エッチングして所望の厚さにすれば、高融点金属が表出し、結果的に貫通電極を形成することができ、貫通電極形成プロセス（特にエッチング部分）が容易となり、全体として製造コストを下げることができる。   Further, the semiconductor element manufacturing method according to the present invention, if necessary, to form a through electrode hole to a predetermined depth without penetrating to the back surface of the semiconductor substrate when forming the through electrode, and then grinding or polishing the back surface of the semiconductor substrate. To do. As described above, in the present invention, a through electrode hole is formed to a predetermined depth, the through electrode hole is filled with a refractory metal, and the substrate surface is ground and etched after completion of the semiconductor substrate surface process treatment to a desired thickness. In this case, the refractory metal is exposed, and as a result, the through electrode can be formed, the through electrode forming process (particularly the etching portion) is facilitated, and the manufacturing cost can be reduced as a whole.

この発明によれば、貫通電極材料は基板表面の配線材料よりも融点が高いために、配線工程処理前に貫通電極を完成させることができる。これにより貫通電極用のプロセスが簡単になり、信頼度向上、歩留まり向上、特性向上を計ることができる。
この発明によれば、貫通電極の表面酸化膜から基板を通しての開口孔が不要であり、低融点金属（Cu等）の埋め込みも不要であるのでプロセスが簡素化されてコスト低減、信頼度向上が計れる。According to this invention, since the through electrode material has a higher melting point than the wiring material on the surface of the substrate, the through electrode can be completed before the wiring process. This simplifies the process for the through electrode and improves reliability, yield, and characteristics.
According to the present invention, an opening hole from the surface oxide film of the through electrode through the substrate is not required and a low melting point metal (Cu or the like) is not required to be embedded, so that the process is simplified, the cost is reduced, and the reliability is improved. Can be measured.

この発明によれば、貫通電極の形状を変えることにより、電極抵抗を下げることができて、重い負荷容量の信号配線や電源配線の貫通電極の抵抗を下げて半導体の高速、安定動作が得られる。
この発明によれば、貫通電極の上部に別の配線を通すことができるためチップ面積を小さくできてコスト低減が計れる。
この発明によれば、貫通電極を半導体中央部の配線領域に配列できるので、電極からの引き回し配線長が短くできるため、半導体の高速動作と安定動作が計れる。According to the present invention, the electrode resistance can be reduced by changing the shape of the through electrode, and the resistance of the through electrode of the signal wiring or the power supply wiring having a heavy load capacitance can be reduced to achieve high-speed and stable operation of the semiconductor. ..
According to the present invention, since another wiring can be passed over the through electrode, the chip area can be reduced and the cost can be reduced.
According to the present invention, since the through electrodes can be arranged in the wiring region in the central portion of the semiconductor, the length of the wiring routed from the electrodes can be shortened, so that high-speed operation and stable operation of the semiconductor can be achieved.

この発明によれば、半導体上面からのボンヂングパッドからと、裏面の貫通電極からと、両方からの信号のやり取りができるために、多端子半導体が容易に実現できる。
この発明によれば、半導体表面からは端子の取り出しが不要となり、半導体表面を直接パッケージに実装でき、熱放散が良くなり、信頼度が向上できる。
この発明によれば、半導体表面からは端子の取り出しが不要となり、光センサー等の短焦点化が可能となるため、装置の小型化が計られる。
この発明をインターポーザーに応用することにより、装置の小型化、高速化、高信頼度化が可能になる。According to the present invention, signals can be exchanged from both the bonding pad from the upper surface of the semiconductor and the through electrode on the back surface, so that a multi-terminal semiconductor can be easily realized.
According to the present invention, it is not necessary to take out terminals from the semiconductor surface, the semiconductor surface can be directly mounted on the package, heat dissipation is improved, and reliability can be improved.
According to the present invention, it is not necessary to take out a terminal from the surface of the semiconductor, and it is possible to shorten the focus of the optical sensor or the like, so that the device can be downsized.
By applying the present invention to an interposer, it becomes possible to reduce the size, speed, and reliability of the device.

本発明の第１の実施形態に係る半導体素子の貫通電極構造の断面図である。FIG. 3 is a cross-sectional view of a through electrode structure of a semiconductor device according to the first embodiment of the present invention. 本発明の第１の実施形態に係る半導体素子の製造方法の概要フローチャートである。3 is a schematic flowchart of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 本発明の第１の実施形態に係る半導体素子の製造方法の概要フローチャートである。3 is a schematic flowchart of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 本発明の第２の実施形態に係る半導体素子の貫通電極構造の断面図である。It is sectional drawing of the penetration electrode structure of the semiconductor element which concerns on the 2nd Embodiment of this invention. 本発明の第２の実施形態に係る半導体素子の製造方法の概要フローチャートである。6 is a schematic flowchart of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. 本発明の第２の実施形態に係る半導体素子の製造方法の概要フローチャートである。6 is a schematic flowchart of a method for manufacturing a semiconductor device according to a second embodiment of the present invention. 本発明の第３の実施形態に係る半導体素子の平面配置図である。It is a plane layout drawing of a semiconductor device concerning a 3rd embodiment of the present invention. 本発明の第４の実施形態に係る半導体素子の積層状態図である。It is a lamination|stacking state figure of the semiconductor element which concerns on the 4th Embodiment of this invention. 本発明の第５の実施形態に係る半導体素子の組み立て実装構造の断面図である。It is sectional drawing of the assembly mounting structure of the semiconductor element which concerns on the 5th Embodiment of this invention. 本発明の第５の実施形態に係る半導体素子をCCDに適用した実装構造の断面図である。It is sectional drawing of the mounting structure which applied the semiconductor element which concerns on the 5th Embodiment of this invention to CCD. 本発明の第６の実施形態に係る半導体素子の貫通電極構造の断面図である。It is sectional drawing of the penetration electrode structure of the semiconductor element which concerns on the 6th Embodiment of this invention. 本発明の第６の実施形態に係る半導体素子の積層状態図である。It is a lamination|stacking state figure of the semiconductor element which concerns on the 6th Embodiment of this invention. 従来の半導体素子の貫通電極構造の断面図である。It is sectional drawing of the conventional through electrode structure of a semiconductor element. 従来の半導体素子の組み立て実装構造の断面図である。It is sectional drawing of the assembly mounting structure of the conventional semiconductor element. 従来のCCDの実装構造の断面図である。It is sectional drawing of the mounting structure of the conventional CCD.

符号の説明Explanation of symbols

１ 半導体基板
２ トランジスタ（Tr.）
３ ゲート
４ ソース、ドレイン
５ 高融点金属配線
６ 絶縁膜
７ 貫通電極金属
８ 多層金属配線層
９ 絶縁膜
１０ 保護絶縁膜
１１ ボンヂングパット
１２ 追加絶縁膜
１３ 追加保護絶縁膜
１４ 追加金属配線
１５ 表面取り出し電極
１６ 裏面絶縁膜
１７ 裏面取り出し電極
１８ ボード
１９ 半田バンプ
２０ パッケージ
２１ 金属バンプ
２２ 半導体素子
２３ 放熱板
２４ 半導体素子裏面
２５ 半導体素子表面
２６ ボンヂングワイア
２７ 透過材料
２８ 光源
２９ レンズ
３０、３１、３２ （高融点金属）貫通電極
３３ 高融点金属配線
３４ （電極）絶縁膜
３８ 裏面絶縁膜
３９ 裏面電極開口（部）
４０ 裏面電極金属
４２ 周辺領域
４３ Tr.領域
４４ 配線領域
４５ エッチング防止膜
４６ エッチング防止膜開口部
４７ 貫通電極孔
４８ 貫通電極穴
４９ 半導体インターポーザー
５０ 積層半導体素子（DRAM）
５１ 積層半導体素子（Flash）
５２ 積層半導体素子（論理LSI）
５３ 積層半導体素子（アナログLSI）
５４ 積層半導体素子（ドライバーIC）1 Semiconductor substrate 2 Transistor (Tr.)
3 Gate 4 Source/Drain 5 High melting point metal wiring 6 Insulating film 7 Through electrode metal 8 Multilayer metal wiring layer 9 Insulating film 10 Protective insulating film 11 Bonding pad 12 Additional insulating film 13 Additional protective insulating film 14 Additional metal wiring 15 Surface extraction Electrode 16 Backside insulating film 17 Backside extraction electrode 18 Board 19 Solder bump 20 Package 21 Metal bump 22 Semiconductor element 23 Heat sink 24 Semiconductor element backside 25 Semiconductor element surface 26 Bonding wire 27 Transparent material 28 Light source 29 Lens 30, 31, 32 (high melting point Metal) Through electrode 33 Refractory metal wiring 34 (Electrode) Insulating film 38 Backside insulating film 39 Backside electrode opening (part)
40 Back Electrode Metal 42 Peripheral Region 43 Tr. Region 44 Wiring Region 45 Etching Preventing Film 46 Etching Preventing Film Opening 47 Through Electrode Hole 48 Through Electrode Hole 49 Semiconductor Interposer 50 Multilayer Semiconductor Device (DRAM)
51 Multilayer semiconductor device (Flash)
52 Stacked semiconductor device (logic LSI)
53 Stacked semiconductor devices (analog LSI)
54 Multilayer semiconductor device (driver IC)

（本発明の第１の実施形態）
本発明の第１の実施形態に係る半導体素子について図１ないし図３に基づき説明する。図１は本実施形態に係る半導体素子の貫通電極構造の断面図、図２は本実施形態に係る半導体素子の製造方法の概要フローチャート、図３は本実施形態に係る半導体素子の製造方法の概要フローチャートである。
前記図１において本実施形態に係る半導体素子は、シリコン（Si）からなる単結晶の半導体基板1にはトランジスタ(Tr.)２と貫通電極３１、３２から構成され、図上部の半導体基板１表面はトランジスタ（Tr.）２の高融点金属材料からなるゲート３、ゲート材料と同じ高融点金属（ホ゜リSi、W、Ti、シリサイド、ポリサイド等）配線５と多層金属（Al、Cu等）配線８と絶縁膜９と保護絶縁膜１０から構成され、保護絶縁膜１０の一部が開口され多層金属配線８の最上部金属が露出されておりボンヂングパッド１１となっている。図下部の半導体基板裏面は裏面絶縁膜３８と、開口部３９に接着された裏面電極金属４０から構成される。貫通電極３１、３２は高融点金属で埋め込まれており、半導体基板１表面と同一平面まで埋め込まれている。貫通電極３１、３２表面からは、スルーホールを通して多層金属配線層８の金属配線を介し、所望の場所に信号を伝えられる構造となっている。(First Embodiment of the Invention)
A semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view of a through electrode structure of a semiconductor device according to this embodiment, FIG. 2 is a schematic flowchart of a method for manufacturing a semiconductor device according to this embodiment, and FIG. 3 is a schematic method for manufacturing a semiconductor device according to this embodiment. It is a flowchart.
In FIG. 1, the semiconductor device according to the present embodiment includes a transistor (Tr.) 2 and through electrodes 31 and 32 on a single crystal semiconductor substrate 1 made of silicon (Si). Is a gate 3 made of a refractory metal material of the transistor (Tr.) 2, a refractory metal (poly Si, W, Ti, silicide, polycide, etc.) wiring 5 and a multi-layer metal (Al, Cu, etc.) wiring 8 which are the same as the gate material. The insulating film 9 and the protective insulating film 10 are formed, and a part of the protective insulating film 10 is opened to expose the uppermost metal of the multilayer metal wiring 8 to form a bonding pad 11. The back surface of the semiconductor substrate at the bottom of the figure is composed of a back surface insulating film 38 and a back surface electrode metal 40 bonded to the opening 39. The penetrating electrodes 31 and 32 are filled with a refractory metal, and are buried up to the same plane as the surface of the semiconductor substrate 1. From the surface of the through electrodes 31 and 32, a signal can be transmitted to a desired place through the through holes and the metal wiring of the multilayer metal wiring layer 8.

半導体基板１はP型を使用し表面上にトランジスタ（Tr.）２がソース４、ドレイン４及びゲート３から形成されている。ソース４、ドレイン４は、基板1に比べてN型拡散層の不純物濃度は最も濃く、電気抵抗が拡散層の中で最も低く作られている。当然P型拡散層ソース、ドレインを持ったP型MOS Tr.はNウェル内に形成されているが、図１には省いてある。
半導体基板１の表面から裏面に、貫通電極３１、３２が柱状に基板に垂直に貫通している。貫通電極３１、３２と半導体基板１との間には、絶縁膜３４が存在する。The semiconductor substrate 1 is of P type, and a transistor (Tr.) 2 is formed on the surface from a source 4, a drain 4 and a gate 3. The source 4 and the drain 4 have the highest impurity concentration in the N-type diffusion layer and the lowest electric resistance in the diffusion layer as compared with the substrate 1. Naturally, the P-type MOS Tr. having the P-type diffusion layer source and drain is formed in the N well, but it is omitted in FIG.
Through electrodes 31 and 32 are column-shaped and vertically penetrate the substrate from the front surface to the back surface of the semiconductor substrate 1. An insulating film 34 exists between the through electrodes 31 and 32 and the semiconductor substrate 1.

貫通電極の形状は自由であり、例えば信号を伝える小電流電極は貫通電極３１、３２のように細い円柱形状で、電源などの大電流電極は別途太い楕円形状、あるいは壁状となった貫通電極を作成することもできる。すなわち、貫通電極の太さ、形状を変えることにより、貫通電極電気抵抗を下げたりすることが出来、電源配線などの貫通電極の抵抗を下げたり、チップ上のレイアウト制限が少なくなり、自由な場所に、自由な大きさの貫通電極配置が出来て、動作の安定化、チップ面積の減少が計れる。   The shape of the through electrode is arbitrary, for example, a small current electrode for transmitting a signal is a thin columnar shape like the through electrodes 31 and 32, and a large current electrode such as a power supply is a thick elliptical shape or a wall-shaped through electrode. Can also be created. That is, by changing the thickness and shape of the through electrode, it is possible to reduce the electrical resistance of the through electrode, reduce the resistance of the through electrode such as the power supply wiring, and reduce the layout restrictions on the chip. In addition, it is possible to arrange the through electrodes of any size, stabilize the operation, and reduce the chip area.

貫通電極からの表面、裏面への取り出し電極は複数箇所であっても良い。このように取り出し電極を複数個有する構造であれば、例えば電源配線用の貫通電極は、複数取り出し電極を繋いで抵抗値を下げることが出来るし、信号線用の貫通電極から１つの信号を複数場所から取り出すことが出来るし、分岐結線として信号線の選択をする事が可能になる。   There may be a plurality of lead electrodes from the through electrode to the front surface and the back surface. With such a structure having a plurality of lead-out electrodes, for example, a through electrode for power supply wiring can reduce the resistance value by connecting a plurality of lead-out electrodes, and a single signal can be transmitted from the through electrode for a signal line. It can be taken out from the place and it becomes possible to select the signal line as a branch connection.

貫通電極３１、３２の裏面からの電極は、裏面絶縁膜３８の裏面電極開口部３９に裏面電極金属（金属ボール等）４０を設けて電極を取り出す構造としている。このように貫通電極を半導体基板裏面から取り出す場合、基板（貫通電極）材料と馴染む材料として金等の金属ボールを使用した構造とするので、貫通電極からの裏面電極取り出し抵抗が下がり、信頼度向上と高速動作が可能となる。
貫通電極３１、３２は半導体基板１の表面まで形成されその上には形成されず、その上には種々の高融点金属配線５、多層金属配線層８が自由に形成されている。The electrodes from the back surface of the through electrodes 31 and 32 have a structure in which a back surface electrode metal (metal ball or the like) 40 is provided in the back surface electrode opening 39 of the back surface insulating film 38 to take out the electrode. In this way, when the through electrode is taken out from the back surface of the semiconductor substrate, the structure is such that a metal ball such as gold is used as a material that is compatible with the substrate (through electrode) material, so the resistance to take out the back surface electrode from the through electrode is reduced and reliability is improved. And high speed operation becomes possible.
The through electrodes 31 and 32 are formed up to the surface of the semiconductor substrate 1 and are not formed thereon, and various refractory metal wirings 5 and multilayer metal wiring layers 8 are freely formed thereon.

次に、本実施形態に係る半導体素子の製造方法について図２に基づき説明する。図２は図１に示す断面構造の製造方法を示した図である。本製造方法の特徴の１つは、半導体基板１の開口エッチングプロセス処理は半導体基板１上のトランジスタ（Tr.）２領域（ウェル、拡散、ゲート）形成前に行うことである。図２に示すように、半導体基板１（Si）表面にエッチング防止膜４５（SiO2）を形成（酸化、デボ）し、その上から貫通電極ホトマスクによる露光、エッチングで貫通電極形成用パターンを形成する（エッチング防止膜開口部４６が形成される）。このとき、ホトマスクを用いることなく直接露光により同様に形成することができる。エッチング防止膜開口部４６を利用して半導体基板１の該当部分をエッチングする。一般的にプラズマエッチングを用いるが、ウエットエッチングを用いてもよい。このエッチングを半導体基板１裏面に貫通するまで行う。エッチング後洗浄し、酸素雰囲気下でSiを酸化させて、半導体基板１の貫通電極孔４７の部分の内壁にSiO2を成長させる（温度は１０００度Ｃないし１２００度Ｃが一般的である）。このとき、酸素雰囲気下で酸化させるのではなく、ＣＶＤ（Chemical Vapor Deposition）等の気相成長法でSiO2等を成長させて絶縁膜３４を形成させてもよい。次に、貫通電極孔４７内に高融点金属を充填する。充填する手段はＣＶＤ、蒸着、メッキ等があるが、充填材料の特性によって最適な手法を選択する。例えば、ポリSiの場合にはＣＶＤが最適であるし、タングステンの場合はＣＶＤ若しくは蒸着が最適である。充填が終了すると、洗浄した後、通常の半導体工程を施せばよく、ウェル工程から開始する。最後に、半導体基板１の裏面絶縁膜３８を形成して開口することでウエハが完成する。図１の裏面電極金属４０は、組み立て前に装着するのが一般的であるが、ウエハが完成して、チップにダイシングする前に裏面電極金属４０を予め装着してもよい。また、裏面電極金属４０は実装側に形成されていて、実装時に結果として半導体素子１の裏面電極金属４０となる構成にすることもできる。   Next, a method of manufacturing the semiconductor device according to this embodiment will be described with reference to FIG. FIG. 2 is a diagram showing a method of manufacturing the sectional structure shown in FIG. One of the features of this manufacturing method is that the opening etching process of the semiconductor substrate 1 is performed before forming the transistor (Tr.) 2 region (well, diffusion, gate) on the semiconductor substrate 1. As shown in FIG. 2, an etching prevention film 45 (SiO2) is formed (oxidized, devoted) on the surface of the semiconductor substrate 1 (Si), and a through electrode formation pattern is formed by exposure and etching with a through electrode photomask. (An etching prevention film opening 46 is formed). At this time, it can be similarly formed by direct exposure without using a photomask. The corresponding portion of the semiconductor substrate 1 is etched using the etching prevention film opening 46. Generally, plasma etching is used, but wet etching may be used. This etching is performed until the back surface of the semiconductor substrate 1 is penetrated. After etching, cleaning is performed, and Si is oxidized in an oxygen atmosphere to grow SiO2 on the inner wall of the through electrode hole 47 portion of the semiconductor substrate 1 (the temperature is generally 1000°C to 1200°C). At this time, the insulating film 34 may be formed by growing SiO2 or the like by a vapor phase growth method such as CVD (Chemical Vapor Deposition), instead of oxidizing it in an oxygen atmosphere. Next, the through electrode hole 47 is filled with a refractory metal. There are CVD, vapor deposition, plating, etc. as the means for filling, and the optimum method is selected depending on the characteristics of the filling material. For example, in the case of poly-Si, CVD is optimal, and in the case of tungsten, CVD or vapor deposition is optimal. When the filling is completed, a normal semiconductor process may be performed after cleaning, and the well process is started. Finally, the back surface insulating film 38 of the semiconductor substrate 1 is formed and opened to complete the wafer. The back electrode metal 40 in FIG. 1 is generally attached before assembly, but the back electrode metal 40 may be attached in advance before dicing into chips after the wafer is completed. Further, the back surface electrode metal 40 may be formed on the mounting side, and the back surface electrode metal 40 of the semiconductor element 1 may be formed as a result at the time of mounting.

このように本実施形態に係る半導体素子によれば、単結晶半導体基板１の表面から裏面までを貫通した貫通電極３１、３２が形成され、この貫通電極３１、３２が半導体基板表面より上層の多層金属配線層８に到達せずに形成されているので、半導体基板１の表面以上の上層部分のうち貫通電極３１、３２の直上部分を有効に使用することができる。また、本実施形態に係る半導体素子によれば、前記貫通電極３１、３２が前記多層金属配線層８の金属材料よりも高い融点の金属材料からなり、この貫通電極３１、３２と半導体基板１間に絶縁膜３４が形成されているので、貫通電極３１、３２を形成した後に半導体基板１の表面より上層に多層金属配線層８等を形成することができ、本構造の貫通電極３１、３２を形成することができる。また、本実施形態に係る半導体素子によれば、前記貫通電極３１、３２は同一チップ内に複数あり、一の貫通電極３１が他の貫通電極３２の表面形状（太さ、パターン）と異なっており、目的に合わせて、電極配線などの貫通電極の抵抗を下げたり、チップ上のレイアウト制限を少なくしたり、自由な場所に自由な大きさの貫通電極を形成でき、動作の安定化、チップ面積の減少にも繋がる。また、本実施形態に係る半導体素子によれば、前記半導体基板１の裏面の貫通電極３１、３２に金（Au）等の基板とオーミック接続の良い金属ボールを配設するので、貫通電極３１、３２からの裏面電極取出抵抗が下がり、信頼度向上と高速動作が可能となる。また、本実施形態に係る半導体素子製造方法によれば、半導体基板表面より上層の多層金属配線層８の形成する前に、半導体基板１を開孔し、孔周りの半導体基板１の内壁に絶縁膜３４を成膜し、高融点金属を当該貫通電極孔４７に充填することにより貫通電極３１、３２を形成するので、貫通電極が多層金属配線層に到達しない半導体素子を容易に形成することができる。また、本実施形態に係る半導体素子製造方法によれば、前記半導体基板１を開孔するための開口エッチングプロセス処理は、半導体基板１の表面のトランジスタ構成要素形成前の基板に対して行われるので、貫通電極形成時に絶縁膜をエッチングすることなく、貫通電極孔４７のみに高融点金属を充填して貫通電極が形成された半導体素子を製造することができる。   As described above, according to the semiconductor element of the present embodiment, the through electrodes 31 and 32 penetrating from the front surface to the back surface of the single crystal semiconductor substrate 1 are formed, and the through electrodes 31 and 32 are multi-layers above the front surface of the semiconductor substrate. Since the metal wiring layer 8 is formed without reaching the metal wiring layer 8, it is possible to effectively use the portion directly above the penetrating electrodes 31 and 32 in the upper layer portion above the surface of the semiconductor substrate 1. Further, according to the semiconductor element of the present embodiment, the through electrodes 31, 32 are made of a metal material having a melting point higher than that of the metal material of the multilayer metal wiring layer 8, and between the through electrodes 31, 32 and the semiconductor substrate 1. Since the insulating film 34 is formed on the upper surface of the semiconductor substrate 1, the multilayer metal wiring layer 8 and the like can be formed above the surface of the semiconductor substrate 1 after the through electrodes 31 and 32 are formed. Can be formed. In addition, according to the semiconductor device of this embodiment, the through electrodes 31 and 32 are plural in the same chip, and one through electrode 31 is different from the surface shape (thickness, pattern) of the other through electrode 32. Depending on the purpose, it is possible to reduce the resistance of the through electrodes such as electrode wiring, reduce the layout restrictions on the chip, and form through electrodes of any size in any location, to stabilize the operation, It also leads to a reduction in area. Further, according to the semiconductor element of the present embodiment, the through electrodes 31, 32 on the back surface of the semiconductor substrate 1 are provided with metal balls having good ohmic contact with the substrate such as gold (Au). The rear surface electrode extraction resistance from 32 is lowered, and reliability can be improved and high-speed operation can be performed. Further, according to the semiconductor element manufacturing method of this embodiment, the semiconductor substrate 1 is opened before the formation of the multilayer metal wiring layer 8 above the surface of the semiconductor substrate, and the inner wall of the semiconductor substrate 1 around the hole is insulated. Since the through electrodes 31 and 32 are formed by forming the film 34 and filling the high melting point metal in the through electrode holes 47, it is possible to easily form a semiconductor element in which the through electrodes do not reach the multilayer metal wiring layer. it can. Further, according to the semiconductor device manufacturing method of the present embodiment, the opening etching process for opening the semiconductor substrate 1 is performed on the substrate on the surface of the semiconductor substrate 1 before forming the transistor constituent elements. A semiconductor element having a through electrode can be manufactured by filling only the through electrode hole 47 with a refractory metal without etching the insulating film when forming the through electrode.

なお、本実施形態に係る半導体素子の製造方法を図２に示したが、図３に示すようにもできる。例えば基板最終厚さが５０［μｍ］であれば、貫通電極の深さは５０［μｍ］以上あればよい。ここで、ウエハのプロセス処理時はウエハの強度の関係でウエハの厚さは２００〜７００［μｍ］程度必要とされる。そこで、貫通電極穴４８を深さ６０［μｍ］程度形成しかかる貫通電極穴４８に高融点金属を充填し、半導体基板表面プロセス処理完了後基板裏面を研削、エッチングして所望の厚さにすれば、充填された高融点金属が基板裏面に表出し、結果的に貫通電極を形成することができる。このように貫通電極を形成することにより、貫通電極形成プロセス（特にエッチング部分）が容易となり、全体として製造コストを下げることができる。   Although the method of manufacturing the semiconductor device according to the present embodiment is shown in FIG. 2, it may be performed as shown in FIG. For example, if the final thickness of the substrate is 50 [μm], the depth of the through electrode may be 50 [μm] or more. Here, at the time of processing the wafer, the thickness of the wafer is required to be about 200 to 700 [μm] due to the strength of the wafer. Therefore, the through electrode hole 48 is formed to a depth of about 60 [μm], the through electrode hole 48 is filled with a refractory metal, and the back surface of the substrate is ground and etched after the completion of the semiconductor substrate surface process treatment, so that the desired thickness is obtained. For example, the filled high melting point metal is exposed on the back surface of the substrate, and as a result, the through electrode can be formed. By forming the through electrode in this manner, the through electrode forming process (particularly the etching portion) is facilitated, and the manufacturing cost can be reduced as a whole.

（本発明の第２の実施形態）
本発明の第２の実施形態に係る半導体素子の製造方法について図４または図５に基づき説明する。図４は本実施形態に係る半導体素子の貫通電極構造の断面図、図５及び図６は本実施形態に係る半導体素子の製造方法の概要フローチャートである。
前記図４において本実施形態に係る半導体素子は、前記第１の実施形態に係る半導体素子と略同様に構成され、製造方法が異なることを異にする構成である。略同様にとしたのは、貫通電極孔４７がゲート材料の配線５の上部までを貫通し、貫通電極孔４７に充填した高融点金属が半導体基板１の表面の多層金属配線層８の下層の高融点金属配線３３として用いている部分が異なるからである。そして、この半導体素子の製造方法は、図５に示すように、半導体基板１の貫通電極孔４７のための開口エッチングプロセス処理は、ゲート材料の配線５を完成させた後に行い、貫通電極孔４７の形成後、孔周りの半導体基板の内壁に絶縁膜３４を形成し、高融点金属を充填して行い、これ以降の処理は図２に示した前記第１の実施形態の製造方法と略同一である。ここで、高融点金属配線５を完成させた後に、貫通電極を形成する工程を行っており、貫通電極だけでなく半導体基板表面に高融点金属が配設された状態となり、かかる高融点金属を高融点金属配線３３として用いることができる。(Second Embodiment of the Invention)
A method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a sectional view of a through electrode structure of a semiconductor device according to this embodiment, and FIGS. 5 and 6 are schematic flowcharts of a method for manufacturing a semiconductor device according to this embodiment.
In FIG. 4, the semiconductor device according to the present embodiment is configured substantially the same as the semiconductor device according to the first embodiment, except that the manufacturing method is different. The substantially same reason is that the through electrode hole 47 penetrates up to the upper part of the wiring 5 of the gate material, and the refractory metal filled in the through electrode hole 47 is formed in the lower layer of the multilayer metal wiring layer 8 on the surface of the semiconductor substrate 1. This is because the portion used as the high melting point metal wiring 33 is different. In the method of manufacturing the semiconductor element, as shown in FIG. 5, the opening etching process for the through electrode hole 47 of the semiconductor substrate 1 is performed after the wiring 5 of the gate material is completed, and the through electrode hole 47 is formed. After the formation, the insulating film 34 is formed on the inner wall of the semiconductor substrate around the hole and is filled with a refractory metal, and the subsequent processing is substantially the same as the manufacturing method of the first embodiment shown in FIG. Is. Here, after the refractory metal wiring 5 is completed, a step of forming a through electrode is performed, and the refractory metal is provided not only on the through electrode but also on the surface of the semiconductor substrate. It can be used as the refractory metal wiring 33.

このように本実施形態に係る半導体素子の製造方法によれば、半導体基板１を開孔するための開口エッチングプロセス処理は、半導体基板表面のトランジスタ構成要素形成後前記多層金属配線層形成前の基板に対して行われるので、一部の絶縁層に高融点金属が配設されるものの、かかる高融点金属は貫通電極のための配線として用いることができ、また、多層金属配線層を貫通した貫通電極が形成されることなく、貫通電極の上層に多層金属配線層を形成することができる。   As described above, according to the method for manufacturing a semiconductor device of the present embodiment, the opening etching process for opening the semiconductor substrate 1 is performed after the formation of the transistor components on the surface of the semiconductor substrate and before the formation of the multilayer metal wiring layer. Since a refractory metal is provided in a part of the insulating layer, the refractory metal can be used as wiring for the through electrode, and the refractory metal penetrates through the multilayer metal wiring layer. It is possible to form a multilayer metal wiring layer on the upper layer of the through electrode without forming the electrode.

また、前記図５に示す製造方法においても、引き伸ばし拡散による広幅化が生じるため、図６に示すように、半導体基板表面プロセス処理完了後半導体基板裏面を研削、エッチして、所望の厚さとすることもできる。これにより引き伸ばし拡散による広幅化を抑制することができ、チップ面積の縮小化が可能となると同時に拡散時間の短縮が計れて、コストが安くなる。   Further, also in the manufacturing method shown in FIG. 5, since the width is widened by stretching and diffusion, as shown in FIG. 6, the back surface of the semiconductor substrate is ground and etched to obtain a desired thickness as shown in FIG. You can also As a result, widening due to stretching and diffusion can be suppressed, the chip area can be reduced, and at the same time, the diffusion time can be shortened and the cost can be reduced.

（本発明の第３の実施形態）
本発明の第３の実施形態に係る半導体素子について図７に基づき説明する。図７は本実施形態に係る半導体素子の平面配置図を示す。
前記図７において、半導体素子の表面は、ボンヂングパッド１１等を配置する周辺領域４２、トランジスタ（Tr.）２が蜜に配置されているTr.領域（セル領域）４３、複数層の金属配線だけが配置される配線領域４４から構成される。(Third Embodiment of the Invention)
A semiconductor device according to the third embodiment of the present invention will be described with reference to FIG. FIG. 7 is a plan view of the semiconductor device according to this embodiment.
In FIG. 7, the surface of the semiconductor element has a peripheral region 42 where the bonding pad 11 and the like are arranged, a Tr. region (cell region) 43 where the transistor (Tr.) 2 is closely arranged, and a plurality of layers of metal wiring. Only the wiring area 44 is arranged.

図７に示すように貫通電極３０、３１、３２及びそれ以外の複数の貫通電極が配置されておりその場所は周辺領域４２だけでなく、配線領域４４の中にも配置されることが可能であることが解る。これは、貫通電極３０、３１、３２は半導体基板１の表面までで止まっており、その上層に種々の高融点金属配線５、多層金属配線層８を自由に配線することができるからである。貫通電極は多様な太さ、形状が可能であり、信号線は細い貫通電極３２で、バス信号などの負荷容量の大きな信号線は少し太い貫通電極３１で、電源線などは大きく太い貫通電極３０とすることが可能である。   As shown in FIG. 7, the through electrodes 30, 31, 32 and a plurality of other through electrodes are arranged, and the positions thereof can be arranged not only in the peripheral region 42 but also in the wiring region 44. I know that there is. This is because the through electrodes 30, 31, 32 are stopped up to the surface of the semiconductor substrate 1, and various refractory metal wirings 5 and the multi-layered metal wiring layer 8 can be freely wired thereabove. The through electrodes can have various thicknesses and shapes, the signal lines are thin through electrodes 32, the signal lines having a large load capacitance such as a bus signal are slightly thick through electrodes 31, and the power supply lines are large and thick through electrodes 30. It is possible to

次に、本実施形態においては、半導体基板表面プロセス工程中で、半導体基板表面の金属配線（ポリSi、ポリサイド、シリサイド、モリブテン、アルミ、銅等）の形成前に少なくとも貫通電極を形成することで、前記配線を実現することができる。
このように本実施形態に係る半導体素子によれば、前記半導体基板１の表面上部に貫通電極３０、３１、３２と異なる金属配線が形成され、半導体素子の配線領域４４又は周辺領域４２に貫通電極が形成されているので、貫通電極の上部を、他の信号線、電源線として金属の配線が重なっている構造となって、チップ面積の減少が計られコストが安くなると同時に配線長が短くなり、高速化が計れる。Next, in the present embodiment, at least the through electrode is formed in the semiconductor substrate surface process step before forming the metal wiring (poly-Si, polycide, silicide, molybdenum, aluminum, copper, etc.) on the semiconductor substrate surface. The wiring can be realized.
As described above, according to the semiconductor device of the present embodiment, the metal wiring different from the through electrodes 30, 31, 32 is formed on the upper surface of the semiconductor substrate 1, and the through electrode is formed in the wiring region 44 or the peripheral region 42 of the semiconductor device. Is formed, the metal wiring overlaps the upper part of the through electrode as other signal lines and power supply lines, reducing the chip area and reducing the cost, and at the same time shortening the wiring length. The speed can be increased.

（本発明の第４の実施形態）
本発明の第４の実施形態に係る半導体素子について図８に基づき説明する。図８は本実施形態に係る半導体素子の積層状態図を示す。
本実施形態に係る半導体素子においては、前記第１の実施形態に係る半導体素子と同様に構成され、加えて半導体素子表面２５のパッドの他に前記半導体基板裏面２４を貫通した貫通電極に導通したパッドを半導体基板裏面２４にパッドを形成する構成である。すなわち、従来は半導体素子表面２５のボンヂングパット１１にボンヂングワイヤ２６を接続していたが、図８に示すようにこのボンヂングワイヤ以外に裏面電極金属４０により接続することもでき、両面から接続することができるため、小さなチップ面積で、沢山の端子をもつことができて、コスト低減、チップ面積縮小、高速動作が可能となる。特に、従来の貫通電極と比べ、本発明の貫通電極は形成場所の自由度が高いため、コスト低減、チップ面積縮小、高速動作をより実現することができる。(Fourth Embodiment of the Present Invention)
A semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 8 shows a stacked state diagram of the semiconductor device according to the present embodiment.
The semiconductor element according to the present embodiment has the same structure as the semiconductor element according to the first embodiment, and in addition to the pads on the front surface 25 of the semiconductor element, the through electrodes penetrating the back surface 24 of the semiconductor substrate are electrically connected. The pad is formed on the back surface 24 of the semiconductor substrate. That is, conventionally, the bonding wire 26 was connected to the bonding pad 11 on the surface 25 of the semiconductor element, but as shown in FIG. Since they can be connected, they can have many terminals with a small chip area, which enables cost reduction, chip area reduction, and high-speed operation. In particular, compared with the conventional through electrode, the through electrode of the present invention has a high degree of freedom in the formation place, so that cost reduction, chip area reduction, and high speed operation can be further realized.

図８に従い説明すると、同図中の左図のようにチッフ゜単体をボード１８に実装して、裏面電極金属４０からと表面ボンヂングパッド１１からとの両側から信号、電源の供給が可能であり、多ピン半導体に応用すると高速、低価格が実現できる。同図中の中央図は半導体素子を積層して裏面電極金属４０及びボンヂングパッド１１両方を使用した例であり、同図中の右図は積層して貫通電極を通して下部の信号を上部に、上部の信号を下部に伝える結線方法の例である。これにより、両側から信号、電源供給が可能となる。
なお、図８に示すように、複数の本実施形態に係る半導体素子を縦に積層して、半導体素子間の信号のやりとり、若しくは上（下）に位置する半導体素子に繋がる配線を、本発明の貫通電極を通して行わせることもでき、簡単に積層構造半導体が実現し、コスト低減、高密度実装、高速動作、高信頼度のシステムが実現できる。Explaining with reference to FIG. 8, as shown in the left figure of FIG. 8, a chip alone is mounted on the board 18, and signals and power can be supplied from both sides of the back surface electrode metal 40 and the front surface bonding pad 11. When applied to multi-pin semiconductors, high speed and low price can be realized. The center diagram in the figure is an example in which semiconductor elements are laminated and both the back surface electrode metal 40 and the bonding pad 11 are used. The right diagram in the figure is laminated and the lower signal is passed through the through electrode to the upper signal, It is an example of a wiring method for transmitting a signal from the upper part to the lower part. This enables signals and power to be supplied from both sides.
As shown in FIG. 8, a plurality of semiconductor elements according to the present embodiment are vertically stacked, and signals are exchanged between the semiconductor elements, or wirings connected to the upper (lower) semiconductor elements are provided in the present invention. It is also possible to realize through a through electrode, and to easily realize a laminated structure semiconductor, and to realize a system of cost reduction, high-density mounting, high-speed operation, and high reliability.

（本発明の第５の実施形態）
本発明の第５の実施形態に係る半導体素子について図９又は図１０に基づき説明する。図９は本実施形態に係る半導体素子の組み立て実装構造の断面図、図１０は本実施形態に係る半導体素子をCCDに適用した実装構造の断面図を示す。より詳しくいえば、例えば、高速ＣＰＵ（Central Processing Unit）等の半導体素子の組み立て実装構造である。
本実施形態に係る半導体素子においては、前記第４の実施形態に係る半導体素子と同様に構成され、加えて前記半導体素子表面２５のパッドを形成しない構成である。(Fifth Embodiment of the Invention)
A semiconductor element according to the fifth embodiment of the present invention will be described with reference to FIG. 9 or 10. FIG. 9 is a sectional view of a semiconductor device assembled and mounted structure according to the present embodiment, and FIG. 10 is a sectional view of a mounting structure in which the semiconductor device according to the present embodiment is applied to a CCD. More specifically, for example, it is an assembled mounting structure of a semiconductor element such as a high-speed CPU (Central Processing Unit).
The semiconductor element according to the present embodiment has the same configuration as the semiconductor element according to the fourth embodiment, and additionally has no pad on the surface 25 of the semiconductor element.

この構成によれば、信号、電源などの端子を全て、半導体基板１の裏面の本発明貫通電極から供給することにより、半導体素子表面２５にはボンヂングパッド１１等の絶縁物開口が無く、電極、ボンヂングワイア２６等の積層物が無い構造となり、図９に示すように半導体素子表面２５に直接熱放散板２３を取り付けることができる。図１４の従来方式では裏面を放熱板２３に接着していたが、本実施形態の場合表面接着であるため、半導体素子表面２５のトランジスタ（Tr.）２からの発熱を効率よく逃がすことができる。また、CCD、MOS等のセンサーに本実施形態に係る半導体素子を適用すれば、図１０に示すように、従来のようにボンヂングワイヤ２６がないため半導体表面とレンズなどの距離を短く出来てシステムの小型化を計ることができる。CCD、MOSの受光部は半導体素子表面２５が光源方向に透明な透過材料２７で保護される必要がある。レンズ２９と半導体素子表面２５の距離を短くして短焦点光学系を構成するには、図１０のような構成により実現することが出来る。   According to this configuration, all terminals for signals, power supplies, etc. are supplied from the through electrodes of the present invention on the back surface of the semiconductor substrate 1, so that the semiconductor element surface 25 does not have an insulating material opening such as the bonding pad 11 and the like. Since there is no laminated body such as the bonding wire 26, the heat dissipation plate 23 can be directly attached to the semiconductor element surface 25 as shown in FIG. In the conventional method of FIG. 14, the back surface is adhered to the heat dissipation plate 23, but in the case of the present embodiment, since it is surface adhesion, heat generated from the transistor (Tr.) 2 on the semiconductor element surface 25 can be efficiently dissipated. .. Further, when the semiconductor device according to the present embodiment is applied to a sensor such as a CCD or a MOS, as shown in FIG. 10, since the bonding wire 26 is not provided unlike the conventional case, the distance between the semiconductor surface and the lens can be shortened. The system can be miniaturized. In the light receiving portion of the CCD or MOS, the semiconductor element surface 25 needs to be protected by a transparent material 27 which is transparent in the light source direction. In order to shorten the distance between the lens 29 and the surface 25 of the semiconductor element to configure the short focus optical system, the configuration as shown in FIG. 10 can be realized.

（本発明の第６の実施形態）
本発明の第６の実施形態に係る半導体素子について図１１または図１２に基づき説明する。図１１は本実施形態に係る半導体素子の貫通電極構造の断面図、図１２は本実施形態に係る半導体素子の積層状態図を示す。
図１１において本実施形態に係る半導体素子においては、トランジスタ（Tr.）２等を形成せず金属配線のみ形成して半導体インターポーザーとして用いる構成である。本実施形態に係る半導体インターポーザーはその半導体基板１の表面にはトランジスタ（Tr.）２が形成されずに金属配線だけが形成されており、表面（裏面）上に、半導体素子が実装された構造にすることができ、すなわち、半導体インターポーザーに本発明貫通電極を用いた構造となっており、これにより半導体インターポーザーからの電極取出しが簡単になり、低コスト、システムの小型化が可能になる。(Sixth Embodiment of the Present Invention)
A semiconductor device according to the sixth embodiment of the present invention will be described based on FIG. 11 or FIG. FIG. 11 is a cross-sectional view of the through electrode structure of the semiconductor device according to this embodiment, and FIG. 12 is a stacking state diagram of the semiconductor device according to this embodiment.
In the semiconductor element according to the present embodiment shown in FIG. 11, the transistor (Tr.) 2 and the like are not formed and only metal wiring is formed to be used as a semiconductor interposer. In the semiconductor interposer according to the present embodiment, the transistor (Tr.) 2 is not formed on the surface of the semiconductor substrate 1, only the metal wiring is formed, and the semiconductor element is mounted on the surface (back surface). It can be structured, that is, the structure is such that the through electrode of the present invention is used for the semiconductor interposer, which makes it easy to take out the electrode from the semiconductor interposer, and enables low cost and downsizing of the system. Become.

本実施形態に係る半導体インターポーザーの表面と裏面に、前記各実施形態に係る半導体素子が配置されて実装された半導体システムとすることで、半導体インターポーザーの表面と裏面を貫通する貫通電極を持つことにより、インターポーザーの表面と裏面に半導体素子を実装することが可能となり、実装密度の向上が計れる。
図１２を用いて本発明の半導体インターポーザーの表面及び裏面両面に半導体素子を実装した例を示す。貫通電極３０、３１、３２を有する半導体インターポーザー４９の上面に、DRAM５０及びFlash５１を積層し、裏面には、論理LSI５２、アナログLSI５３及びドライバーIC５４を実装している。上部積層メモリ群と下部実装LSIとは、半導体インターポーザー４９内の貫通電極で直接繋がる場合もあるし、半導体インターポーザー４９上の配線で繋がる場合もあり、自由な結線配線が可能となる。By providing a semiconductor system in which the semiconductor element according to each of the above-described embodiments is arranged and mounted on the front surface and the back surface of the semiconductor interposer according to the present embodiment, a through electrode penetrating the front surface and the back surface of the semiconductor interposer is provided. As a result, semiconductor elements can be mounted on the front and back surfaces of the interposer, and the mounting density can be improved.
An example in which semiconductor elements are mounted on both front and back surfaces of the semiconductor interposer of the present invention will be described with reference to FIG. The DRAM 50 and the Flash 51 are stacked on the upper surface of the semiconductor interposer 49 having the through electrodes 30, 31, 32, and the logic LSI 52, the analog LSI 53, and the driver IC 54 are mounted on the back surface. The upper laminated memory group and the lower mounting LSI may be directly connected by a through electrode in the semiconductor interposer 49, or may be connected by a wiring on the semiconductor interposer 49, which allows free connection wiring.

（その他の実施形態）
前記各実施形態においては、上記貫通電極の説明上は、P型Siの半導体基板１を用いたCMOS構造を例題に示したが、N型Siの半導体基板１を用いた場合も同様の構造が可能であり、NMOS構造、PMOS構造、バイポーラ構造、Bi-CMOS構造でも同様の貫通電極構造が可能である。半導体基板１がSiでなく、化合物半導体（ガリウム砒素、インヂウムアンチモン等）でも同様の構造が可能であり、同様の効果が得られることは明白である。(Other embodiments)
In each of the above-mentioned embodiments, the CMOS structure using the P-type semiconductor substrate 1 is shown as an example in the description of the through electrode, but the same structure is obtained when the N-type semiconductor substrate 1 is used. This is also possible, and the same through electrode structure is possible even in the NMOS structure, the PMOS structure, the bipolar structure, and the Bi-CMOS structure. It is obvious that the semiconductor substrate 1 can be made of a compound semiconductor (gallium arsenide, indium antimony, etc.) instead of Si, and the same structure can be obtained, and the same effect can be obtained.

前記半導体素子の積層を説明した各実施形態においては、裏面電極金属４０と表面電極金属を分けて説明を行ったが、完成時には同一の物であり、図１、図４の完成図で示した裏面電極金属４０は、裏面には付けずに、実装時に、下部の半導体素子（積層構造）、ボード、インターポーザー等の表面に電極金属を装着しておき、その上から実装したい半導体素子を取り付け（圧着、熱圧着等）しても良い。   Although the back electrode metal 40 and the front electrode metal are separately described in the respective embodiments for explaining the stacking of the semiconductor elements, they are the same when completed, and are shown in the completed views of FIGS. 1 and 4. The back surface electrode metal 40 is not attached to the back surface, but at the time of mounting, the electrode metal is attached to the surface of the lower semiconductor element (laminated structure), board, interposer, etc., and the semiconductor element to be mounted is attached from above. (Crimping, thermocompression, etc.) may be used.

Claims (18)

単結晶半導体基板の表面から裏面までを貫通した貫通電極が形成され、当該貫通電極が半導体基板表面より上層の多層金属配線層に到達せずに形成されている半導体素子。 A semiconductor element in which a through electrode penetrating from the front surface to the back surface of a single crystal semiconductor substrate is formed, and the through electrode does not reach a multilayer metal wiring layer above the surface of the semiconductor substrate. 単結晶半導体基板の表面から裏面までを貫通した貫通電極が形成され、当該貫通電極が半導体基板表面より上層の多層金属配線層を貫通することなく形成されている半導体素子。 A semiconductor element in which a through electrode penetrating from the front surface to the back surface of a single crystal semiconductor substrate is formed, and the through electrode is formed without penetrating a multilayer metal wiring layer above the surface of the semiconductor substrate. 前記請求項１に記載の半導体素子において、
前記貫通電極が前記多層金属配線層の金属材料よりも高い融点の金属材料からなり、当該貫通電極と半導体基板間に絶縁膜が形成されていることを
特徴とする半導体素子。The semiconductor device according to claim 1,
A semiconductor element, wherein the through electrode is made of a metal material having a melting point higher than that of the metal material of the multilayer metal wiring layer, and an insulating film is formed between the through electrode and the semiconductor substrate. 前記請求項２に記載の半導体素子において、
前記貫通電極が前記多層金属配線層の金属材料よりも高い融点の金属材料からなり、当該貫通電極と半導体基板間に絶縁膜が形成されていることを
特徴とする半導体素子。The semiconductor device according to claim 2, wherein
A semiconductor element, wherein the through electrode is made of a metal material having a melting point higher than that of the metal material of the multilayer metal wiring layer, and an insulating film is formed between the through electrode and the semiconductor substrate. 前記請求項１ないし４のいずれかに記載の半導体素子において、
前記貫通電極は同一チップ内に複数あり、一の貫通電極が他の貫通電極の表面形状と異なることを
特徴とする半導体素子。The semiconductor device according to any one of claims 1 to 4,
The semiconductor element is characterized in that a plurality of the through electrodes are provided in the same chip, and one through electrode has a surface shape different from that of another through electrode. 前記請求項１ないし４のいずれかに記載の半導体素子において、
前記半導体基板の表面上部に貫通電極埋め込み金属材料と異なる金属配線が形成され、半導体の配線領域又は周辺領域に貫通電極が形成されていることを
特徴とする半導体素子。The semiconductor device according to any one of claims 1 to 4,
A semiconductor element, wherein a metal wiring different from a metal material for embedding a through electrode is formed on an upper surface of the semiconductor substrate, and a through electrode is formed in a wiring region or a peripheral region of the semiconductor. 前記請求項１ないし４のいずれかに記載の半導体素子において、
前記貫通電極から半導体基板の表面及び／又は裏面で電極取り出しを行うための取り出し口が１つの貫通電極につき複数の取り出し口又は電極を有することを
特徴とする半導体素子。The semiconductor device according to any one of claims 1 to 4,
A semiconductor device having a plurality of outlets or electrodes per one through electrode for taking out electrodes from the through electrode on the front surface and/or the back surface of the semiconductor substrate. 前記請求項１ないし４のいずれかに記載の半導体素子において、
前記半導体基板裏面の貫通電極に金（Au）等の基板とオーミック接続の良い金属ボールを配設することを
特徴とする半導体素子。The semiconductor device according to any one of claims 1 to 4,
A semiconductor element characterized in that a metal ball, such as gold (Au), having a good ohmic contact with a substrate is provided on the through electrode on the back surface of the semiconductor substrate. 前記請求項１ないし４のいずれかに記載の半導体素子において、
半導体素子表面のパッドの他に前記半導体基板裏面を貫通した貫通電極に導通したパッドを半導体基板裏面に形成することを
特徴とする半導体素子。The semiconductor device according to any one of claims 1 to 4,
In addition to the pads on the front surface of the semiconductor element, a pad electrically connected to a through electrode penetrating the back surface of the semiconductor substrate is formed on the back surface of the semiconductor substrate. 前記請求項９に記載の半導体素子において、
前記半導体素子表面のパッドを形成しないことを
特徴とする半導体素子。The semiconductor device according to claim 9,
A semiconductor device characterized in that no pad is formed on the surface of the semiconductor device. 前記請求項９に記載の半導体素子を最上層に配置し、下層に前記請求項１ないし４のいずれかに記載の半導体素子を配置して積層構造としていることを
特徴とする積層構造半導体システム。A semiconductor device having a laminated structure, wherein the semiconductor element according to claim 9 is arranged in an uppermost layer and the semiconductor element according to any one of claims 1 to 4 is arranged in a lower layer to form a laminated structure. 前記請求項１０に記載の半導体素子を最上層に配置し、下層に前記請求項１ないし４のいずれかに記載の半導体素子を配置して積層構造としていることを
特徴とする積層構造半導体システム。A semiconductor device having a laminated structure, wherein the semiconductor element according to claim 10 is arranged in an uppermost layer and the semiconductor element according to any one of claims 1 to 4 is arranged in a lower layer to form a laminated structure. 前記請求項１ないし４のいずれかに記載の半導体素子表面にTr.を形成することなく金属配線のみ形成し、半導体基板裏面に貫通電極の取り出し電極のみ形成された構成であることを
特徴とする半導体インターポーザー。5. The structure according to claim 1, wherein only the metal wiring is formed without forming the Tr. on the surface of the semiconductor element and only the lead-out electrode of the through electrode is formed on the back surface of the semiconductor substrate. Semiconductor interposer. 前記請求項１３に記載の半導体インターポーザーの表面と裏面に、前記請求項１ないし４のいずれかに記載の半導体素子が配置されて実装されていることを
特徴とする半導体システム。A semiconductor system, wherein the semiconductor element according to any one of claims 1 to 4 is arranged and mounted on a front surface and a back surface of the semiconductor interposer according to claim 13. 半導体基板表面より上層の多層金属配線層の形成する前に、半導体基板を開孔し、孔周りの半導体基板の内壁に酸化膜を成膜し、高融点金属を当該貫通電極孔に充填することにより貫通電極を形成する半導体素子製造方法。 Before forming the multi-layered metal wiring layer above the surface of the semiconductor substrate, the semiconductor substrate is opened, an oxide film is formed on the inner wall of the semiconductor substrate around the hole, and the high melting point metal is filled in the through electrode hole. A method for manufacturing a semiconductor device, in which a through electrode is formed by the method. 前記請求項１５に記載の半導体素子製造方法において、前記半導体基板を開孔するための開口エッチングプロセス処理は、半導体基板表面のトランジスタ構成要素形成前の基板に対して行われることを
特徴とする半導体素子製造方法。16. The semiconductor element manufacturing method according to claim 15, wherein the opening etching process for opening the semiconductor substrate is performed on the substrate on the surface of the semiconductor substrate before forming the transistor constituent elements. Device manufacturing method. 前記請求項１６に記載の半導体素子製造方法において、
前記半導体基板を開孔するための開口エッチングプロセス処理は、半導体基板表面のトランジスタ構成要素形成後前記多層金属配線層形成前の基板に対して行われることを
特徴とする半導体素子製造方法。The semiconductor device manufacturing method according to claim 16,
A method of manufacturing a semiconductor device, wherein the opening etching process treatment for opening the semiconductor substrate is performed on the substrate after the formation of the transistor constituent elements on the surface of the semiconductor substrate and before the formation of the multilayer metal wiring layer. 前記請求項１５ないし１７のいずれかに記載の半導体素子製造方法において、
前記貫通電極形成時に半導体基板裏面まで貫通させずに所定の深さまでの貫通電極穴を形成し、後で半導体基板裏面を研削又は研磨することを
特徴とする半導体素子製造方法。The method of manufacturing a semiconductor device according to any one of claims 15 to 17,
A method of manufacturing a semiconductor element, wherein a through electrode hole is formed to a predetermined depth without penetrating to the back surface of the semiconductor substrate when forming the through electrode, and the back surface of the semiconductor substrate is ground or polished later.
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