JPH11168157A - Multi-chip semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a multi-chip semiconductor device whose planar area is small and which is superior in a heat dissipating property. SOLUTION: A multi-chip semiconductor device is constituted by laminating respective chips 11 , 12 , 13 provided with silicon substrates 2 on which elements are integrated and formed. A connecting substrate 311 on which conductive plugs 4 are formed inside respective through-holes is installed between the two upper and lower adjacent chips 11 , 12 . The chips 11 , 12 are connected electrically to each other via conductive plugs 4. A metal plate 32 whose thermal conductivity is larger than that of the connecting substrate 311 is installed inside the connecting substrate 311 in order to improve the heat dissipating property of the chips 11 , 12 . For the chips 12 , 13 , the chips 12 , 13 are connected with similar technique, and the heat dissipating property of the chips 12 , 13 is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multi-chip semiconductor device which is a semiconductor device using a plurality of chips.

[0002]

2. Description of the Related Art In recent years, large-scale integrated circuits (ICs) formed by integrating a large number of transistors, resistors, and the like on an important part of a computer or a communication device so as to achieve an electric circuit, and integrating them on a semiconductor substrate. Chips) are frequently used. For this reason, the performance of the entire device is greatly linked to the performance of the chip alone.

On the other hand, a so-called multi-chip semiconductor device using a plurality of chips to improve the performance of the entire device has been proposed. 19 to 24 show sectional views of a conventional multichip semiconductor device.

FIG. 19 shows, for example, a multi-chip semiconductor device of a type in which a plurality of chips 82 are arranged on a stacked wiring substrate 81 in a plane. In the drawing, reference numeral 83 denotes a solder bump.

[0005] FIG. 20 shows a state in which the surfaces are faced to each other (Face).
1 illustrates a multi-chip semiconductor device of a type in which chips are connected to each other as “to face”.

FIG. 21 shows a case where a plurality of chips 82 are
1 shows a multi-chip semiconductor device of a type in which the components are stacked and arranged.

FIG. 22 shows a multi-chip semiconductor device using wire bonding as a mounting method.
A pad (not shown) of the Si chip 91 is connected to a lead frame 94 of the laminated board 93 by a bonding wire 92.

FIG. 23 shows a mounting method of TAB (Tape A).
1 shows a multi-chip semiconductor device using the utomated bonding, in which a pad of a Si chip 91 has solder bumps 9.
5. Connected to pads (not shown) of the laminate 93 via TAB leads 96.

In FIGS. 22 and 23, reference numeral 97 denotes a socket, and 98 denotes a connector pin.

FIG. 24 shows a multi-chip semiconductor device using a flip chip as a mounting method. Pads 100 arranged in a grid on the entire surface of a Si chip 91 are:
The solder bumps 102 are connected to the pads 101 which are similarly arranged in a grid pattern on the entire surface of the laminated board 99.

In FIG. 24, reference numeral 103 denotes an epoxy resin-based adhesive containing a filler.
3 is filled between the Si chip 91 and the laminated board 99, and these 91 and 93 are tightly fixed. Also, 104, 10
Reference numerals 5 and 107 indicate pads, and 106 and 108 indicate solder bumps.

[0012]

However, these conventional multi-chip semiconductor devices have the following problems.

That is, the conventional multi-chip semiconductor device shown in FIG. 19 has a problem that the plane area of the device is large because a plurality of chips 82 are arranged on a plane.

In the conventional multi-chip semiconductor device shown in FIG. 20, since a plurality of chips 82 are stacked, there is no problem that the planar area of the device becomes large, but there is a problem that the number of stacked devices is limited to two. Another problem is that it is difficult to inspect the device.

In the conventional multi-chip semiconductor device shown in FIG. 21, since a plurality of chips 82 can be stacked, there is no problem that the planar area of the device becomes large or the number of stacked devices is limited to two. There is a problem that the bumps 83 on the chip 82 cannot be selectively melted, and it is difficult to repair the chip 82. Further, although the chip generates heat during the operation of the chip, the heat cannot be effectively released to the outside, so that there is a problem that the operating characteristics of the chip deteriorate and the life of the chip is shortened.

The conventional multi-chip semiconductor device shown in FIG. 22 uses a laminated board 93 to connect a narrow pitch pad of a highly integrated Si chip 91 to a lead frame 94 of the laminated board 93 by a bonding wire 92. It is necessary to form wiring thereon and to align the chip and the laminated board with high accuracy, which makes connection difficult.

In the conventional multi-chip semiconductor device shown in FIGS. 22 and 23, since the laminated plates 93 are connected to each other using the socket 97 and the connector pins 98, a certain height is required. There is a problem that the gap is large and integration in the vertical direction is difficult.

This kind of problem can be solved by using the conventional multi-chip semiconductor device shown in FIG.
4 has the following problems.

Since the shape of the solder bumps 102 is in the shape of a drum, when the integration of the Si chip 91 is further advanced and the sizes and pitch intervals of the pads 100 and 101 are further reduced, the Si chip 91 and the laminated board 99 are reduced. If the distance (connection distance) between them is not shortened and the diameter of the solder bump 102 is not reduced, a connection failure occurs in which the adjacent solder bumps 102 are short-circuited.

However, while the Si chip 91 is formed using a Si substrate, the laminated plate 99 is formed using a plastic substrate made of glass epoxy or the like, so that the Si chip 91 and the laminated plate 99 are formed. The thermal expansion coefficients differ from each other. As a result, when the connection distance is shortened, thermal distortion occurs in the solder bump 102, and fatigue fracture occurs due to repeated thermal cycles. The shorter the connection distance, the greater the thermal strain and the shorter the fatigue life. Therefore,
The shorter the connection distance, the lower the reliability of the connection between the Si chip 91 and the laminated board 99.

The adhesive 103 filled between the Si chip 91 and the laminated plate 99 has a function of reducing such thermal distortion, and therefore, SiO _2, which can make the coefficient of thermal expansion of both of them close, is a filler. It is mixed as.

The size of the filler is about 10 to 30 μm. However, if the connection distance is short, a portion where the adhesive 103 is not filled occurs.
And the reliability of the connection between the upper and lower Si chips 91 cannot be ensured as a result.

The present invention has been made in view of the above circumstances, and it is an object (first object) of the present invention that the plane area of the apparatus is small and the apparatus can be easily inspected. To provide a multi-chip semiconductor device.

Another object of the present invention (second object)
An object of the present invention is to provide a multi-chip semiconductor device having a small planar area and excellent heat dissipation.

Another object of the present invention (third object)
An object of the present invention is to provide a multi-chip semiconductor device having a small plane area and capable of easily performing repair.

Another object of the present invention (fourth object)
It is an object of the present invention to provide a multi-chip semiconductor device in which the planar area of the device is small and the reliability of connection between upper and lower chips can be ensured.

[0027]

Means for Solving the Problems [Structure] In order to achieve the first object, a multichip semiconductor device according to the present invention (Claim 1) includes a chip having a semiconductor substrate on which elements are integrated and formed. In a multi-chip semiconductor device formed by laminating a plurality of chips, two adjacent upper and lower chips are electrically connected to each other via a connection substrate provided therebetween, and a through hole is formed in the semiconductor substrate. The conductive plug formed in the through hole is connected to the connection substrate.

Here, the through-hole may be provided in one or both of the semiconductor substrates of the two chips.

In order to achieve the second object,
A multichip semiconductor device according to the present invention (Claim 2)
In a multi-chip semiconductor device in which a plurality of chips each having a semiconductor substrate on which elements are integrally formed are stacked, a connection substrate having a conductive plug formed in a through hole is provided between two adjacent upper and lower chips. And the two chips are electrically connected to each other via the conductive plug, and the connection substrate has higher heat dissipation than the chips.

Further, in another multi-chip semiconductor device according to the present invention (claim 3), in the multi-chip semiconductor device (claims 1 and 2), the connection substrate is formed of the chip It is characterized in that a substance having a higher heat dissipation property is selected.

Specifically, in the case of a Si chip,
As a constituent material of the connection substrate, an insulating material such as SiC or SiN is used.

In another multi-chip semiconductor device according to the present invention (claim 4), in the multi-chip semiconductor device (claims 1 and 2), the connection substrate may be a connection formed with the conductive plug. It is characterized by comprising a substrate main body and a high thermal conductivity member having higher thermal conductivity than the connection substrate main body.

More specifically, the constituent material of the connection substrate is Si
In the case of an insulating material such as C, the high thermal conductivity member is
A member made of a metal material such as W or Cu is used.

In another multichip semiconductor device according to the present invention (claim 5), in the multichip semiconductor device (claim 4), the high thermal conductivity member is formed inside the connection substrate body. A conductive plate.

Here, a conductive plate may be provided on the surface of the connection substrate. Further, conductive plates may be provided both inside and on the surface of the connection board.

In another multichip semiconductor device according to the present invention (claim 6), in the multichip semiconductor device (claim 4), the high thermal conductivity member is provided on a surface of the connection board main body. Characterized in that it is a radiation fin.

Here, the heat radiation fins may be provided on all the connection substrates, or may be provided only on a specific connection substrate, for example, only the connection substrate having low heat radiation.

In order to achieve the third object,
A multi-chip semiconductor device according to the present invention (claim 7)
In a multi-chip semiconductor device in which a plurality of chips each having a semiconductor substrate on which elements are integrally formed are stacked, a connection substrate having a conductive plug formed in a through hole is provided between two adjacent upper and lower chips. And the two chips are electrically connected to the conductive plugs via bumps, respectively, and the connection substrate has a heat generating portion.

Another multi-chip semiconductor device according to the present invention (claim 8) is characterized in that, in the multi-chip semiconductor device (claim 7), the heat-generating portions of each connection board can be independently controlled.

In order to achieve the fourth object,
Multi-chip semiconductor device according to the present invention (Claim 12)
In a multichip semiconductor device formed by stacking a plurality of chips each having a semiconductor substrate on which elements are integrally formed, a connection formed by forming a conductive plug in a through hole between two upper and lower adjacent chips. A substrate is provided, and the two chips are electrically connected to each other via the conductive plug, and the connection substrate has higher heat dissipation than the chips, and a constituent material of the connection substrate is the semiconductor substrate. Is characterized by having a coefficient of thermal expansion substantially the same as that of

In order to achieve the fourth object,
Another multi-chip semiconductor device according to the present invention (Claim 1)
3) In a multichip semiconductor device formed by stacking a plurality of chips each having a semiconductor substrate on which elements are integrally formed, a conductive plug is formed in a through hole between two adjacent upper and lower chips. Wherein the two chips are electrically connected to each other via the conductive plug, and a constituent material of the connection substrate has substantially the same coefficient of thermal expansion as that of the semiconductor substrate. And

[Operation] According to the first aspect of the present invention (claim 1), since a plurality of chips are stacked, unlike a conventional multi-chip semiconductor device in which a plurality of chips are arranged in a plane, the device has a flat surface. The area can be reduced.

According to the first aspect of the present invention, if the chip on which the conductive plug is formed is arranged at the top or bottom, the test probe can be easily applied to the conductive plug. Therefore, the inspection of the apparatus can be easily performed.

According to the second invention (claims 2 to 6),
For the same reason as the first present invention (claim 1), the plane area of the device can be reduced.

Further, according to the second aspect of the present invention, since the connection substrate has higher heat radiation than the chip, the heat of the chip can be effectively released to the outside via the connection substrate. By improving the heat dissipation as described above, it is possible to prevent deterioration of the operating characteristics of the chip and shortening of the life of the chip due to heat generation of the chip during operation of the chip.

According to the third invention (claims 7 to 9),
For the same reason as the first present invention (claim 1), the plane area of the device can be reduced.

According to the third aspect of the present invention, the defective chip can be separated from the connection substrate by melting the bumps connected to the defective chip by the heating portion of the connection substrate. Repair can be performed easily. In particular, in the case of the present invention (claim 8), since the heat generating portion of each connection board can be controlled independently, the chip can be repaired more easily.

According to the fourth invention (claims 12 to 14), the plane area of the device can be reduced for the same reason as in the first invention (claim 1).

According to the fourth aspect of the present invention, since the thermal expansion coefficient of the constituent material of the connection substrate is substantially equal to that of the constituent material of the semiconductor substrate, the bump is used to connect the connection substrate and the semiconductor substrate. However, almost no thermal distortion occurs in the bumps.

Therefore, even if the integration of the chip is further advanced and the distance between the chip and the connection substrate is reduced,
The reliability of the connection between the connection substrate and the semiconductor substrate can be ensured, and thus the reliability of the connection between the upper and lower chips can be ensured.

Further, since the coefficient of thermal expansion of the constituent material of the connection substrate is substantially equal to that of the constituent material of the semiconductor substrate, it is not necessary to use an adhesive containing a filler in order to make the coefficients of thermal expansion close to each other.

Therefore, even if the integration of the chip is further advanced and the distance between the connection substrate and the semiconductor substrate is reduced, no portion is not filled with the adhesive, and the connection between the chip and the connection substrate does not occur. And the reliability of the connection between the upper and lower chips can be ensured.

Table 1 shows the thermal conductivity and the coefficient of linear expansion of the main materials used for the constituent materials of the semiconductor substrate and the connection substrate used for the chip.

[0054]

[Table 1]

As the constituent material of the connection substrate in the present invention, for example, when the constituent material of the semiconductor substrate is Si, the same material Si is the best in terms of relaxation of thermal strain, but the linear expansion coefficient is almost the same as that of Si. Equal silicon carbide (SiC) and aluminum nitride (AlN) may be used. Since these have higher thermal conductivity than Si, they are also excellent in heat dissipation.

When the constituent material of the semiconductor substrate used for the chip is a compound semiconductor, for example, gallium arsenide (GaAs)
In the case of s), GaAs, beryllia (BeO), and alumina (Al ₂ O ₃ ) are suitable.

The extent to which the difference in thermal expansion can be tolerated depends on the size and pitch of the connection terminals (pads) and the size of the connection substrate. To ensure this, the difference between the coefficient of thermal expansion of the constituent material of the connection substrate and that of the constituent material of the semiconductor substrate is ± 5.
It is preferably within 0 × 10 ⁻⁶ .

[0058]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a cross-sectional view of the multi-chip semiconductor device according to the embodiment.

[0060] The multi-chip semiconductor device, two chips 1 _1, 1 ₂ has a configuration that is connected via the laminated wiring board 9 made of ceramic. Chips 1 ₁ and 1 ₂
It can be roughly divided into a silicon substrate 2 on which elements are integrated and formed.
And a multilayer wiring layer 3 for connecting the elements in a predetermined relationship.

The pads 6 provided on the multilayer wiring layer 3 of the chip ₁ are electrically connected to the pads 6 provided on the laminated wiring board 9 via the solder bumps 8. This pad 6
Other pads 6 provided on the multilayer wiring board 9 are electrically connected to is electrically connected to the pad 6 formed on the multilayer wiring layer 3 of the chip 1 _2. In this way, the upper and lower two chips _1, the chip 1 ₂ will be through the multilayer wiring board 9 provided therebetween are electrically connected to each other.

[0062] Also, the chip 1 _2, through plugs fourth conductive penetrating the silicon substrate 2 (conductive plugs) are provided. The through plug 4, the pad 6 is provided on the chip 1 _2, via the bumps 8 thereon, and is electrically connected to the pad 6 provided in the multilayer wiring board 9.

The through plug 4 is formed outside the element formation region, and an insulating film 5 is provided between the through plug 4 and the silicon substrate 2 (through hole). The insulating film 5 and the through plug 4 form a connection plug.

[0064] Further, the multilayer wiring layer 3 of the chip 1 ₂ silicon region of the silicon substrate 2 on the opposite side, that is a region other than the through plug 4 is covered with an insulating film 7. Such a through plug 4 has an effect of promoting heat radiation.

[0065] As another means of promoting heat radiation, it is formed of a material having high thermal conductivity and the like than the multilayer wiring board 9 chips 1 _1, 1 _2. Specifically, in the case of a Si chip, an insulating material such as SiC or SiN can be used. Further, a metal plate may be embedded inside as described in the second embodiment.

According to [0066] this embodiment, since through the multilayer wiring board 9 on the chip 1 ₁ are stacked chips 1 _2, unlike the conventional multi-chip semiconductor device which plane position a plurality of chips, device Can be reduced in planar area.

Further, according to the present embodiment, the through plug 4 which is electrically connected to the chip 1 ₁ via a multilayer wiring board 9
Due to the use of chip 1 ₂ having the through plugs 4
The inspection of the device can be performed by applying an inspection probe to the device. Here, since the through plug 4 is exposed on the back surface of the semiconductor substrate 2, an inspection probe can be easily applied to the through plug 4. Therefore, according to the present embodiment, the inspection of the apparatus can be easily performed.

Although the case of two chips has been described here, in the present embodiment, the chips are connected to each other by the laminated wiring board 9, so that the face-to-F connection is used.
Unlike a conventional multi-chip semiconductor device in which chips are connected to each other by ace, there is no problem that the number of stacked chips is limited to two.

Therefore, according to the present embodiment, it is possible to realize a multi-chip semiconductor device in which the planar area of the device is small, the device can be easily inspected, and the number of stacked layers is not limited to two.

[0070] In the present embodiment, is provided through the plug 4 in the chip 1 _2, it may be provided on the chip 1 _1, or chip 1 _1, 1 may be provided in both _two.

(Second Embodiment) FIGS. 2 and 3 are process sectional views showing a method of forming a through plug 4 of the multi-chip semiconductor device of FIG. Note that, in the following drawings, the same reference numerals as those described above indicate the same or corresponding portions, and a detailed description thereof will be omitted.

First, as shown in FIG. 2A, a silicon substrate 2 is prepared. This silicon substrate 2 may be at any stage before, after, after or after element isolation.

In the figure, in the region surrounded by a circle, before forming the element,
After the STI element isolation, a protective film (B
2 shows a substrate after PSG is formed (after element formation). After forming the element, there is a case after forming another wiring.

In the course of element formation, for example, the next step after forming a necessary well on the substrate surface by ion implantation and the next step after forming a gate electrode can be mentioned.

Next, as shown in FIG. 2B, after a mask pattern 11 made of SiO ₂ and having a thickness of 1 μm is formed on the silicon substrate 2, the etching gas is RIE of an F-based gas.
The silicon substrate 2 is selectively etched using the mask pattern 11 as a mask to form a groove 12 having a depth of 100 μm on the surface of the silicon substrate 2. This groove 12 eventually becomes a through hole.

Here, the mask pattern 11 made of SiO ₂ is used as the constituent material. Instead, the mask pattern made of a material having a high selectivity to Si, such as Al or Al ₂ O ₃ , is used instead. Eleven may be used.

Further, the processing technique for forming the groove 12 (through hole) is not limited to RIE.
Wet etching, ultrasonic machining, and electric discharge machining can also be used. Further, the above processing techniques may be appropriately combined. A method in which RIE or optical etching is combined with wet etching will be described later.

Next, as shown in FIG. 2C, after removing the mask pattern 11, a 100 nm thick SiO
_Two films and a Si ₃ N ₄ film having a thickness of 100 nm are sequentially deposited by using the LPCVD method to form an insulating film 5 having a laminated structure composed of a SiO ₂ film and a Si ₃ N ₄ film. Note that a single-layer insulating film may be used instead of the insulating film 5 having a stacked structure.

Next, as shown in FIG. 2D, a low-resistance polycrystalline silicon film 4 doped with an impurity such as B, which becomes a through plug, is formed on the entire surface to a thickness overflowing from the groove 12. Then, the trench 12 is filled with the polycrystalline silicon film 4.

The method for forming the polycrystalline silicon film 4 is as follows.
For example, a CVD method or a sputtering method is used. When a metal film is used instead of the polycrystalline silicon film 4, a plating method can be used.

Although the impurity-doped polycrystalline silicon film 4 is used here as the conductive film serving as the through plug, an amorphous silicon film doped with impurities may be used instead. Furthermore, W film, Mo
A metal such as a film, a Ni film, a Ti film, or a metal silicide film thereof may be used.

Next, as shown in FIG. 3A, the polycrystalline silicon film 4 and the insulating film 5 are retracted by using a method such as a CMP method or an etch back method until the surface of the silicon substrate 2 is exposed. . As a result, a structure in which the polycrystalline silicon film (through plug) 4 is buried in the groove 12 via the insulating film 5 is formed.

Next, as shown in FIG. 3B, a multilayer wiring layer 3 is formed on the silicon substrate 2 on the side where the through plugs 4 are formed. Before forming the multilayer wiring layer 3, element isolation and element formation are performed. Then, the multilayer wiring layer 3
After a groove is formed on the surface of the substrate, a pad 6 is formed in the groove.

Next, as shown in FIG. 3C, the surface (hereinafter referred to as the back surface) of the silicon substrate 2 opposite to the side where the through plug 4 is formed is exposed to the insulating film 5 at the bottom of the groove 12. Until the silicon substrate 2 is retracted. Silicon substrate 2
The retreat (thinning) is performed by, for example, a method using a processing technique of CMP, chemical polishing, mechanical polishing, wet etching, plasma etching or gas etching, or a method combining these processing techniques.

Next, as shown in FIG. 3D, the back surface of the silicon substrate 2 is selectively etched until the insulating film 5 on the side wall of the groove 12 above the insulating film 5 at the bottom of the groove 12 is exposed. I do. For this etching, for example, CDE, RIE or wet etching is used.

Next, as shown in FIG.
An insulating film 7 (second insulating film) made of SiO ₂ is deposited on the back surface of the silicon substrate 2 by using the VD method.

When a low-temperature process is required, a coating film such as an SOG film may be used instead of the insulating film 7 made of SiO ₂ . When it is desired to reduce the stress applied to the silicon substrate ₂ , instead of SiO ₂ ,
It is preferable to use an insulating film made of an organic material such as polyimide.

Next, as shown in FIG. 3E, the through plug 4 and the insulating films 5, 7 are polished by the CMP method until the back surface of the silicon substrate 2 is exposed.

As a result, a structure is formed in which the through plug (polycrystalline silicon film 4) is buried in the through hole (groove 12) and the silicon region on the back surface of the silicon substrate 2 is covered with the insulating film 7.

As described above, in the present embodiment, the grooves 1 not penetrating the silicon substrate 2 are formed on the surface of the silicon substrate 2.
After forming the silicon substrate 2, the silicon substrate 2 and the like are polished from the back surface to form a structure in which the through holes (grooves 12) are filled with the through plugs (polycrystalline silicon film 4).

Therefore, according to the present embodiment, even if the original silicon substrate 2 is thick (usually thick), it is not necessary to form a deep through-hole, so that the through-hole (groove 12) is connected to the connection plug (multiple). A structure embedded with the crystalline silicon film 4 and the insulating film 5) can be easily formed.

If it is not necessary to cover the silicon region on the back surface with the insulating film 7, the silicon substrate 2 and the insulating film 5 are polished until the polycrystalline silicon film 4 is exposed in the step of FIG. This completes a structure in which the through holes (grooves 12) are filled with the connection plugs (polycrystalline silicon film 4, insulating film 5).

The polishing (retreating) of the silicon substrate 2 is performed as follows.
It is preferably performed after the silicon substrate 2 is cut out from the wafer. This is because wafers are generally large and have low mechanical strength, making it difficult to perform uniform polishing (retreat).

FIG. 4 shows sectional views of connection plugs having various structures. This is a cross-sectional view corresponding to the step of FIG. In the drawings, the multilayer wiring layer 3, the pads 6, and the insulating film 7 are omitted.

FIG. 4A shows a connection plug having a low stress film 13.

That is, the outside of the connection plug is formed of the conductive film 4a, and the inside is the low stress film 13 having a smaller difference in thermal expansion coefficient from the semiconductor substrate 2a than the conductive film 4a.
It is composed of

The low stress film 13 is an insulating film, a semiconductor film,
Any of a metal film may be used. By using such a connection plug, the stress applied to the silicon substrate 2 can be reduced.

When the constituent material (silicon) of the through plug (polycrystalline silicon film 4) and the semiconductor substrate (silicon substrate 2) is the same as in this embodiment, such a structure is not always necessary. Absent.

FIG. 4B shows a connection plug having a cap metal film 14. That is, the polycrystalline silicon film 4 is formed only up to a certain depth of the through hole, and a cap metal film 14 is formed on the upper surface of the polycrystalline silicon film 4 so as to fill the through hole. . FIG. 4C shows a connection plug using a cap insulating film 15 instead of the cap metal film 14.

FIG. 5 is a process sectional view showing another method of forming the groove 12. As shown in FIG. This is RIE or photo etching,
This is a formation method combining wet etching.

First, as shown in FIG. 5A, after a mask pattern 11 is formed on a silicon substrate 2 having a principal surface of {100}, the silicon substrate 2 is etched using the mask pattern 11 as a mask. , the cross-sectional shape to form a groove 12 ₁ of the rectangle.

Here, RIE or photoetching (photochemical etching, photoablation (photoablation) etching) is used as the etching. Particularly light etching is fast etching, so has the advantage of low damage, it is suitable for forming a deep groove 12 _1. In the case of photochemical etching, for example, C is used as an etching gas.
L ₂ gas and ultraviolet light are used as excitation light.

Next, as shown in FIG. 5B, the silicon substrate 2 is wet-etched using the mask pattern 11 as a mask to expose the {111} plane. As a result, the cross-sectional shape grooves 12 ₂ triangles are formed. As an etching solution, for example, a KOH solution having a temperature of 60 to 90 ° C. is used.

[0104] Then, as shown in FIG. (B), the groove 12 _2, for example, disposing Ni, Ti, Zr, Hf, the metal ball 16 of the V or the like. Specifically, the metal ball 16 is inserted into the groove 1
Placing the portion of 2 ₂ at the bottom.

Next, as shown in FIG. 5C, the metal balls 16 and the silicon substrate 2 are reacted by heat treatment.
Groove 12 _second metal silicide film 1 on the silicon substrate 2 at the bottom
7 is formed.

[0106] Next, as shown in FIG. 5 (d), is selectively removed by etching the metal silicide film 17, to form a deeper groove 12 _3. Finally, after forming the insulating film and embedding the metal, the back surface of the substrate is polished to obtain a deep through-hole.

By gradually increasing the depth of the hole as described above, a deep hole can be easily formed, and therefore a deep through hole can be easily formed.

FIG. 6 shows another method of forming a through plug.

FIG. 6A shows a method of applying a conductive paste 18 as a through plug on the entire surface, fluidizing the conductive paste 18 by heat treatment, and embedding the conductive paste 18 in the groove. After that, the extra conductive paste 18 outside the groove is removed by using a CMP method or the like.

FIG. 6B shows a state in which a plurality of metal fine particles 19 as a through plug are deposited on the entire surface, and the inside of the groove is buried with the fine particles 19, and then the extra metal fine particles 19 outside the groove are removed by CMP or the like. And remove it.

Note that, instead of the metal fine particles 19, a solvent (suspension) in which metal particles are dispersed may be used.

FIG. 6C shows that a silicon film 20 is deposited on the entire surface, and then a high-melting point metal film (not shown) such as a Ti film is deposited on the silicon film 20. A method of forming a silicide film 21 is shown. After that, the extra metal silicide film 21 outside the groove is removed by using a CMP method or the like.

The silicon film is conformally deposited on the insulating film. Therefore, even if the groove is deep, the silicon film 20
Covers the entire edge film 5 in the groove, so that the metal silicide film 21 covering the entire side and bottom surfaces of the groove can be formed. If a cavity remains in the groove, it may be filled with a low stress film, for example.

FIG. 7 shows still another method of forming a through plug.

First, as shown in FIG. 7A, a silicon film 22 is formed which covers the entire side and bottom surfaces of the groove 12 but does not fill the inside of the groove 12. Thereafter, Ni grains 23 (metal balls) having a diameter of about 10 μm are arranged in the groove 12 as shown in FIG.

Next, as shown in FIG. 7B, the silicon film 22 and the Ni grains 23 react by heat treatment,
A Ni silicide film 24 as a through plug is formed therein. Here, since there is no sufficient amount of the silicon film 22 and the Ni grains 23 in the trench 12, a cavity remains on the Ni silicide film 24.

Finally, as shown in FIG. 7C, after an insulating film or a metal film serving as a cap film 25 is deposited on the entire surface, the insulating film or the metal film is polished, and the upper portion of the Ni silicide film 24 is polished. Is filled with a cap film 25.

The method for forming the through plug is the same as the method described above (CVD method, sputtering method, plating method, method using conductive paste, method using metal fine particles, method using metal balls, The method is not limited to a method using a turbid liquid, but various methods such as a method of appropriately combining these methods are possible.

(Third Embodiment) FIG. 8 shows a third embodiment of the present invention.
FIG. 3 is a cross-sectional view of the multi-chip semiconductor device according to the embodiment. FIG. 9 is a plan view of a connection substrate of the multi-chip semiconductor device of FIG.

The feature of this multi-chip semiconductor device is that two upper and lower adjacent chips are electrically connected to each other via a connection substrate having a through plug and a heater.

[0121] That is, the connection pads 6 provided on the multilayer wiring layer 3 of the chip 1 ₁ via the solder bumps 8 substrate 31
Connected to the _first through plug 4, through plug 4 of the connection substrate 31 ₁ is connected to the through plug 4 of the chip 1 ₂ via the solder bumps 8.

In this way, the upper and lower adjacent chips 1 ₁ and 1 ₂ are connected to the connection substrate 31 ₁ provided between them.
Are electrically connected to each other via the through plug 4. Similarly, the chip 1 ₂ via the through plugs 4 of the connection substrate 31 _2, will be electrically connected to the chip 1 _3. The method of forming the through plug 4 is similar to that of the second embodiment.

[0123] The connection substrate 31 _1, 31 _2, the thermal conductivity is formed so as to be sufficiently higher than the chip ₁ 1 to 1 _3.

[0124] Specifically, the material of the connection board 31 _1, 31 _2, material having a high thermal conductivity than silicon, which is the material of the silicon substrate 2, for example SiC, is formed of an insulating material such as SiN I have. Incidentally, in the figure, the material of the connection board 31 ₂ indicates those in the case where an insulating material. Therefore, no insulating film is formed on the side surface of the through hole in which the through plug 4 is embedded.

Further, a metal plate 32 having a higher thermal conductivity is embedded in the connection board body (through plug 4 + connection board 31 ₁ , through plug 4 + connection board 31 ₂ ). The constituent material of the metal plate 32 is as follows.
For example, it is a metal such as W and Cu. The metal plate 32 may be provided on the connection substrate 31 _1, 31 ₂ of the surface, it may be provided on both the interior and surface.

[0126] Also, the front and back surfaces of the connection substrate 31 _1, 31 _2, so as to surround the periphery of the solder bumps 8, respectively, a heater 33 is buried. Heater 33
Via a power line 34 comprising a connection board 31 _1, 31 W or the like provided in _2, is connected to an external power source.

[0127] Each supply line 34 can be controlled independently, thereby connecting the substrate 31 _first surface and the heater 33 are respectively buried in the back surface and the connecting board 31 and _second surface and the heater 33 are respectively buried in the back surface,
That is, each of the four heaters can be controlled independently. In addition, the power supply line 34 forms a capacitor, and enables stable power supply.

In the figure, reference numeral 35 denotes a wiring board, and 36 denotes a multilayer wiring layer. Reference numeral 31 ₃ denotes a connection substrate 31 ₁ ,
31 ₂ shows a similar connection substrate and is not used for connection of the chips. This connecting board 31 ₃ and is used as a heat sink, not always necessary.
The insulating film on the side wall of the through hole of the semiconductor substrate is omitted.

In this embodiment, the connection substrates 31 ₁ and 31 ₂
But since the heat conductivity is sufficiently higher than the chip ₁ 1 to 1 _3, even if heat generation chip ₁ 1 to 1 ₃ during operation of the chip ₁ 1 to 1 _3, the heat is connecting substrate 31 _1, 31 ₂ can effectively escape to the outside. Thus, deterioration of the operating characteristics of the chip 1 ₁ to 1 ₃ due to heat generation, the chip 1
It becomes possible to prevent the shortening of ₁ to 1 _3.

Further, according to the present embodiment, the connection substrate 31
_1, 31 ₂ provided et al were, by the heater 33 can be controlled independently by selectively melting only bumps connected to the determined chip defective by the inspection, only selectively defective chip from the connecting board Since the chips can be separated, the chip can be easily repaired.

FIG. 10 shows a state of the repair. Although only the reference numbers necessary for the description are given in the figure, the configuration of the multi-chip semiconductor device is the same as that shown in FIG. 8 (the same applies to other embodiments).

FIG. 10A shows a state where the chip is inspected by the inspection probe, and FIG.
Shows a state of removing a chip 1 ₂ determined to be defective by the inspection, the connected connection substrate 31 ₂ thereto.
Incidentally, the chip 1 ₂ in the step of FIG. 10 (b), the may be removed connected connection substrate 31 ₁ thereto.

[0133] Thereafter, the chip 1 ₂ separates from the connection substrate 31 _2, to connect the new chip to the connection substrate 31 _2. Then connecting the new chip connected connection substrate 31 ₂ based on the street. After that, if the chip is inspected and passed, the repair is finished, but if not, the above steps are repeated until the chip is passed.

In the present embodiment, the case where the heater 33 is formed so as to surround the peripheral portion of the solder bump 8 and the peripheral portion of the solder bump 8 is preferentially heated, but the entire connection substrate is heated. Thus, even when the heater 33 is provided, repair can be performed more easily than in the conventional case.

(Fourth Embodiment) FIG. 11 is a sectional view of a multi-chip semiconductor device according to a fourth embodiment of the present invention.

This embodiment is different from the third embodiment in that the heat radiation fins 37 are provided on the connection boards 31 _{1 to} 31 ₃ . The radiation fins 37 are fixed to the connection substrates 31 _{1 to} 31 ₃ by, for example, an adhesive. Note that another fixing method such as fixing by metallizing may be used.

According to the present embodiment, the connection substrates 31 _{1 to} 3 ₁
1 ₃ not only conduct heat away from, since heat can be Nigasuru from high heat radiation fins 37 in thermal conductivity than can be released from the chip 1 ₁ to 1 ₃ heat more effectively .

(Fifth Embodiment) FIG. 12 is a sectional view of a multichip semiconductor device according to a fifth embodiment of the present invention.

This embodiment is different from the fourth embodiment in that the radiation fins 37 are provided only on the chips having a large heat value. Here, the chip 1 _2, 1 ₃ chip 1
_It is said that the calorific value is larger than ₁ . In this case, it is not necessary to provide a connection board 31 ₃ as a heat sink to the chip 1 _3, it is possible to miniaturize the apparatus with respect to the stacking direction.

(Sixth Embodiment) FIG. 13 is a sectional view of a multichip semiconductor device according to a sixth embodiment of the present invention.

[0141] This embodiment differs from the third embodiment, the inside of the connection substrate 31 ₂ multilayer interconnection of, is that the rearranged wiring. Specifically, the solder bump 8a is not connected to the solder bump 8b thereon, but is connected to the upper left solder bump 8c via the plug 38a, the wiring layer 39a, and the plug 38b.
And the solder bump 8d is not connected to the solder bump 6c thereon, but is connected to the wiring layer 39b via the plug 38c.
Connected to

[0142] Incidentally, the heater 33 is buried in the surface and the back surface of the chip 1 _3, the wiring layer 39a, but is provided at a position away from a 39 b, a heater 33 chip 1
₃ and may be provided on the same layer as the wiring layers 39a and 39b.

(Seventh Embodiment) FIG. 14 is a sectional view of a multichip semiconductor device according to a seventh embodiment of the present invention.

The present embodiment differs from the third embodiment in that a capacitor is provided inside the connection substrate to stabilize the power supplied to the chip. Connection board 31
₃ will be described. In the connection board 31 ₃ , the power lines 4 are provided so that the ground lines 41 exist above and below the power lines 40.
0, the ground line 41 is formed. Thereby, two directly connected capacitors are formed in the vertical direction.

[0145] Note that the structure material of the connection board 31 ₃ is an insulating material. In the drawing, reference numerals 42 and 43 indicate wirings. The wirings 42 and 43 are respectively connected to the bumps via pads, but these pads are omitted. As for the other connection substrate other than the connection substrate ₃₁₃ (not shown),
A similar capacitor is formed.

(Eighth Embodiment) FIG. 15 is a sectional view of a multichip semiconductor device according to an eighth embodiment of the present invention.

The multi-chip semiconductor device of this embodiment is
Upper layer Si chip 51₁Is a laminated wiring base made of Si
Board 52₁, 52_TwoThe lower Si chip 51_Two, 5
1_Three It is configured to be connected to In the figure, 50 is
Si chip 51₁~ 51_Three Of FIG.

[0148] pads 53 provided on the Si chip 51 ₁
Via the solder bump 54 is connected to a pad 55 provided on the multilayer wiring substrate 52 _1. This pad 55
A wiring layer (not shown) formed in the multilayer wiring board 52 _1, through plugs 4 are connected to the wiring layer, the pads 56 provided on the multilayer wiring substrate 52 ₁ and the solder bumps 57
Via a pad 58 provided on the laminated wiring board 52 ₂
Connected to Here, the through plug 4 and the wiring layer usually use a metal such as Cu or Al in order to sufficiently exhibit their original purpose. It is preferable to use a material formed of a Si film having a high impurity concentration.

[0149] pads 58, the wiring layer (not shown) formed in the multilayer wiring board 52 _2, the pads 59 are connected to the wiring layer, and through the solder bumps 60, Si chip 5
It is connected to a pad 61 provided in the 1 _2, 51 _3. As described above, the wiring layer uses a metal material or a Si film having a high impurity concentration.

Thus, the upper Si chip 51
₁ is a lower layer Si through the multilayer wiring boards 52 ₁ and 52 _2.
It is connected to the chip 51 _2, 51 _3.

[0151] The layered wiring substrate 52 _1, the pad 5
6, the solder bumps 57, and through the pad 58, is connected to the laminated wiring board 52 _2. Laminated wiring board 52 ₂
Are similarly connected to a plastic substrate 65 via pads 62, solder bumps 63, and pads 64. Pads 66 and solder bumps 67 are provided on the plastic substrate 65, and a wiring layer 68 connecting the pads 64 and 66 is formed in the plastic substrate 65.

Between the Si chip 51 ₁ and the multilayer wiring board 52 ₁ , between the Si chips 51 ₂ and 51 ₃ and the multilayer wiring board 52 ₂
Is filled with an adhesive 69 containing no filler.

[0153] even when no filler is mixed into the adhesive 69, an Si chip 51 _{1-51 3} constituting material and the laminated wiring board 52 _1, 52 ₂ of the same Si with it, thus the Si chip 51 _1-51 since the thermal expansion coefficient of the multilayer wiring board 52 _{1 3,} 52 ₂ and it is equal, it is possible to obtain a reliable connection.

[0154] On the other hand, since each other materials of construction and the laminated wiring board 52 ₂ and the plastic substrate 65 is different, between the laminated wiring board 52 ₂ and the plastic substrate 65, the adhesive 70 which filler is mixed is filled And these 52
The reliability of the connection between ₂ and 65 is ensured.

[0155] Here, since the laminated wiring board 52 _1, 52 ₂ are not elements formed can be set pitch between the solder bumps 63 to a desired value. Therefore, the pitch between the solder bumps 63 can be set to the extent that the adhesive 70 can be reliably inserted between the solder bumps 63.

[0156] In the embodiment as described above, since the multilayer wiring board 52 _1, 52 ₂ and the Si chip 51 _{1-51 3} are formed in the same Si, solder bumps 54,6
0 has almost no thermal distortion.

Therefore, the Si chips 51 _{1 to} 51 ₃
As the integration of semiconductor chips further progresses, the distance between the Si chip 51 ₁ and the laminated wiring substrate 52 ₁ , the Si chips 51 ₂ , 51
It is _3. But the shorter the distance between the laminated wiring board _522, the reliability of the connection between them is ensured, thus the upper layer of the Si chip 51 ₁ and the lower layer of the Si chip 51 _2, 5
1 ₃ will be able to ensure the reliability of connection between the.

The laminated wiring boards 52 ₁ , 52 ₂ and Si
Since the chip 51 _{1-51 3} are formed in the same Si, without any need to approach these thermal expansion coefficients, thus it is possible to use an adhesive 69 that does not have a filler.

Therefore, the Si chip 51₁~ 51_Three
Of the Si chip 51₁And stacked arrangement
Wire substrate 52₁Distance between the Si chip 51_Two, 51
_ThreeAnd laminated wiring board 52_TwoThe distance between
Also, since there is no portion where the adhesive 69 is not filled,
Layer Si chip 51₁And lower Si chip 51_Two, 51
_Three And the reliability of the connection between them.

For the same reason as in the first embodiment, the plane area of the device can be reduced.

[0161] Further, in the present embodiment, the Si chip 51 _{1-51 3} formed of elements it is not necessary to form the through plugs can suppress an increase in cost. Of course, by using the Si chip 51 _{1-51 3} having a through plug, Si chip 51 ₁ and the Si chip 51 _2, 51
₃ and 2008 may be the configuration of connecting only through the multilayer wiring board 52 _1.

16 to 18 are process sectional views showing a method for manufacturing a multi-chip semiconductor device of the present embodiment.

[0163] First, as shown in FIG. 16 (a), a device (not shown) on the element formation surface 50 of the Si substrate is integrally formed to create a Si chip 51 ₁ then forming a pad 53, followed by the pad A solder bump 54 is formed on 53.

[0164] Next, as shown in FIG. 16 (b), through plugs 4 and the wiring layer made of Si on Si substrate, and then forming a pad 55 to create a multilayer wiring substrate 52 _1. The pad 55 is formed at a position corresponding to the pad 33. The pads 33 and 55 are squares each having a side of 20 μm.
The pitch of 3,55 is 30 μm (the distance between pads is 10 μm).
m).

Next, as shown in FIG. 16C, the solder bumps 54 of the Si chip 51 ₁ are aligned with the pads 55 of the laminated wiring board 52 ₁ , and after these 54 and 55 are joined, the Si chip 51 _An epoxy-based adhesive 6 in which no filler is mixed between ₁ and the laminated wiring board 52 ₁
9 on the laminated wiring substrate 52 ₁ by filling
i chip ₅₁₁ to form a unit 71 ₁ formed by flip chip bonding.

[0166] The distance between the Si substrate constituting the Si substrate and the Si chip 51 ₁ forming the laminated wiring board 52 ₁ 20μ
m. For this purpose, the size of the solder bump 54 may be about 20 μmφ.

[0167] Next, as shown in FIG. 17 (d), the element (not shown) on the element formation surface 50 of the Si substrate is integrally formed to create a Si chip 51 ₂ then forming a pad 61, followed by Si solder bumps on the chip 51 _{and second} pad 61 60
To form Next, as shown in FIG. 1 (d), to create a Si chip 51 ₂ in the same manner, followed by forming a solder bump 60 on the Si chip 51 _second pad 61.

Next, as shown in FIG. 17E, a through plug 4 made of Si, a wiring layer, and a pad 5 are formed on a Si substrate.
To form a 8,59,62 create a multilayer wiring board 52 _2, then to form a solder bump 57 on the pad 58.

[0169] Next, as shown in FIG. 17 (f), as in the case of unit 71 _1, aligning, bonding, adhesive 69
Performing filling, Si chip 5 on the laminated wiring board 52 ₂
A unit 71 ₂ is formed by flip chip bonding of 1 ₂ and 51 ₃ .

[0170] Next, as shown in FIG. 18 (g), by joining the solder bumps 58 and the pads 56, connecting the unit 71 ₁ and the unit 71 _2.

At this time, the laminated wiring boards 52 ₁ , 52 ₂ ,
Since Si chip 51 _{2-51 3} is formed by Si, thermal strain due to difference in thermal expansion coefficient is not. Therefore, the size and pitch of the design of the bumps, thermal strain due to difference in thermal expansion coefficient is without considering, considering only the thickness of the Si chip 51 _2, 51 ₃ between the multilayer wiring board 52 _1, 52 ₂ Just do it.

[0172] pads 62 formed on the lower surface of the multilayer wiring board 52 _2, solder bumps 63 of the plastic substrate 65
Therefore, the diameter and pitch of the pad 62 need to be about 100 μm and 200 μm or more, respectively. Moreover, it is formed the wiring layer for relaxing the pitch in the laminated wiring board 52 _2.

Finally, as shown in FIG. 18H, the plastic substrate 6 having the pads 64 and 66 and the wiring layer 68 is formed.
5 and then solder bumps 6 on pads 64 and 66.
3 and 67 are formed, and then the plastic substrate 65 and the unit 71 ₂ to which the unit 71 ₁ is connected are aligned and joined.
By filling the adhesive 70 containing the SiO ₂ filler to relax the strain between the _two multi-chip semiconductor device is completed as shown in FIG. 15.

In this embodiment, the laminated wiring boards 52 ₁ , 52
Si is used substrate as 2 _second substrate. Therefore, inexpensive and uniform laminated wiring boards 52 ₁ , 52
₂ can be formed.

The design rules of the wiring layers formed on the laminated wiring boards 52 ₁ and 52 ₂ are based on the Si chips 51 ₁ and 5
1 much looser than that of the wiring layer formed on the ₂ (for example, several μm order). Therefore, the yield is almost 10
0% can be obtained. MOS transistors,
Since it is not necessary to form an element such as a capacitor, there is almost no need to consider the contamination of the Si substrate, and the process can be simplified.

In this embodiment, the case where the constituent material of the chip is the same as the constituent material of the laminated wiring board has been described. However, the constituent materials may be different as long as the coefficients of thermal expansion are substantially equal. Also, in this case, as described in the section of the operation, a combination of constituent materials that makes the heat dissipation of the laminated wiring board (connection board) higher than that of the chip is preferable.

Further, in the case of the same constituent material, for example, by providing a heat radiating means such as a radiating fin on the laminated wiring board, or by giving a heat radiating function to a through plug formed on the laminated wiring board, It is preferable to form the through plug with a material having a higher heat dissipation property than the constituent material. Specifically, when the constituent material of the chip and the laminated wiring board is Si, it can be seen from Table 1 that SiC or AlN may be used.

[0178]

As described in detail above, according to the first aspect of the present invention, since a plurality of chips are stacked, the plane area of the device can be reduced, and the chip on which the conductive plug is formed is best. By arranging it at the top or the bottom, it is possible to easily apply the inspection probe to the conductive plug, so that the inspection of the device can be easily performed.

According to the second aspect of the present invention, since a plurality of chips are stacked, the plane area of the device can be reduced.
Moreover, since the connection substrate has higher heat dissipation than the chip, the heat dissipation can be improved.

According to the third aspect of the present invention, since a plurality of chips are stacked, the plane area of the device can be reduced.
In addition, the bumps connected to the defective chip can be melted by the heat generating portion of the connection substrate, and thus the chip can be easily repaired.

According to the fourth aspect of the present invention, since a plurality of chips are stacked, the plane area of the device can be reduced, and the thermal expansion coefficient of the constituent material of the connection substrate and that of the constituent material of the semiconductor substrate can be reduced. Since they are almost equal, the reliability of connection between the upper and lower chips can be ensured even if bumps and an adhesive are used for the connection members.

[Brief description of the drawings]

FIG. 1 is a sectional view of a multi-chip semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing a method for forming a first half of a through plug of a multichip semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a process cross-sectional view showing a first-half method of forming a through plug of a multi-chip semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a sectional view showing a through plug.

FIG. 5 is a process sectional view showing a method of forming a groove.

FIG. 6 is a process sectional view showing another method of forming the through plug.

FIG. 7 is a process sectional view showing still another method of forming a through plug.

FIG. 8 is a sectional view of a multi-chip semiconductor device according to a third embodiment of the present invention.

FIG. 9 is a plan view of a connection substrate of the multi-chip semiconductor device of FIG. 8;

FIG. 10 is a diagram showing a state of repair of the multi-chip semiconductor device of FIG. 8;

FIG. 11 is a sectional view of a multi-chip semiconductor device according to a fourth embodiment of the present invention.

FIG. 12 is a sectional view of a multi-chip semiconductor device according to a fifth embodiment of the present invention.

FIG. 13 is a sectional view of a multi-chip semiconductor device according to a sixth embodiment of the present invention.

FIG. 14 is a sectional view of a multichip semiconductor device according to a seventh embodiment of the present invention.

FIG. 15 is a sectional view of a multichip semiconductor device according to a seventh embodiment of the present invention;

16 is a process sectional view illustrating the method of manufacturing the multi-chip semiconductor device in FIG.

FIG. 17 is a process sectional view illustrating the method of manufacturing the multi-chip semiconductor device, following FIG. 16;

FIG. 18 is a process sectional view illustrating the method of manufacturing the multi-chip semiconductor device, following FIG. 17;

FIG. 19 is a sectional view of a conventional multichip semiconductor device.

FIG. 20 is a sectional view of another conventional multi-chip semiconductor device.

FIG. 21 is a sectional view of still another conventional multi-chip semiconductor device.

FIG. 22 is a cross-sectional view of a multi-chip semiconductor device using wire bonding as a conventional mounting method.

FIG. 23 is a cross-sectional view of a multi-chip semiconductor device using TAB as a conventional mounting method.

FIG. 24 is a cross-sectional view of a multi-chip semiconductor device using a flip chip as a conventional mounting method.

[Explanation of symbols]

1 ₁ , 1 ₂ , 1 ₃ … Chip 2… Silicon substrate 3… Multilayer wiring layer 4… Through plug (conductive plug) 4 a… Conductive film 5… Insulating film 6… Pad 7… Insulating film 8… Solder bump 9… laminated wiring board (connection substrate) 11 ... mask pattern 12, 12 ₁ to 12 ₃ ... groove 13 ... low-stress film 14 ... cap metal film 15 ... cap insulating film 16 ... metal balls 17 ... metal silicide film 18 ... conductive paste 19 ... Metal fine particles 20 ... Silicon film 21 ... Metal silicide film 22 ... Silicon film 23 ... Ni grain 24 ... Ni silicide film 25 ... Cap film 31 _{1 to} 31 ₃ ... Connection substrate 32 ... Metal plate (high thermal conductivity member, conductive plate) 33: heater (heat generating part) 34: power supply line 35: wiring board 36: multilayer wiring layer 37: heat radiation fins 38a to 38c: plugs 39a, 39b Wiring layers 40 ... power supply line 41 ... ground line 42, 43 ... wiring 50 ... element forming surface 51 _1, 51 _2, 51 ₃ ... Si chip 52 _1, 52 ₂ ... multilayer wiring board (connection substrate) 53 ... pad 54 ... solder bumps 55 ... pad 4 ... penetrating plug 56 ... pad 57 ... solder bump 58, 59 ... pad 60 ... solder bump 61, 62 ... pad 63 ... solder bump 64 ... pad 65 ... plastic substrate 66 ... pad 67 ... solder bump 68 ... wiring layer 69 ... adhesive (No filler) 70 ... Adhesive (with filler) 71 ₁ , 71 ₂ ... Unit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Katsuya Okumura 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Pref.

Claims (14)

[Claims] 1. A multi-chip semiconductor device comprising a plurality of chips having a semiconductor substrate on which elements are integratedly formed, wherein two adjacent upper and lower chips are mutually connected via a connection substrate provided between them. A multichip semiconductor device electrically connected to the semiconductor substrate, wherein a through hole is formed in the semiconductor substrate, and a conductive plug formed in the through hole is connected to the connection substrate. 2. A multi-chip semiconductor device comprising a plurality of chips each having a semiconductor substrate on which elements are integratedly formed, wherein a conductive plug is formed in a through hole between two adjacent upper and lower chips. A connection board is provided, and
A multi-chip semiconductor device, wherein the two chips are electrically connected to each other via the conductive plug, and the connection substrate has higher heat dissipation than the chips. 3. The multi-chip semiconductor according to claim 1, wherein a material having a higher heat dissipation property than that of the chip is selected for the connection board as a constituent material of the connection board. apparatus. 4. The connection board according to claim 1, wherein the connection board includes a connection board body on which the conductive plug is formed, and a high thermal conductivity member having higher thermal conductivity than the connection board body. 3. The multi-chip semiconductor device according to claim 1 or 2. 5. The multi-chip semiconductor device according to claim 4, wherein said high thermal conductivity member is a conductive plate formed inside said connection substrate body. 6. The multi-chip semiconductor device according to claim 4, wherein said high thermal conductivity member is a radiation fin provided on a surface of said connection board main body. 7. A multi-chip semiconductor device comprising a plurality of chips having a semiconductor substrate on which elements are integrated and formed, a conductive plug is formed in a through hole between two adjacent upper and lower chips. A connection board is provided, and
A multi-chip semiconductor device, wherein each of the chips is electrically connected to the conductive plug via a bump, and the connection substrate has a heat generating portion. 8. The multi-chip semiconductor device according to claim 7, wherein the heat generating portions of each connection board can be controlled independently. 9. The multi-chip semiconductor device according to claim 7, wherein said heat generating portion is formed so as to surround said bump. 10. The multi-chip semiconductor device according to claim 2, wherein a multilayer wiring is formed in said connection substrate. 11. The connection substrate is made of an insulating material, and a power supply line is provided in the connection substrate with a first capacitor electrode,
The multi-chip semiconductor device according to claim 2, wherein a capacitor having a ground line as a second capacitor and the connection substrate as a capacitor insulating film is formed. 12. A multi-chip semiconductor device comprising a plurality of chips having a semiconductor substrate on which elements are integrated and formed, a conductive plug is formed in a through hole between two adjacent upper and lower chips. And the two chips are electrically connected to each other via the conductive plug, and the connection substrate has higher heat dissipation than the chip, and the constituent material of the connection substrate is A multi-chip semiconductor device having substantially the same coefficient of thermal expansion as that of the semiconductor substrate. 13. A multi-chip semiconductor device comprising a plurality of chips having a semiconductor substrate on which elements are integrated and formed, wherein a conductive plug is formed in a through hole between two adjacent upper and lower chips. And the two chips are electrically connected to each other via the conductive plug, and the constituent material of the connection substrate has substantially the same coefficient of thermal expansion as that of the semiconductor substrate. A multi-chip semiconductor device characterized by the following. 14. The difference between the coefficient of thermal expansion of the constituent material of the connection substrate and that of the constituent material of the semiconductor substrate is ± 5.0 × 1.
^14. The multi-chip semiconductor device according to claim 12, wherein the value is within 0-6.