JPS63291436A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63291436A JPS63291436A JP62125871A JP12587187A JPS63291436A JP S63291436 A JPS63291436 A JP S63291436A JP 62125871 A JP62125871 A JP 62125871A JP 12587187 A JP12587187 A JP 12587187A JP S63291436 A JPS63291436 A JP S63291436A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- ions
- superconducting
- semiconductor element
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000463 material Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000005468 ion implantation Methods 0.000 claims abstract description 19
- 238000000137 annealing Methods 0.000 claims abstract description 14
- 239000001301 oxygen Substances 0.000 claims abstract description 13
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 13
- 239000002887 superconductor Substances 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- -1 oxygen ions Chemical class 0.000 claims description 10
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 4
- 239000005751 Copper oxide Substances 0.000 claims description 4
- 229910000431 copper oxide Inorganic materials 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 abstract description 19
- 239000010409 thin film Substances 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 6
- 238000000206 photolithography Methods 0.000 abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 18
- 239000010408 film Substances 0.000 description 10
- 239000012212 insulator Substances 0.000 description 10
- 239000000203 mixture Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に係り、特に配線パター
ンが１μｍ以下のＶＬＳＩの製造に好適な半導体装置の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device suitable for manufacturing a VLSI with a wiring pattern of 1 μm or less.
従来半導体装置の配線材料にはＡＱあるいはＡＱに少量
Ｓｉを含むＡｎ−８ｉ合金が用いられて来た。配線の微
細化に伴い現在、「日経マイクロデバイスＪ １９８６
年１２月号ｐｐ８５にあるようにＡＱ−Ｃｕ−８ｉ合金
も検討されている。Conventionally, AQ or an An-8i alloy containing a small amount of Si in AQ has been used as a wiring material for semiconductor devices. Due to the miniaturization of wiring, currently "Nikkei Microdevice J 1986
AQ-Cu-8i alloy is also being considered, as stated in the December issue, pp. 85.
しかし、配線材料に金属を用いた場合には、配線材料の
比抵抗の下限は全金属中で最も比抵抗の小さいＡｇ（７
）１．６ｘ１０−８Ω・ａｎ（２０’Ｃ）を大きく上ま
わることは困難と予想される。However, when metal is used as the wiring material, the lower limit of the specific resistance of the wiring material is Ag (7
) It is expected that it will be difficult to significantly exceed 1.6 x 10 -8 Ω·an (20'C).
また、従来の配線技術では配線のエッチングエ程を伴い
、大きな段差を発生させている。そのため、「セミコン
ダクター ワールド」第６巻 第３号 第３６頁、１９
８７年（ＳｅｍｉｃｏｎｄｕｃｔｏｒＷｏｒｌｄ Ｖｏ
Ｑ、６．Ｎａ５ｐｐ、３６ １９８７）で述べられてい
る各種平坦化法が考案されている。Further, the conventional wiring technology involves an etching process for the wiring, which causes a large level difference. Therefore, "Semiconductor World" Volume 6 No. 3 Page 36, 19
1987 (Semiconductor World Vo.
Q, 6. Various planarization methods have been devised as described in Na5pp, 36 1987).
これらの平坦化法は、配線のエツチングにより発生した
段差をそれ以降のプロセスで埋めて平坦化するものであ
り、複雑な工程を必要とし、また完全に平坦にできるわ
けではない。These planarization methods involve filling in the step difference caused by etching the wiring in a subsequent process to achieve planarization, which requires a complicated process and cannot achieve complete planarization.
上記従来技術では、配線材料としてアルミニウムあるい
はアルミニウム合金のみしか示されておらず、配線の微
細化に伴なう抵抗の増大を解決することができなかった
。また、上記従来技術では配線のパターニングの結果生
じる段差を完全に平坦化することは困難であり、多層配
線等でさらに上部にパターンを形成する上で問題があっ
た。In the above-mentioned conventional technology, only aluminum or an aluminum alloy is shown as the wiring material, and it has not been possible to solve the problem of increased resistance due to miniaturization of the wiring. Further, in the above-mentioned conventional technology, it is difficult to completely flatten the level difference that occurs as a result of wiring patterning, and there is a problem in forming a pattern further above in a multilayer wiring or the like.
本発明の目的は、抵抗がゼロである超伝導材料を配線に
用い、配線のパターニングによる段差の発生のない半導
体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device using a superconducting material having zero resistance for wiring and eliminating steps caused by patterning of the wiring.
本発明は、銅酸化物系超伝導材料の超伝導性が組成を変
えることにより消失することを利用し、イオンインプラ
チージョン技術により、薄膜中の組成を部分的に変え、
超伝導配線部分と絶縁体部分を同一の膜中に形成し、エ
ツチングによる段差の発生なしに超伝導配線を形成する
ようにしたものである。The present invention takes advantage of the fact that the superconductivity of cuprate-based superconducting materials disappears by changing the composition, and uses ion implantation technology to partially change the composition in the thin film.
The superconducting wiring portion and the insulator portion are formed in the same film, so that the superconducting wiring can be formed without creating a step difference due to etching.
本発明の一例は、半導体素子表面に酸化物超伝導材料層
を形成し、配線を形成する部分以外の部分にイオン打込
みを行って非超伝導化することにより達成できる。イオ
ン打込み量を調整することにより抵抗値を変化させ、常
伝導化或は絶縁体化することができる。An example of the present invention can be achieved by forming an oxide superconducting material layer on the surface of a semiconductor element, and implanting ions into areas other than those where interconnections are to be formed to make them non-superconducting. By adjusting the amount of ion implantation, the resistance value can be changed and the material can be made into a normal conductor or an insulator.
他の例としては、半導体素子表面に酸素イオン打込みに
より酸化物超伝導体を形成する物質層を形成し、配線を
形成する部分のみに酸素イオンを打込み、次いでアニー
ルして該部分を超伝導体することにより達成できる。こ
の具体的方法とじては、前記半導体素子表面に酸素イオ
ン打込みにより銅酸化物系超伝導体を形成する、少なく
とも二層からなる物質層を形成し且つそのうちの最上層
は銅層とし、配線を形成する部分のみに酸素イオンを打
込み、次いでアニールして銅酸化物系超伝導体を形成し
、残りの銅層を除去することが望ましい。Another example is to form a layer of material that forms an oxide superconductor on the surface of a semiconductor element by implanting oxygen ions, implanting oxygen ions only in the portion where wiring will be formed, and then annealing to transform that portion into a superconductor. This can be achieved by This specific method involves forming a material layer consisting of at least two layers to form a copper oxide superconductor by implanting oxygen ions on the surface of the semiconductor element, the top layer of which is a copper layer, and wiring is formed. It is desirable to implant oxygen ions only in the portion to be formed, then anneal to form a copper oxide superconductor, and remove the remaining copper layer.
本発明の方法は、多層配線の形成にも利用できる。The method of the present invention can also be used to form multilayer wiring.
半導体素子上に形成された超伝導薄膜のうちイオンイン
プランテーション及びその後のアニールを受けた部分で
はインプランテーションされたイオンが膜中で膜の構成
元素と結合し膜組成を変えてしまい、非超伝導性たとえ
ば絶縁性のセラミックとなるので、パターニング段差な
しで超伝導配線を形成できる。In the part of the superconducting thin film formed on the semiconductor device that has undergone ion implantation and subsequent annealing, the implanted ions combine with the film's constituent elements in the film and change the film composition, making it non-superconducting. Since the material is made of, for example, insulating ceramic, superconducting wiring can be formed without patterning steps.
銅薄膜上から酸素イオンをインプランテーションする際
、銅薄膜が十分薄くまた。イオンの加速電圧が適当な大
きさであれば、酸素イオンは銅原子を下の金属酸化物膜
中に打込みながらインプランテーションされる。その結
果、金属酸化物膜は銅酸化物系超伝導体の組成となり超
伝導配線が形成される。その後に余分の銅をエツチング
で除くことにより段差のない超伝導配線を形成すること
ができる。When implanting oxygen ions from above the copper thin film, make sure that the copper thin film is sufficiently thin. If the ion accelerating voltage is of an appropriate magnitude, oxygen ions are implanted while driving copper atoms into the underlying metal oxide film. As a result, the metal oxide film has a composition of a copper oxide superconductor, and superconducting wiring is formed. Thereafter, by removing excess copper by etching, it is possible to form a superconducting interconnection with no steps.
イオンインプランテーションにおいては、イオンの加速
電圧を変えることによりイオンの打込み深さを調節する
ことができ、特定の深さのイオンの打込み濃度を制御で
きる。よって２回以上のイオンインプランテーションに
より、膜中の深さの異なる位置に２種以上のパターンを
形成することが可能である。イオンインプランテーショ
ンの後アニールして、任意の多層パターンを有する超伝
導配線を形成することができる。In ion implantation, the ion implantation depth can be adjusted by changing the ion acceleration voltage, and the ion implantation concentration at a specific depth can be controlled. Therefore, by performing ion implantation twice or more, it is possible to form two or more types of patterns at different depths in the film. By annealing after ion implantation, a superconducting interconnect having an arbitrary multilayer pattern can be formed.
実施例１
以下、本発明の一実施例を第１図、第２図により説明す
る。Example 1 An example of the present invention will be described below with reference to FIGS. 1 and 2.
第１図は本発明に係る半導体装置の断面図である。１は
Ｓｉ基板上に形成された半導体素子であり、２は熱酸化
Ｓｉ０２層である。３は半導体素子と配線をつなぐコン
タクト孔を形成する層間絶縁層であり、化学気相蒸着（
ＣＶＤ）法で形成したガラスおよび５ｉ３Ｎａより成る
。４はＴｉＮ膜のバリヤ層であり、半導体素子１が、配
線膜の形成及びアニールの際に５の超伝導材料配線と反
応するのを防ぐ。６はイオン打込み及びアニールにより
組成が変えられ非超伝導体たとえば絶縁体となった部分
であり、７はＣＶＤ法で形成されたガラス保護膜層であ
る。以下で、本発明に係る超伝導材料配線５および非超
伝導体（絶縁体）６の形成方法を第２図（イ）〜（ハ）
に従い説明する。FIG. 1 is a sectional view of a semiconductor device according to the present invention. 1 is a semiconductor element formed on a Si substrate, and 2 is a thermally oxidized Si02 layer. 3 is an interlayer insulating layer that forms contact holes connecting semiconductor elements and wiring, and is made by chemical vapor deposition (chemical vapor deposition).
It is made of glass formed by CVD method and 5i3Na. 4 is a barrier layer of TiN film, which prevents the semiconductor element 1 from reacting with the superconducting material wiring 5 during formation and annealing of the wiring film. 6 is a portion whose composition has been changed by ion implantation and annealing to become a non-superconductor, such as an insulator, and 7 is a glass protective film layer formed by CVD. Below, the method for forming the superconducting material wiring 5 and the non-superconductor (insulator) 6 according to the present invention will be explained as shown in FIGS.
Explain according to the following.
半導体素子上にスパッタ法により酸化物超伝導体薄膜８
を形成する。スパッタターゲットの組成はＢａｚＹＣｕ
３０Ｂ、５であるが、スパッタ中にＯは少し抜け、薄膜
はＢａｚＹＣｕＯ７−ｘの組成で形成される。次に第２
図の（ロ）に示すようにホトリソグラフィーによりレジ
スト９でパターンを形成し、レジスト９をマスクとして
配線部分以外にイオン打込みを行なう。符号１ｏは打込
みイオンを示す。Oxide superconductor thin film 8 is deposited on the semiconductor device by sputtering.
form. The composition of the sputter target is BazYCu
30B, 5, some O is lost during sputtering, and the thin film is formed with a composition of BazYCuO7-x. Then the second
As shown in (b) of the figure, a pattern is formed using resist 9 by photolithography, and ions are implanted into areas other than the wiring portion using resist 9 as a mask. Reference numeral 1o indicates implanted ions.
イオン打込みはＯ＋を８０ｋｅＶで１×１０１６ＣＩ１
１−２の条件で行なう。イオン種は○十以外にもＮ＋。Ion implantation is O+ at 80keV and 1×1016CI1.
Perform under the conditions 1-2. In addition to ○10, the ion species are N+.
ｐ＋ 、ＢＦｚ＋のいずれでもよい。レジストを除去し
酸素雰囲気中で９００’Ｃ６０分のアニールを行ない打
込みイオンの安定化と配線部分の安定化を行ない超伝導
配線パターンを得る。半導体素子によっては高温での酸
素雰囲気アニールが不適な場合もあり、その際は０＋の
全面イオン打込みを８０ｋｅＶ、Ｉ×１０１番■−２の
条件で行ない、５００〜７００℃のＮ２あるいはＡｒ雰
囲気のアニールを６０分行なう。完成した半導体装置は
臨界温度以下の温度で使用するが、上記の方法で作製し
た超伝導配線材料の臨界温度は９０に以上であり、液体
窒素中（７７Ｋ）での使用が可能である。第３図に、配
線の比抵抗と温度の関係を示す。Either p+ or BFz+ may be used. The resist is removed and annealing is performed at 900'C for 60 minutes in an oxygen atmosphere to stabilize the implanted ions and the wiring portion, thereby obtaining a superconducting wiring pattern. Depending on the semiconductor device, annealing in an oxygen atmosphere at high temperatures may be inappropriate. In that case, 0+ full-surface ion implantation is performed under the conditions of 80 keV, I Annealing is performed for 60 minutes. Although the completed semiconductor device is used at a temperature below the critical temperature, the critical temperature of the superconducting wiring material produced by the above method is above 90°C, and it can be used in liquid nitrogen (77K). FIG. 3 shows the relationship between the specific resistance of the wiring and the temperature.
実施例２
以下、本発明の別な一実施例を第４図、第５図により説
明する。第４図は本発明に係る半導体装置の断面図であ
る。５はイオン打込みおよびアニールによって超伝導配
線となった部分であり、６は非超伝導体たとえば酸化物
絶縁体である。以下セ、本発明に係る超伝導配線５と非
超伝導体（絶縁体）６の形成方法を第５図（イ）〜（ハ
）に従い説明する。半導体素子上にスパッタ法により絶
縁体Ｂａ２Ｙ○３．６よりなる酸化物絶縁体薄膜１１を
形成する。さらにその上に銅薄膜１２をスパッタ法によ
り５００人形成する。次にホトリソグラフィーによりレ
ジスト９でパターンを形成し、レジスト９をマスクにし
て配線部分のみにＯ＋のイオン打込みを行なう。イオン
打込みは８０ｋｅＶＩ Ｘ １０１６ａｎ−２の条件で
行なう。レジスト９及び銅薄膜１２を除去し５００〜７
００℃６０分のＮ２あるいはＡｒ雰囲気アニールを行な
い超伝導配線パターンを得る。Embodiment 2 Another embodiment of the present invention will be described below with reference to FIGS. 4 and 5. FIG. 4 is a sectional view of a semiconductor device according to the present invention. 5 is a portion that has become a superconducting wiring through ion implantation and annealing, and 6 is a non-superconductor such as an oxide insulator. Hereinafter, a method for forming superconducting wiring 5 and non-superconductor (insulator) 6 according to the present invention will be described with reference to FIGS. 5(A) to 5(C). An oxide insulator thin film 11 made of an insulator Ba2Y3.6 is formed on the semiconductor element by sputtering. Further, 500 copper thin films 12 are formed thereon by sputtering. Next, a pattern is formed using resist 9 by photolithography, and O+ ions are implanted only into the wiring portion using resist 9 as a mask. Ion implantation is performed under the conditions of 80keVI x 1016an-2. After removing the resist 9 and the copper thin film 12,
Annealing is performed at 00° C. for 60 minutes in N2 or Ar atmosphere to obtain a superconducting wiring pattern.
実施例３
本発明の他の一実施例を第６図、第７図により説明する
。第６図は本発明に係る半導体装置の断面図であり、超
伝導材料による３層配線を示している。以下で本発明に
係る超伝導材料配線５と非超伝導体（絶縁体）６の形成
方法を第７図（イ）〜（ニ）により説明する。第７図（
イ）のように半導体素子上にスパッタ法によりＢａｚＹ
ＣｕＯ７−ｘ組成の酸化物超伝導薄膜８を形成する。次
にホトリソグラフィーによりレジスト９で一層目の配線
パターンを形成し、レジスト９をマスクに一層目の配線
以外の部分にイオン打込みを行なう。イオン打込みは０
＋を２００ｋｅＶで１Ｘ１０１６ａｎ−”の条件で行な
う。次に第７図（ロ）のようにレジストの一部を除去し
、再度ホトリソグラフィーにより二層目の配線パターン
を形成する。一層目と同じくイオン打込みを行なうが、
打込み条件は１００ｋｅＶＩＸ１０１Ｂａｎ−２とする
。三層目配線も同様に形成するが、イオンの打込み条件
は、３０ ｋ ｅＶＩ Ｘ １０１Ｂａ＋＋−２とする
。打込みイオンは０＋以外ニＮ＋ 、 ｐ＋ 、 Ｂ
Ｆｚ＋（７）ｕ’ずれでもよい。レジストを除去し、５
００〜７００℃６０分のＮ２あるいはＡｒ雰囲気アニー
ルを行ない、第７図（Ｃ）に示すように三層の超伝導パ
ターンを得る。打込みイオンの深さプロファイルは第８
図より、深さ方向に十分な精度を持った立体配線が可能
である。Embodiment 3 Another embodiment of the present invention will be described with reference to FIGS. 6 and 7. FIG. 6 is a cross-sectional view of a semiconductor device according to the present invention, showing three-layer wiring made of superconducting material. The method for forming the superconducting material wiring 5 and the non-superconductor (insulator) 6 according to the present invention will be explained below with reference to FIGS. 7(a) to (d). Figure 7 (
BazY is deposited on the semiconductor device by sputtering as shown in b).
An oxide superconducting thin film 8 having a CuO7-x composition is formed. Next, a first layer wiring pattern is formed using resist 9 by photolithography, and ions are implanted into portions other than the first layer wiring using resist 9 as a mask. Ion implantation is 0
+ at 200 keV and 1 x 1016 an-'' condition.Next, as shown in Figure 7(b), a part of the resist is removed and a second layer wiring pattern is formed again by photolithography.Similar to the first layer, ion I type in, but
The implantation conditions are 100keVIX101Ban-2. The third layer wiring is formed in the same manner, but the ion implantation conditions are 30 keVI X 101Ba++-2. The implanted ions are 2N+, p+, B other than 0+.
The deviation may be Fz+(7)u'. Remove the resist, 5
Annealing is performed in N2 or Ar atmosphere for 60 minutes at 00 to 700 DEG C. to obtain a three-layer superconducting pattern as shown in FIG. 7(C). The implanted ion depth profile is 8th.
From the figure, three-dimensional wiring with sufficient accuracy in the depth direction is possible.
本発明によれば、超伝導材料による配線をエツチング工
程なしで形成できるため、超伝導材料による配線を段差
の発生なしで形成する効果がある。According to the present invention, since wiring made of superconducting material can be formed without an etching process, there is an effect that wiring made of superconducting material can be formed without generation of steps.
第１図は本発明の一実施例を示す断面図、第２図は第１
図に示す実施例の作製手順を示す工程図。
第３図は温度と配線材料の比抵抗の関係を示す特性図で
ある。第４図は他の実施例を示す断面図、第５図は第４
図に示す実施例の作製手順を示す工程図である。第６図
は更に他の実施例を示す断面図、第７図は第６図に示す
実施例の作製手順を示？
す工程図、第１図はイオン打込の際のエネルギーと打込
深さの関係を示す特性図である。
１・・・半導体素子、５・・・超伝導材料配線、６・・
・非超伝導体、８・・・酸化物超伝導体薄膜、１０・・
・打込みイオン、１１・・・酸化物絶縁体薄膜、１２・
・・銅薄膜。FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
FIG. 3 is a process diagram showing the manufacturing procedure of the example shown in the figure. FIG. 3 is a characteristic diagram showing the relationship between temperature and specific resistance of wiring material. FIG. 4 is a sectional view showing another embodiment, and FIG. 5 is a sectional view showing another embodiment.
FIG. 3 is a process diagram showing the manufacturing procedure of the example shown in the figure. FIG. 6 is a sectional view showing still another embodiment, and FIG. 7 shows the manufacturing procedure of the embodiment shown in FIG. 6. FIG. 1 is a characteristic diagram showing the relationship between energy and implantation depth during ion implantation. 1... Semiconductor element, 5... Superconducting material wiring, 6...
・Non-superconductor, 8...Oxide superconductor thin film, 10...
・Ion implantation, 11...Oxide insulator thin film, 12.
... Copper thin film.
Claims (1)
において、前記半導体素子表面に酸化物超伝導材料層を
形成し、配線を形成する部分以外の部分をイオン打込み
により非超伝導体化することを特徴とする半導体装置の
製造方法。 ２、半導体素子表面の所定の位置に配線を形成する方法
において、前記半導体素子表面に酸素イオン打込みによ
り酸化物超伝導体を形成する物質層を形成し、配線を形
成する部分のみに酸素イオンを打込み、次いでアニール
して超伝導体化することを特徴とする半導体装置の製造
方法。 ３、半導体素子表面の所定の位置に配線を形成する方法
において、前記半導体素子表面に酸素イオン打込みによ
り銅酸化物系超伝導体を形成する、少なくとも二層から
なる物質層を形成し且つそのうちの最上層は銅層とし、
配線を形成する部分のみに酸素イオンを打込み、次いで
アニールして銅酸化物系超伝導体を形成し、残りの銅層
を除去することを特徴とする半導体装置の製造方法。[Claims] 1. In a method for forming wiring at a predetermined position on the surface of a semiconductor element, an oxide superconducting material layer is formed on the surface of the semiconductor element, and portions other than the portion where the wiring is to be formed are formed by ion implantation. A method for manufacturing a semiconductor device characterized by making it a non-superconductor. 2. In a method for forming wiring at a predetermined position on the surface of a semiconductor element, a layer of material that forms an oxide superconductor is formed by implanting oxygen ions on the surface of the semiconductor element, and oxygen ions are implanted only in the portion where the wiring is to be formed. A method for manufacturing a semiconductor device, characterized by implanting and then annealing to make it a superconductor. 3. A method for forming wiring at a predetermined position on the surface of a semiconductor element, which comprises forming a material layer consisting of at least two layers forming a cuprate-based superconductor by implanting oxygen ions on the surface of the semiconductor element; The top layer is a copper layer,
A method for manufacturing a semiconductor device, comprising implanting oxygen ions only into a portion where wiring is to be formed, then annealing to form a copper oxide superconductor, and removing the remaining copper layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62125871A JPS63291436A (en) | 1987-05-25 | 1987-05-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62125871A JPS63291436A (en) | 1987-05-25 | 1987-05-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63291436A true JPS63291436A (en) | 1988-11-29 |
Family
ID=14920993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62125871A Pending JPS63291436A (en) | 1987-05-25 | 1987-05-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63291436A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0198278A (en) * | 1987-06-22 | 1989-04-17 | Sumitomo Electric Ind Ltd | Manufacture of superconducting circuit |
| JPH01199453A (en) * | 1988-02-04 | 1989-08-10 | Fujitsu Ltd | Manufacture of superconductor element |
| JPH01220873A (en) * | 1988-02-29 | 1989-09-04 | Nec Corp | Oxide superconductor wiring and manufacture thereof |
| JPH01298776A (en) * | 1988-03-29 | 1989-12-01 | American Teleph & Telegr Co <Att> | Manufacture of superconducting device |
| US4920512A (en) * | 1987-06-30 | 1990-04-24 | Mitsubishi Denki Kabushiki Kaisha | Non-volatile semiconductor memory capable of readily erasing data |
| JPH0355889A (en) * | 1989-07-25 | 1991-03-11 | Furukawa Electric Co Ltd:The | Manufacture of superconducting multilayered circuit |
| JPH07263767A (en) * | 1994-01-14 | 1995-10-13 | Trw Inc | Planer type high-temperature superconducting integrated circuit using ion implantation |
| US5593918A (en) * | 1994-04-22 | 1997-01-14 | Lsi Logic Corporation | Techniques for forming superconductive lines |
-
1987
- 1987-05-25 JP JP62125871A patent/JPS63291436A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0198278A (en) * | 1987-06-22 | 1989-04-17 | Sumitomo Electric Ind Ltd | Manufacture of superconducting circuit |
| US4920512A (en) * | 1987-06-30 | 1990-04-24 | Mitsubishi Denki Kabushiki Kaisha | Non-volatile semiconductor memory capable of readily erasing data |
| JPH01199453A (en) * | 1988-02-04 | 1989-08-10 | Fujitsu Ltd | Manufacture of superconductor element |
| JPH01220873A (en) * | 1988-02-29 | 1989-09-04 | Nec Corp | Oxide superconductor wiring and manufacture thereof |
| JPH01298776A (en) * | 1988-03-29 | 1989-12-01 | American Teleph & Telegr Co <Att> | Manufacture of superconducting device |
| JPH0355889A (en) * | 1989-07-25 | 1991-03-11 | Furukawa Electric Co Ltd:The | Manufacture of superconducting multilayered circuit |
| JPH07263767A (en) * | 1994-01-14 | 1995-10-13 | Trw Inc | Planer type high-temperature superconducting integrated circuit using ion implantation |
| US5593918A (en) * | 1994-04-22 | 1997-01-14 | Lsi Logic Corporation | Techniques for forming superconductive lines |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4843034A (en) | Fabrication of interlayer conductive paths in integrated circuits | |
| US4070501A (en) | Forming self-aligned via holes in thin film interconnection systems | |
| US5003375A (en) | MIS type semiconductor integrated circuit device having a refractory metal gate electrode and refractory metal silicide film covering the gate electrode | |
| US4381595A (en) | Process for preparing multilayer interconnection | |
| JP3113800B2 (en) | Method for forming wiring of semiconductor device | |
| EP0300567A2 (en) | Method of applying thin layers of oxidic superconductive material | |
| JPS63291436A (en) | Manufacture of semiconductor device | |
| JPH0226055A (en) | Manufacture of semiconductor device | |
| US5554884A (en) | Multilevel metallization process for use in fabricating microelectronic devices | |
| Sirkin et al. | A method of forming contacts between two conducting layers separated by a dielectric | |
| JPH04196122A (en) | Manufacture of semiconductor device | |
| GB2208119A (en) | Method and structure for achieving low contact resistance to aluminium and its alloys | |
| US5686323A (en) | Method of manufacturing a semiconductor device having an out diffusion preventing film | |
| JP2614942B2 (en) | Superconducting integrated circuit device manufacturing method | |
| JPH02170424A (en) | Manufacture of semiconductor device | |
| JPS63304646A (en) | Formation of superconductor thin film pattern | |
| JPS63152164A (en) | Semiconductor device | |
| JPS60217645A (en) | Manufacture of semiconductor device | |
| JPH0234195B2 (en) | ||
| JPS61174628A (en) | Manufacture of semiconductor device | |
| JPS63276243A (en) | Oxide superconducting wiring structure | |
| JPH06163545A (en) | Wiring structure of semiconductor device and fabrication thereof | |
| JPS6249644A (en) | Manufacture of semiconductor device | |
| JPS636859A (en) | Manufacture of semiconductor device | |
| JPH03276763A (en) | Semiconductor device |