JPH0817926A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0817926A JPH0817926A JP16899194A JP16899194A JPH0817926A JP H0817926 A JPH0817926 A JP H0817926A JP 16899194 A JP16899194 A JP 16899194A JP 16899194 A JP16899194 A JP 16899194A JP H0817926 A JPH0817926 A JP H0817926A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon oxide
- reflow
- oxide film
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に不純物を含有するシリコンガラス膜にリフ
ロー処理を施す工程を含む半導体装置の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a step of subjecting a silicon glass film containing impurities to a reflow process.
【0002】[0002]
【従来の技術】近年、半導体集積回路の高集積化ととも
に、表面層の平坦化が重要視されている。その中で、高
温熱処理に耐え得るポリシリコンや高融点金属等の配線
層の段差形状を解消するために平坦化を行うに当たっ
て、配線層上層の層間絶縁膜としてBPSG(Boro-Pho
spho Silicate Glass)膜が用いられている。BPSG膜
とは、シリコン酸化膜中にホウ素(B)とリン(P)を
導入してガラス転移温度(リフロー軟化温度)を下げた
絶縁膜をいい、BPSG膜を窒素雰囲気中で900℃程
度の温度で熱処理することにより、リフローと呼ばれる
流動現象が生じ、段差形状を有する表面が平坦化され
る。2. Description of the Related Art In recent years, along with the high integration of semiconductor integrated circuits, it has become important to flatten the surface layer. Among them, BPSG (Boro-Pho) is used as an interlayer insulating film in the upper layer of the wiring layer in performing planarization to eliminate the step shape of the wiring layer such as polysilicon and refractory metal that can withstand high temperature heat treatment.
A spho Silicate Glass) film is used. The BPSG film is an insulating film in which boron (B) and phosphorus (P) are introduced into a silicon oxide film to lower the glass transition temperature (reflow softening temperature). The BPSG film has a temperature of about 900 ° C. in a nitrogen atmosphere. By performing heat treatment at a temperature, a flow phenomenon called reflow occurs, and the surface having a step shape is flattened.
【0003】しかし、素子の微細化に伴ってリフロー温
度をさらに低温化する必要が生じている。そのための方
法として、リフロー処理の雰囲気を窒素から水蒸気にす
る方法が知られている。この方法について図3を参照し
て簡単に説明する。However, with the miniaturization of elements, it is necessary to further lower the reflow temperature. As a method therefor, a method is known in which the atmosphere of the reflow treatment is changed from nitrogen to steam. This method will be briefly described with reference to FIG.
【0004】まず、図3(a)に示すように、半導体基
板11上に配線層12をパターン形成し、その後にシリ
コン窒化膜17を全面に成膜する。First, as shown in FIG. 3A, a wiring layer 12 is patterned on a semiconductor substrate 11, and then a silicon nitride film 17 is formed on the entire surface.
【0005】次に、図3(b)に示すように、シリコン
窒化膜17上にBPSG膜15を全面に成膜する。Next, as shown in FIG. 3B, a BPSG film 15 is formed on the entire surface of the silicon nitride film 17.
【0006】次に、図3(c)に示すように、水蒸気雰
囲気下で熱処理を行い、BPSG膜15をリフローさせ
て配線層12による段差形状を平坦化する。Next, as shown in FIG. 3C, heat treatment is performed in a steam atmosphere to reflow the BPSG film 15 to flatten the stepped shape of the wiring layer 12.
【0007】水蒸気雰囲気下で熱処理によってリフロー
軟化温度が低下するのは、水蒸気がBPSG膜中に取り
込まれる際にOH分子となり、Si−O−Si結合がS
i−OH結合に変わることによって結合強度が弱まるた
めである。The reason why the reflow softening temperature is lowered by the heat treatment in the water vapor atmosphere is that when water vapor is taken into the BPSG film, it becomes an OH molecule and the Si--O--Si bond becomes S.
This is because the bond strength is weakened by changing to the i-OH bond.
【0008】[0008]
【発明が解決しようとする課題】しかしながら、BPS
G膜15内のSi−OH結合を構成するOH分子は、酸
化膜中での拡散係数が大きいために熱処理中に容易に拡
散し、半導体基板11や配線層12を酸化させる。そこ
で、この酸化を防ぐために、OH分子の拡散係数が小さ
いシリコン窒化膜17をBPSG膜15下に酸化防止膜
として形成する必要があったが、シリコン窒化膜17は
シリコン酸化膜に比べてストレスが大きい。つまり、上
述の水蒸気雰囲気下での熱処理によってBPSG膜15
をリフローする方法は、リフロー軟化温度を低下するこ
とができるという利点があったものの、シリコン窒化膜
17のストレスによって半導体装置の信頼性を低下させ
るという問題点があった。[Problems to be Solved by the Invention] However, BPS
The OH molecules forming the Si—OH bond in the G film 15 easily diffuse during the heat treatment due to the large diffusion coefficient in the oxide film, and oxidize the semiconductor substrate 11 and the wiring layer 12. Therefore, in order to prevent this oxidation, it was necessary to form a silicon nitride film 17 having a small diffusion coefficient of OH molecules as an anti-oxidation film under the BPSG film 15. However, the silicon nitride film 17 has less stress than the silicon oxide film. large. That is, the BPSG film 15 is formed by the heat treatment in the above-described steam atmosphere.
Although the method of reflowing has an advantage that the reflow softening temperature can be lowered, it has a problem that the stress of the silicon nitride film 17 lowers the reliability of the semiconductor device.
【0009】そこで、本発明の目的は、リフロー軟化温
度を低いまま維持しつつ、シリコン窒化膜を用いる必要
がなくストレスの小さいリフローを行うことのできる半
導体装置の製造方法を提供することにある。Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of performing reflow with small stress without using a silicon nitride film while keeping the reflow softening temperature low.
【0010】[0010]
【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体装置の製造方法は、半導体基板上に
シリコン酸化膜を形成する第1の工程と、不活性ガスを
用いて前記シリコン酸化膜をスパッタエッチングする第
2の工程と、前記シリコン酸化膜上に不純物を含有する
シリコンガラス膜を形成する第3の工程と、前記シリコ
ンガラス膜にリフロー処理を施す第4の工程とを有す
る。In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention uses a first step of forming a silicon oxide film on a semiconductor substrate and an inert gas. A second step of sputter etching the silicon oxide film, a third step of forming a silicon glass film containing impurities on the silicon oxide film, and a fourth step of performing a reflow process on the silicon glass film. Have.
【0011】[0011]
【作用】不活性ガスを用いてシリコン酸化膜をスパッタ
エッチングすることにより、シリコン酸化膜の表面に加
工変質層が形成され、この加工変質層がリフロー処理の
際の半導体基板や配線層の酸化を防止する。従って、リ
フロー軟化温度を低くできるとともに、シリコン窒化膜
を用いる必要のない低ストレスのリフローを行うことが
できる。[Function] A work-affected layer is formed on the surface of the silicon oxide film by sputter etching the silicon oxide film using an inert gas, and this work-affected layer prevents oxidation of the semiconductor substrate or wiring layer during reflow treatment. To prevent. Therefore, the reflow softening temperature can be lowered and the low stress reflow can be performed without using the silicon nitride film.
【0012】[0012]
【実施例】以下、本発明の実施例を図面を参照して説明
する。Embodiments of the present invention will be described below with reference to the drawings.
【0013】図1に、本実施例の半導体装置の製造方法
を工程順に示す。FIG. 1 shows a method of manufacturing a semiconductor device of this embodiment in the order of steps.
【0014】まず、図1(a)に示すように、半導体基
板1上に膜厚0.3μm程度のポリシリコン配線層2を
パターン形成する。しかる後、膜厚0.2μm程度のシ
リコン酸化膜3を全面に低圧熱CVD法で成膜する。
尚、ポリシリコン配線層2の代わりに、タングステンシ
リサイド膜等の高融点金属単層又は高融点金属とポリシ
リコンとの積層構造膜を用いてもよい。また、シリコン
酸化膜3の成膜法として常圧熱CVD法やプラズマCV
D法を用いることができる。First, as shown in FIG. 1A, a polysilicon wiring layer 2 having a film thickness of about 0.3 μm is patterned on a semiconductor substrate 1. Then, a silicon oxide film 3 having a thickness of about 0.2 μm is formed on the entire surface by low pressure thermal CVD.
Instead of the polysilicon wiring layer 2, a high melting point metal single layer such as a tungsten silicide film or a laminated structure film of a high melting point metal and polysilicon may be used. Further, as a method for forming the silicon oxide film 3, a normal pressure thermal CVD method or a plasma CV method is used.
Method D can be used.
【0015】次に、図1(b)に示すように、シリコン
酸化膜3の表面をアルゴンガスを用いて0.05μm程
度スパッタエッチングする。これによって、シリコン酸
化膜3の表面層には、0.05μm程度の加工変質層4
が形成される。スパッタエッチングの条件は、平行平板
型のRFエッチャーを用いて圧力300Pa程度、RF
出力500W程度、アルゴンガス流量50sccm程度
である。尚、アルゴン以外に窒素等の不活性ガスを用い
てもよい。Next, as shown in FIG. 1B, the surface of the silicon oxide film 3 is sputter-etched by using argon gas to a thickness of about 0.05 μm. As a result, the work-affected layer 4 having a thickness of about 0.05 μm is formed on the surface layer of the silicon oxide film 3.
Is formed. The conditions for the sputter etching are: a parallel plate type RF etcher, a pressure of about 300 Pa, and an RF
The output is about 500 W and the argon gas flow rate is about 50 sccm. In addition to argon, an inert gas such as nitrogen may be used.
【0016】この加工変質層4の構造について、図2を
参照して説明する。スパッタエッチングする前のシリコ
ン酸化膜3は、図2(a)に示すように、シリコン原子
(Si)の4方位に酸素原子(O)が結合した状態であ
る。従って、水酸基OH等の拡散を阻止できず、下地の
半導体基板1や配線層2の酸化が進行する。一方、シリ
コン酸化膜3の表面をスパッタエッチングすると、その
表面層は図2(b)に示すように、シリコンと酸素の結
合状態が乱れ、未結合手が多数存在するようになる。よ
って、リフロー処理時に拡散してきた水酸基OH等はこ
の部分で捕獲されるため、加工変質層4は下地膜の酸化
防止膜として機能する。The structure of the work-affected layer 4 will be described with reference to FIG. As shown in FIG. 2A, the silicon oxide film 3 before the sputter etching is in a state in which oxygen atoms (O) are bonded to the four directions of silicon atoms (Si). Therefore, the diffusion of the hydroxyl group OH and the like cannot be prevented, and the underlying semiconductor substrate 1 and the wiring layer 2 are oxidized. On the other hand, when the surface of the silicon oxide film 3 is sputter-etched, as shown in FIG. 2B, the bonding state of silicon and oxygen is disturbed in the surface layer, and many dangling bonds are present. Therefore, since the hydroxyl group OH and the like diffused during the reflow process are captured in this portion, the work-affected layer 4 functions as an antioxidant film of the base film.
【0017】次に、図1(c)に示すように、加工変質
層4上に膜厚0.5μm程度のBPSG膜5を常圧熱C
VD法によって成膜する。尚、BPSG膜5は、低圧熱
CVD法やプラズマCVD法を用いて成膜してもよい。
また、BPSG膜5に含まれるリン及びホウ素の代わり
にゲルマニウムや砒素を添加したシリコンガラス膜(シ
リケートガラス)を用いてもよい。Next, as shown in FIG. 1C, a BPSG film 5 having a thickness of about 0.5 μm is formed on the work-affected layer 4 under normal pressure heat C.
The film is formed by the VD method. The BPSG film 5 may be formed using a low pressure thermal CVD method or a plasma CVD method.
A silicon glass film (silicate glass) to which germanium or arsenic is added instead of phosphorus and boron contained in the BPSG film 5 may be used.
【0018】次に、図1(d)に示すように、水蒸気雰
囲気下で温度850℃、30分の熱処理を行い、BPS
G膜5をリフローさせてポリシリコン配線層2の段差形
状の平坦化を行う。このとき、上述のように、加工変質
層4が下地の半導体基板1及びポリシリコン配線層2の
酸化防止膜として機能する。Next, as shown in FIG. 1 (d), a heat treatment is performed in a steam atmosphere at a temperature of 850 ° C. for 30 minutes to obtain BPS.
The G film 5 is reflowed to flatten the step shape of the polysilicon wiring layer 2. At this time, as described above, the work-affected layer 4 functions as an antioxidant film for the underlying semiconductor substrate 1 and the polysilicon wiring layer 2.
【0019】以上説明したように、本実施例によると、
シリコン酸化膜3の表面に形成した加工変質層4がリフ
ロー処理時にシリコン酸化膜3中を拡散するOH分子を
捕獲する酸化防止膜として機能し、リフロー処理中にシ
リコン基板1や配線層2が酸化されるのを防止すること
ができる。つまり、水蒸気雰囲気下で比較的低温のリフ
ローができ、且つ、従来のようにストレスの高いシリコ
ン窒化膜を用いることなく下地膜の酸化防止ができて、
半導体装置の信頼性及び集積度を向上させることができ
る。As described above, according to this embodiment,
The work-affected layer 4 formed on the surface of the silicon oxide film 3 functions as an antioxidant film for capturing OH molecules diffused in the silicon oxide film 3 during the reflow process, and the silicon substrate 1 and the wiring layer 2 are oxidized during the reflow process. Can be prevented. In other words, it is possible to perform reflow at a relatively low temperature in a water vapor atmosphere, and prevent the underlying film from being oxidized without using a silicon nitride film with high stress as in the conventional case.
The reliability and the degree of integration of the semiconductor device can be improved.
【0020】[0020]
【発明の効果】本発明によると、シリコン酸化膜を不活
性ガスを用いてスパッタエッチングすることにより、シ
リコン酸化膜の表面に加工変質層が形成され、この加工
変質層がリフロー処理の際の半導体基板や配線層の酸化
を防止する。従って、リフロー軟化温度を低くできると
ともに、シリコン窒化膜を用いる必要のない低ストレス
のリフローを行うことができる。よって、半導体装置の
信頼性及び集積度を向上させることができる。According to the present invention, the work-affected layer is formed on the surface of the silicon oxide film by sputter etching the silicon oxide film with the use of an inert gas, and the work-affected layer is formed in the semiconductor during reflow treatment. Prevents oxidation of the substrate and wiring layers. Therefore, the reflow softening temperature can be lowered and the low stress reflow can be performed without using the silicon nitride film. Therefore, the reliability and the degree of integration of the semiconductor device can be improved.
【図1】本発明の実施例の半導体装置の製造方法を工程
順に示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in process order.
【図2】シリコンと酸素との結合の様子を示す模式図で
ある。FIG. 2 is a schematic diagram showing a state of bonding between silicon and oxygen.
【図3】従来の半導体装置の製造方法を工程順に示す概
略断面図である。FIG. 3 is a schematic cross-sectional view showing a method of manufacturing a conventional semiconductor device in the order of steps.
1 半導体基板 2 ポリシリコン配線層 3 シリコン酸化膜 4 加工変質層 5 BPSG膜 1 semiconductor substrate 2 polysilicon wiring layer 3 silicon oxide film 4 work-affected layer 5 BPSG film
Claims (1)
る第1の工程と、 不活性ガスを用いて前記シリコン酸化膜をスパッタエッ
チングする第2の工程と、 前記シリコン酸化膜上に不純物を含有するシリコンガラ
ス膜を形成する第3の工程と、 前記シリコンガラス膜にリフロー処理を施す第4の工程
とを有することを特徴とする半導体装置の製造方法。1. A first step of forming a silicon oxide film on a semiconductor substrate, a second step of sputter etching the silicon oxide film using an inert gas, and containing impurities on the silicon oxide film. A method of manufacturing a semiconductor device, comprising: a third step of forming a silicon glass film, and a fourth step of subjecting the silicon glass film to a reflow process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16899194A JPH0817926A (en) | 1994-06-28 | 1994-06-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16899194A JPH0817926A (en) | 1994-06-28 | 1994-06-28 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0817926A true JPH0817926A (en) | 1996-01-19 |
Family
ID=15878335
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16899194A Withdrawn JPH0817926A (en) | 1994-06-28 | 1994-06-28 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0817926A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6569782B2 (en) | 2000-06-15 | 2003-05-27 | Samsung Electronics Co., Ltd. | Insulating layer, semiconductor device and methods for fabricating the same |
US6730619B2 (en) | 2000-06-15 | 2004-05-04 | Samsung Electronics Co., Ltd. | Method of manufacturing insulating layer and semiconductor device including insulating layer |
US7645705B2 (en) | 2005-12-29 | 2010-01-12 | Dongbu Hitek Co., Ltd. | Method of fabricating a semiconductor device having a pre metal dielectric liner |
-
1994
- 1994-06-28 JP JP16899194A patent/JPH0817926A/en not_active Withdrawn
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6569782B2 (en) | 2000-06-15 | 2003-05-27 | Samsung Electronics Co., Ltd. | Insulating layer, semiconductor device and methods for fabricating the same |
US6730619B2 (en) | 2000-06-15 | 2004-05-04 | Samsung Electronics Co., Ltd. | Method of manufacturing insulating layer and semiconductor device including insulating layer |
US7180129B2 (en) | 2000-06-15 | 2007-02-20 | Samsung Electronics Co., Ltd. | Semiconductor device including insulating layer |
US7645705B2 (en) | 2005-12-29 | 2010-01-12 | Dongbu Hitek Co., Ltd. | Method of fabricating a semiconductor device having a pre metal dielectric liner |
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Legal Events
Date | Code | Title | Description |
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A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20010904 |