JPH08181209A - Manufacture of semiconductor device and semiconductor manufacturing device - Google Patents

Abstract

PURPOSE: To improve the flatness of the surface of a reflow insulating film obtained on a semiconductor substrate by adopting reflow insulating-film forming technique, and to enhance crack resistance. CONSTITUTION: A process, in which a lower layer wiring 22 is formed onto a semiconductor substrate 20, nd a reflow-film forming process, in which a semiconductor substrate after the formation of a lower layer wiring 22 is aranged into a reaction chamber for a low pressure CVD device, the inside on the reaction chamber is supplied continuously with SiH4 gas while H2 O2 is fed intermittently and SiH4 gas and H2 O2 are reacted mutually and a reflow SiO2 film 23 having a reflow shape is formed onto the semiconductor substrate, are provided at the time of a multilayer interconnection process at the time of the manufacture of a semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method and a semiconductor manufacturing apparatus, and more particularly to a method for forming an interlayer insulating film and an interlayer insulating film forming apparatus for a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor devices increases, so-called multi-layer wiring is being formed, in which wiring materials are formed in multiple layers on a substrate, and the manufacturing process of a semiconductor device having such a multi-layer wiring structure is It is becoming more complicated and longer.

In particular, the step of forming the multi-layered wiring occupies a large portion of the manufacturing cost of the semiconductor device, and there is an increasing demand for reduction of the multi-layered wiring step in order to reduce the cost of the semiconductor device.

Here, a conventional process for forming a multi-layer wiring will be described. First, after depositing the first wiring material for the lower layer wiring on the insulating film on the semiconductor substrate, the lower layer wiring is patterned.

Next, a first insulating film is formed on the lower layer wiring and an insulating film is embedded between the lower layer wirings. At this point, depending on the pattern of the lower layer wiring, etc., the first
There is a step on the surface of the insulating film, and if it remains as it is, it will adversely affect the subsequent deposition of the second wiring material for the upper layer wiring and the patterning of the upper layer wiring, resulting in disconnection due to step breakage of the upper layer wiring, short circuit, May cause serious defects.

Therefore, usually, before depositing the second wiring material on the first insulating film, the surface of the first insulating film, which is the base of the second wiring material, is flattened by resist etching back. After alleviating the step difference, a second insulating film is formed thereon.

The conventional process for forming an interlayer insulating film in which the first insulating film and the second insulating film are laminated is as follows: first film formation → planarization → second film formation and the number of processes. This is a major obstacle to the demand for reduction of the multilayer wiring process as described above.

Further, instead of the method of flattening the surface of the first insulating film as described above, spin on glass (SO) which is an insulating material is formed on the first insulating film.
G) There is also known a method of forming a film to mitigate the step difference in the underlying layer of the upper wiring material.

However, this method requires a large number of heat treatment steps when forming (baking) the SOG film, and it is necessary to remove unnecessary portions of the SOG film by resist etch back in order to ensure the reliability of the upper wiring. However, as a result, the number of steps is large, and again, it is not possible to sufficiently meet the demand for reduction of the multilayer wiring step as described above.

By the way, recently, as one of the techniques for responding to the demand for reduction of the above-mentioned multi-layer wiring process, when forming an interlayer insulating film, as shown in FIG. 3, SiH ₄ gas and H which is an oxidizing agent are used. By reacting with ₂ O ₂ (hydrogen peroxide solution) in a vacuum at a low temperature (for example, about 0 ° C.), a self-flowing (reflow) SiO film is formed on the lower wiring 32 on the insulating film 31 on the semiconductor substrate 30. ₂ films (hereinafter reflow SiO
A method of forming a film (referred to as _two films) 33 is drawing attention.

According to this method, the filling of the insulating film between the wirings of the lower layer wiring 32 and the flattening of the insulating film surface can be achieved at the same time, and the steps up to the flattening can be completed by one film formation. Can be reduced.

However, the reflow SiO ₂ as described above is used.
The film 33 is formed by using SiH during the deposition of the SiO ₂ film 33.
₄ Gas and H ₂ O ₂ as a liquid source are continuously supplied at a constant flow rate. Thus, during deposition of the SiO ₂ film 33, since reflow is characteristic in the case of using the reaction of SiH ₄ gas and H ₂ O ₂ resulting in the SiO ₂ film 33 are sequentially deposited in less sufficiently performed Therefore, the SiO ₂ film 33 having low surface flatness is formed.

Further, the method of forming the reflow SiO ₂ film 33 as described above is
Moisture (H ₂ O) is generated during the formation of the SiO ₂ film 33, and S
A large amount of water is contained in the iO ₂ film 33, and this water in the film causes cracks in the SiO ₂ film 33 in the high temperature heat treatment step after film formation. Processing is required.

[0014]

As described above, the reflow SiO ₂ film obtained when the reflow insulating film forming technique is adopted in the conventional interlayer insulating film forming step in the multilayer wiring step has a flat surface. However, there is a problem that annealing and prebaking are required after the film formation in order to suppress the generation of cracks due to moisture in the film.

The present invention has been made to solve the above-mentioned problems. A reflow SiO ₂ film obtained when a reflow insulating film forming technique is adopted in an interlayer insulating film forming process in a multilayer wiring process of a semiconductor device is provided. It is an object of the present invention to provide a semiconductor device manufacturing method capable of improving surface flatness and crack resistance.

[0016]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a lower layer wiring on a semiconductor substrate,
The semiconductor substrate after the formation of the lower layer wiring is placed in a reaction chamber of a low pressure vapor phase growth apparatus, and SiH ₄ gas is continuously supplied into the reaction chamber and H ₂ O ₂ is intermittently supplied to react with each other. And a reflow film forming step of forming a reflow SiO ₂ film having a reflow shape on the semiconductor substrate.

[0017]

[Function] By adopting the reflow insulating film forming technique in the interlayer insulating film forming step in the multi-layer wiring step, when forming the reflow SiO ₂ film, the semiconductor substrate after the lower layer wiring is formed is placed in the reaction chamber of the reduced pressure vapor phase growth apparatus. , SiH ₄ gas is continuously supplied into the reaction chamber, and H ₂ O ₂ is intermittently supplied,
A reflow SiO ₂ film having a reflow shape is formed on a semiconductor substrate by reacting each other in a temperature range of −10 ° C. or higher and + 10 ° C. or lower in a vacuum of 650 Pa or lower.

As a result, it becomes possible to sufficiently perform reflow, which is a characteristic of the insulating film during the deposition using the reaction of SiH ₄ gas and H ₂ O _2, and to release the moisture in the film. It is possible to form an interlayer insulating film having good flatness and good film quality.

Therefore, it is possible to prevent a serious defect such as disconnection or short circuit due to step disconnection of the upper layer wiring without adversely affecting the subsequent deposition of the upper layer wiring material and the patterning of the upper layer wiring, and the formation of the upper layer wiring can be prevented. No treatment such as annealing or prebaking is required after the film.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 schematically shows an example of the configuration of a low pressure CVD apparatus used in the method for manufacturing a semiconductor device of the present invention.

A low pressure CVD (vapor phase growth) apparatus shown in FIG. 1 is a reaction chamber 11 for low pressure CVD that accommodates a semiconductor substrate.
, SiH ₄ gas supply source 12, and H ₂ O ₂ supply source 13
If, SiH ₄ gas H ₂ O ₂ to intermittently into the reaction chamber 11 from the H ₂ O ₂ supply source 13 as well as continuously supplied to the reaction chamber 11 from the SiH ₄ gas source 12 It is provided with a supply controller 14 for supplying, a vacuum pump 15, and a vacuum controller 16 for keeping the inside of the reaction chamber 11 in a predetermined vacuum state by using the vacuum pump 15.

FIG. 2 shows that the reflow SiO ₂ film deposition and the reflow are alternately repeated when a reflow insulating film forming technique is adopted in the interlayer insulating film forming step in the multilayer wiring step according to the method for manufacturing a semiconductor device of the present invention. Is shown.

An example of a multi-layer wiring process using a reflow insulating film forming technique in the interlayer insulating film forming process according to the method for manufacturing a semiconductor device of the present invention will be described below with reference to FIGS. 1 and 2.

First, a first wiring material (for example, aluminum) for lower wiring is deposited on the insulating film 21 on the semiconductor substrate (generally a silicon wafer) 20 by, for example, a sputtering method, and then a photolithography technique and reactive ion etching are performed. The lower wiring 22 is formed by patterning the first wiring material using the (RIE) technique.

Next, an insulating film is embedded between the lower layer wirings 22 and an insulating film is deposited on the lower layer wirings to form an interlayer insulating film. In the step of forming the interlayer insulating film, the semiconductor substrate 20 after the lower wiring is formed is placed on a quartz boat (not shown) in the reaction chamber 11 of the low pressure CVD apparatus, and SiH ₄ gas is continuously supplied in the reaction chamber. And H ₂ O ₂ are intermittently supplied to react with each other within a temperature range of −10 ° C. or higher and + 10 ° C. or lower (for example, 0 ° C.) in a vacuum of 650 Pa or less, thereby the semiconductor substrate 2
A reflow SiO ₂ film 23 having a reflow shape is obtained on the top surface of the film.

In this case, it is desirable to repeat the supply / non-supply of H ₂ O ₂ at least three times (three times in this example) during the formation of the reflow SiO ₂ film 23. In addition, the H ₂
It is desirable that the supply period of O ₂ is 10 to 90% of the film formation period of the reflow SiO ₂ film 20.

Next, directly on the reflow SiO ₂ film,
Alternatively, after depositing another interlayer insulating film, an opening for a through hole or a via hole is formed, and after depositing a second wiring material for the upper layer wiring, patterning is performed to form an upper layer wiring (not shown). To do.

According to the above embodiment, the reflow insulating film forming technique is adopted in the interlayer insulating film forming step in the multilayer wiring step,
When forming the reflow SiO ₂ film 23, SiH ₄ gas is continuously supplied and H ₂ O ₂ is intermittently supplied.

[0029] In this case, the period during which H ₂ O ₂ is supplied is SiO ₂ film 23 is deposited, reflow rows H ₂ period the supply of O ₂ is stopped deposited film (SiO ₂ film) 23 Therefore, the flatness of the surface of the reflow SiO ₂ film 23 is improved.

[0030] Moreover, the so the supply / non-supply of the H ₂ O ₂ is repeated at least 3 times during the formation of the reflow SiO ₂ film 23, the reflow SiO ₂ film 23 is good flatness of the surface is obtained.

Therefore, there is a possibility of causing serious defects such as disconnection and short circuit due to step breakage of the upper layer wiring without adversely affecting the deposition of the upper layer wiring material after the formation of the reflow SiO ₂ film 23 and the patterning of the upper layer wiring. It becomes possible to prevent.

During the period when the supply of H ₂ O ₂ is stopped, moisture in the film in the deposited film (SiO ₂ film) 23 is released, so that the insulating film is formed in the reflow SiO ₂ film forming step. even moisture contained moisture in the insulating film occurs, film moisture reduces the reflow SiO ₂ film forming step after the completion of the reflow SiO ₂ film 23, the film quality good interlayer insulating film can be obtained in the .

[0033] Thus, it processes such as annealing or pre-baking after forming the reflow SiO ₂ film is not required, generation of cracks due to film moisture reflow SiO ₂ film is reduced, the crack resistance of the reflow SiO ₂ film improves.

[0034]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the surface of the reflow SiO ₂ film obtained when the reflow insulating film forming technique is adopted in the interlayer insulating film forming step in the multilayer wiring step. The flatness can be improved and the crack resistance can be improved. Therefore, reflow Si
It is possible to improve the flatness of the surface of the O ₂ film and further miniaturize the upper layer wiring formed thereon.

[Brief description of drawings]

FIG. 1 is a structural explanatory view schematically showing an example of a low pressure CVD apparatus used in a method for manufacturing a semiconductor device of the present invention.

FIG. 2 shows a state in which deposition and reflow of a reflow SiO ₂ film are alternately repeated when a reflow insulating film forming technique is adopted in an interlayer insulating film forming step in a multilayer wiring step according to a method for manufacturing a semiconductor device of the present invention. Sectional drawing to show.

FIG. 3 is a cross-sectional view showing a state in which a reflow SiO ₂ film is continuously deposited when a reflow insulating film forming technique is used in an interlayer insulating film forming step in a conventional semiconductor device multilayer wiring step.

[Explanation of symbols]

11 ... Reaction chamber for low pressure CVD, 12 ... SiH ₄ gas supply source, 13 ... H ₂ O ₂ supply source, 14 ... Supply control device, 15
... vacuum pump, 16 ... vacuum control device, 20 ... semiconductor substrate, 22 ... lower wiring, 23 ... reflow SiO ₂ film.

Claims (4)

[Claims] 1. A step of forming a lower layer wiring on a semiconductor substrate, and disposing the semiconductor substrate after the lower layer wiring is formed in a reaction chamber of a reduced pressure vapor phase growth apparatus, and continuously supplying SiH ₄ gas into the reaction chamber. And a reflow film forming step of forming a reflow SiO ₂ film having a reflow shape on the semiconductor substrate by intermittently supplying H ₂ O ₂ and reacting with each other. . 2. The method of manufacturing a semiconductor device according to claim 1, wherein the supply / non-supply of the H ₂ O _{2 is performed by} the reflow S.
A method for manufacturing a semiconductor device, which is repeated at least three times during the formation of the iO ₂ film. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the supply period of the H ₂ O ₂ is 10 to 90% of the film formation period of the reflow SiO ₂ film. Manufacturing method of semiconductor device. 4. A reaction chamber for low pressure vapor phase growth containing a semiconductor substrate, a supply control device for continuously supplying SiH ₄ gas and intermittently supplying H ₂ O ₂ into the reaction chamber, A semiconductor manufacturing apparatus, comprising: a vacuum controller for maintaining a predetermined vacuum state in the reaction chamber.