JP3192903B2 - Semiconductor device manufacturing method and semiconductor manufacturing apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for manufacturing a semiconductor device, and more particularly to a method and an apparatus for forming an interlayer insulating film of a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor devices has increased, so-called multilayer wiring, in which wiring materials are formed in multiple layers on a substrate, has been advanced, and the manufacturing process of a semiconductor device having such a multilayer wiring structure has been increasing. It is becoming more complicated and longer.

[0003] In particular, the process of forming the multilayer wiring accounts for a large proportion of the manufacturing cost of the semiconductor device, and there is an increasing demand for a reduction in the number of multilayer wiring processes in order to reduce the cost of the semiconductor device.

Here, a conventional process for forming a multilayer wiring will be described. First, after depositing a first wiring material for a lower wiring, patterning of the lower wiring is performed, and a first insulating film is formed on the lower wiring and an insulating film is embedded between the lower wirings. At this point, a step exists on the surface of the first insulating film depending on the pattern of the lower wiring, etc., and if this is left as it is, the step of depositing the second wiring material for the upper wiring and the patterning of the upper wiring will be performed. Sometimes has an adverse effect,
A serious defect such as disconnection or short circuit due to disconnection of the upper wiring may occur.

Therefore, usually, before depositing the second wiring material on the first insulating film, the surface of the underlying first insulating film is flattened by resist etch back to reduce the step. After that, a second insulating film is formed thereon.

The conventional process of forming an interlayer insulating film in which the first insulating film and the second insulating film are stacked as described above involves a first film forming process, a flattening process, and a second film forming process. This is a great obstacle to the above-mentioned demand for reduction in the number of multilayer wiring steps.

As one of the techniques for flattening the surface of an interlayer insulating film in response to a demand for a reduction in the number of multilayer wiring steps, an AP is used.
L (Advanced Planarisation Layer) process reported (literature; Matsuura et.al., IEEE Tech. Dig., Pp117,199)
4) Have been.

In the APL process, when forming an interlayer insulating film, SiH ₄ gas and H ₂ O ₂ (hydrogen peroxide solution) as an oxidizing agent are reacted at a low temperature (for example, about 0 ° C.) in a vacuum. Self-flowing (reflow) SiO ₂ film on the lower wiring (hereinafter referred to as reflow SiO ₂ film)
Is formed.

According to this method, the burying of the insulating film between the lower wiring layers and the flattening of the insulating film surface can be achieved at the same time.
Since the steps up to planarization are completed by one film formation, the number of multilayer wiring steps can be reduced.

Before the reflow SiO ₂ film is formed, the first plasma CVD method is applied to the first wiring on the lower wiring.
First plasma CV as an interlayer insulating film (base insulating film)
After forming a D insulating film and forming the above-mentioned reflow SiO ₂ film, a second plasma CVD insulating film is formed as a second interlayer insulating film (cap film) on the reflow SiO ₂ film by a normal plasma CVD method. Perform furnace annealing.

However, the reflow insulating film formed by the above-described method has a high relative dielectric constant of about 4.5 to 4.7 (about 3.9 for a normal SiO ₂ film formed by thermal oxidation).
Therefore, there is a problem that it is difficult to follow a low dielectric constant insulating film required for a high-speed device.

Therefore, as a method of lowering the relative dielectric constant, it is effective to incorporate fluorine (F) into the reflow insulating film during the formation of the reflow insulating film. In the formation method, fluorine gas is difficult to decompose, so it is difficult to take in fluorine.

[0013]

As described above, a reflow SiO ₂ film obtained when a reflow insulating film forming technique is employed in an interlayer insulating film forming step in a conventional multilayer wiring step has a high relative dielectric constant. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a ratio of a reflow insulating film obtained when a reflow insulating film forming technique is employed in an interlayer insulating film forming process in a multilayer wiring process of a semiconductor device. Dielectric constant can be lowered,
It is an object of the present invention to provide a method of manufacturing a semiconductor device which can realize an interlayer insulating film having excellent flatness at low cost without performing a flattening step.

[0015]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a reaction chamber containing a semiconductor substrate; a SiH ₄ gas, a H ₂ O ₂ gas, and a fluorine-based gas in a radical state passed through a microwave waveguide. Is introduced in a vacuum of 665 Pa or less within a temperature range of -10 ° C or more and + 10 ° C or less.
A reflow film forming step of forming a reflow SiO ₂ film having a reflow shape on the semiconductor substrate by reacting H ₄ gas, H ₂ O ₂ and a fluorine-based gas with each other.

Further, the semiconductor manufacturing apparatus of the present invention includes a chamber for accommodating a semiconductor substrate and depositing and forming a vapor phase growth insulating film on the semiconductor substrate; a SiH ₄ gas supply pipe connected to the chamber; An H ₂ O ₂ supply pipe connected to the chamber, a microwave waveguide connected to the chamber, a microwave generator for generating microwaves and supplying microwaves to the microwave waveguide, A fluorine-based gas supply source for supplying a fluorine-based gas to one end of the microwave waveguide is provided.

[0017]

According to the manufacturing method and the semiconductor manufacturing apparatus of the present invention, a reflow insulating film forming technique is employed in an interlayer insulating film forming step in a multilayer wiring step, and SiH ₄ is accommodated in a reaction chamber containing a semiconductor substrate after forming an insulating film. A gas, H ₂ O ₂ and a fluorine-based gas in a radical state through a microwave waveguide are introduced, and 5 Torr = 5 × 133.322 Pa (about 665 P)
a) By reacting the above SiH ₄ gas, H ₂ O ₂ and fluorine-based gas with each other in a temperature range of −10 ° C. to + 10 ° C. in the following vacuum, reflow S
It is possible to form an iO ₂ film.

As a result, an interlayer insulating film having excellent flatness can be realized at low cost without performing a flattening step. In addition, when the reflow SiO ₂ film is formed by the low-temperature and low-pressure CVD method as described above, since a fluorine-based gas in a radical state is introduced, the reflow SiO ₂ film is formed.
_2. It was confirmed that fluorine was easily incorporated into the film during the formation of the film, and the relative dielectric constant of the reflow SiO ₂ film could be reduced to 3.6 or less.

[0019]

An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1A schematically shows an example of the configuration of a multi-chamber type semiconductor manufacturing apparatus used in the semiconductor device manufacturing method of the present invention.

In FIG. 1A, reference numeral 10 denotes a plasma CV.
D apparatus, 20 is a low-pressure CVD apparatus, 1 is a cassette loader chamber in which a semiconductor substrate is accommodated and set, 2 is the cassette loader chamber 1 and the reaction chamber of the plasma CVD apparatus 10 or the reaction chamber of the low-pressure CVD apparatus 20. It is a robot arm that transfers (loads / unloads) semiconductor substrates between them.

The above-mentioned plasma CVD apparatus 10 has a normal configuration, and an example of the configuration is schematically shown in FIG. In FIG. 1B, 11 is a reaction chamber (chamber), 12 is an upper electrode (shower head), 13 is a lower electrode (table), 14 is an exhaust port, 15 is a process gas supply pipe, and 16 is a high frequency power supply pipe. It is.

The reduced-pressure CVD apparatus has a structure in which a fluorine-based gas in a radical state through a microwave waveguide can be introduced into a reduced-pressure CVD apparatus having a normal configuration. Is schematically shown in FIG. 1 (c).

In FIG. 1C, 21 is a reaction chamber (chamber), 22 is an upper electrode (shower head), 23 is a lower electrode (table), 24 is an exhaust port, and 25 is a SiH connected to the chamber 11. ₄ gas supply pipe, 26 is an H ₂ O ₂ supply pipe connected to the chamber 11, 27 is connected to the chamber 11, and a microwave waveguide in which a fluorine-based gas is supplied to a fluorine-based gas inlet at one end thereof. tube,
Reference numeral 28 denotes a microwave generator for generating a microwave and supplying the microwave to the middle of the microwave waveguide, and 29 denotes a heater for heating a part of the H ₂ O ₂ supply pipe 26.

FIGS. 2A to 2E show the semiconductor device manufacturing apparatus and the reflow insulating film forming technique of FIG. 1 employed in the interlayer insulating film forming step in the multilayer wiring step according to the semiconductor device manufacturing method of the present invention. An example of the case is shown.

First, as shown in FIG. 2A, a first wiring material for a lower wiring (for example, a metal such as aluminum containing Si or Cu) is formed on an insulating film 31 on a semiconductor substrate (for example, a silicon substrate) 30. After depositing a wiring material) by, for example, a sputtering method, the lower wiring 32 is formed by patterning the first wiring material using a photolithography technique and a reactive ion etching (RIE) technique.

Next, using the semiconductor manufacturing apparatus, an insulating film is buried between the lower wirings 32 and an insulating film is deposited on the lower wirings to form an interlayer insulating film. In the step of forming the interlayer insulating film, first, the semiconductor substrate 30 after the lower wiring is formed is set on a boat made of, for example, quartz in the cassette loader chamber 1.

Next, the interior of the cassette loader chamber 1 is set to a vacuum state of 100 mTorr or less using a dry pump (not shown), and the semiconductor substrate 30 is moved by the robot arm 2 into the reaction chamber 11 of the plasma CVD apparatus 10. Carry in. The inside of the reaction chamber 11 of the plasma CVD apparatus 10 is set to a vacuum state of 5 mTorr or less and the lower electrode 13 is set to about 300 ° C., and the entire surface of the semiconductor substrate 20 is 0.1 μm or more (100 nm in this example). A first plasma SiO ₂ film 33 having a thickness of ₃ nm is formed.

Next, the semiconductor substrate 30 is transferred by the robot arm 2 from the reaction chamber 11 of the plasma CVD apparatus to the reaction chamber 21 of the low pressure CVD apparatus. Then, SiH ₄ gas is introduced into the reaction chamber 21 of the reduced-pressure CVD apparatus at a flow rate of 120 sccm from the SiH ₄ gas supply source via the SiH ₄ gas supply pipe 25, and H ₂ O _{2 is} supplied from the H ₂ O ₂ supply source. 0.6 g of H ₂ O ₂ via the ₂ O ₂ supply pipe 26
Per minute, an inert gas (eg, N ₂ gas) is introduced at a flow rate of 500 sccm, and a radical fluorine-based gas (eg, CF ₄ gas) passed through the microwave waveguide. Is introduced at a flow rate of 20 sccm, and reacted with each other in a vacuum of 5 Torr or less (500 mTorr in this example) within a temperature range of -10 ° C. or more and + 10 ° C. or less (for example, 0 ° C.), as shown in FIG. 0.4 μm having a reflow shape on the semiconductor substrate 30
As described above, the reflow SiO ₂ film 34 having a thickness of 1.4 μm or less (0.8 μm in this example) is obtained.

Next, as shown in FIG. 2C, the semiconductor substrate 30 is immersed in the reaction chamber 11 of the low-pressure CVD apparatus in a vacuum of 5 mTorr or less for 30 seconds or more (30 seconds in this example).
put.

Next, the semiconductor substrate 30 is transferred by the robot arm 2 from the reaction chamber 21 of the low pressure CVD apparatus to the reaction chamber 11 of the plasma CVD apparatus. Then, as shown in FIG. 2D, in a reaction chamber of the plasma CVD apparatus 10, at a high temperature of 300 ° C. or more and less than 450 ° C. (300 ° C. in this example) for a time of 120 seconds or more and less than 600 seconds (this (120 seconds in the example).

Thereafter, as shown in FIG. 2E, the entire surface of the semiconductor substrate 30 is 0.3 μm or more (300 n in this example).
A second plasma SiO ₂ film 35 having a thickness of m) is formed. Thereafter, the semiconductor substrate 30 is taken out of the semiconductor manufacturing apparatus, and is removed using another semiconductor manufacturing apparatus.
Perform furnace annealing at 30 ° C. for 30 minutes.

Thereafter, etching is performed to open a contact hole or a via hole in the interlayer insulating film,
After depositing a second wiring material for the upper wiring, patterning is performed to form an upper wiring.

According to the above embodiment, the reflow insulating film forming technique is employed in the interlayer insulating film forming step in the multilayer wiring step.
Si in the reaction chamber containing the semiconductor substrate after forming the insulating film
H ₄ gas, H ₂ O _2, and a fluorine-based gas in a radical state through a microwave waveguide are introduced, and the SiH ₄ gas is introduced in a vacuum of 5 Torr or less and at a temperature of -10 ° C. or more and + 10 ° C. or less. By reacting H ₂ O ₂ and a fluorine-based gas with each other, a reflow SiO ₂ film is formed on the insulating film by a low pressure CVD method.

Thus, an interlayer insulating film having excellent flatness can be realized at low cost without performing a flattening step. Moreover, the reflow SiO 2 is formed by the low pressure CVD method.
_In forming the _two films, since a fluorine-based gas in a radical state is introduced, it is easy to incorporate fluorine into the film during the formation of the reflow SiO ₂ film.
It was confirmed that the relative dielectric constant of the _two films could be reduced to 3.6 or less.

It should be noted, left for a predetermined time or more during the predetermined vacuum after forming the reflow SiO ₂ film 34, further, by leaving a predetermined time or more during the predetermined high temperature, the insulation in the step of forming the reflow SiO ₂ film 34 Even if moisture is generated during the film formation and moisture is contained in the insulating film, it is possible to obtain a reflow SiO ₂ film 34 with good crack resistance by controlling to reduce the moisture in the insulating film. become.

Therefore, it is possible to prevent a serious defect such as disconnection or short circuit due to disconnection of the upper wiring without adversely affecting the deposition of the upper wiring after the formation of the interlayer insulating film and the patterning of the upper wiring. Becomes possible.

When a heat treatment is performed at 450 ° C. for 30 minutes after the formation of the reflow SiO ₂ film 34 obtained in the above embodiment, the plasma SiO ₂ film is formed on the reflow SiO ₂ film 34 and on the reflow SiO ₂ film. ₂ film (cap film)
A parameter cap thickness in the case of forming the cracking of the reflow SiO ₂ film 34 caused by such release of moisture contained in the reflow SiO ₂ film 34 (cracks) was measured the situation that occurred. As a result, the reflow SiO ₂ film 34 obtained in the present embodiment has the same crack characteristics as that of the conventional example when no cap film is present, but does not cause cracks when the cap film is present. The upper limit increased to approximately 1.4 μm, confirming that crack resistance was improved.

[0038]

As described above, according to the method of manufacturing a semiconductor device of the present invention, a reflow insulating film obtained when a reflow insulating film forming technique is employed in a step of forming an interlayer insulating film in a multilayer wiring process of a semiconductor device. Can be easily increased, and an interlayer insulating film having excellent flatness can be realized at low cost without performing a flattening step.

[Brief description of the drawings]

FIG. 1 is a configuration explanatory view schematically showing an example of a semiconductor manufacturing apparatus used in a method of manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing an example of a multi-layer wiring process employing a reflow insulating film forming technique in an interlayer insulating film forming process according to the method of manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

1 ... cassette loader room, 2 ... robot arm, 10 ...
Plasma CVD apparatus, 11, 21: reaction chamber (chamber), 12, 22: upper electrode (shower head), 1
3, 23: lower electrode (table), 14, 24: exhaust port, 15: process gas supply pipe, 16: high frequency power supply pipe, 20: reduced pressure CVD apparatus, 25: SiH ₄ gas supply pipe, 26: H ₂ O ₂ supply pipe, 27 ... microwave waveguide,
28 microwave generator, 29 heater, 30 semiconductor substrate, 31 insulating film, 32 lower wiring, 33 first
Plasma CVD film, 34 ... reflow SiO ₂ film, 35
... Second plasma CVD film.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-77466 (JP, A) JP-A-4-11730 (JP, A) JP-A-6-295901 (JP, A) JP-A 8- 111412 (JP, A) JP-A-8-181209 (JP, A) JP-A 8-195439 (JP, A) JP-A 8-204008 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/316 H01L 21/31

Claims (2)

(57) [Claims] A step of forming an insulating film on wiring on a semiconductor substrate, and passing SiH ₄ gas, H ₂ O ₂ and a microwave waveguide into a reaction chamber containing the semiconductor substrate after the formation of the insulating film. Introduced fluorine-based gas in a radical state,
In a vacuum of 665 Pa or less, the SiH ₄ gas, H ₂ O ₂ and fluorine-based gas are reacted with each other within a temperature range of −10 ° C. to + 10 ° C. to form a reflow SiO ₂ film having a reflow shape on the semiconductor substrate. And a step of forming a reflow film. 2. A chamber for accommodating a semiconductor substrate and depositing and forming a vapor deposition insulating film on the semiconductor substrate, a SiH ₄ gas supply pipe connected to the chamber, and an H ₂ gas connected to the chamber. An O ₂ supply pipe, a microwave waveguide connected to the chamber and supplied with a fluorine-based gas from one end side, and a microwave generator for supplying microwaves to the microwave waveguide are provided. Semiconductor manufacturing equipment.