WO1999035675A1 - Method for forming titanium film by cvd - Google Patents

Method for forming titanium film by cvd Download PDF

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Publication number
WO1999035675A1
WO1999035675A1 PCT/JP1999/000033 JP9900033W WO9935675A1 WO 1999035675 A1 WO1999035675 A1 WO 1999035675A1 JP 9900033 W JP9900033 W JP 9900033W WO 9935675 A1 WO9935675 A1 WO 9935675A1
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Prior art keywords
film
oxide film
silicon
gas
cvd
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PCT/JP1999/000033
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French (fr)
Japanese (ja)
Inventor
Taroh Ikeda
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Tokyo Electron Limited
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Publication of WO1999035675A1 publication Critical patent/WO1999035675A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04Coating on selected surface areas, e.g. using masks
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides

Definitions

  • the present invention relates to a method for forming a Ti film by CVD, which is used, for example, as a contact metal or an adhesion layer in a semiconductor device.
  • the circuit configuration has tended to have a multilayer Ifi ⁇ structure in response to recent demands for higher density and higher integration. For this reason, the lower semiconductor device and the upper wiring layer have been developed.
  • a 1 aluminum
  • W tungsten
  • an alloy mainly composed of these is generally used. If it comes into direct contact with the underlying Si (silicon) substrate or A1 wiring, an alloy of both metals may be formed at these boundaries due to the absorption effect of A1.
  • the alloy formed in this way has a large resistance value, and it is not preferable to form such an alloy because of the recent demands for high power and high speed operation 11 ⁇ .
  • WF 6 gas used for forming the buried layer tends to degrade the electrical characteristics in the S i substrate, also not preferable .
  • a barrier layer is formed on these inner walls, and the barrier layer is buried from above.
  • the formation of the embedded layer is performed.
  • a barrier layer having a two-layer structure of a Ti (titanium) film and a TiN (titanium nitride) film is generally used.
  • PVD physical vapor deposition
  • the Ti film and the TiN film constituting the barrier layer are being formed by chemical vapor deposition (CVD), which can be expected to form a higher quality film.
  • CVD chemical vapor deposition
  • a Ti film as a contact metal is formed on Si at the bottom of the hole.
  • the natural oxide film of silicon formed on the underlying Si in the previous process is usually removed by a cleaning treatment with 1% diluted hydrofluoric acid.
  • the electrical characteristics at the time of forming the contact may vary depending on the cleaning conditions and the time management until the next process after the cleaning. There is a problem that it gets stuck.
  • T i layer In the formation of T i layer, the use of T i C 1 4 as a film-forming gas, during film formation is T i S i 2 reacts S i and T i force underlying are formed, the The morphology of the interface with the underlying Si deteriorates in the course of the reaction, and when used in the process of forming a contact hole, junction leakage is likely to occur, and also adversely affects the case of a via hole.
  • the present invention has been made in view of the above circumstances, and is based on a CVD method capable of forming a Ti film that stabilizes contact resistance and improves morphology at the interface with the underlying Si.
  • An object of the present invention is to provide a method for forming a Ti film. Disclosure of the invention
  • a titanium film is formed on a surface of a silicon layer such as a silicon substrate or a polysilicon wiring by CVD using a film forming gas containing a TiC14 gas.
  • a film forming gas containing a TiC14 gas shall apply in the method, a step of allowing the formation of a silicon oxide film on the silicon layer surface, the film gas containing T i C 1 4 gas in a state where the oxide film is left to be supplied to the silicon layer surface titanium film
  • a method for forming a titanium film by CVD comprising the steps of:
  • the silicon layer has its surface exposed at the bottom of a contact hole formed in an insulating film on a silicon substrate, or has its surface exposed at the bottom of a via hole formed in an insulating film on a polysilicon wiring layer. ing.
  • the silicon oxide film is a film having a thickness of about 10 ⁇ or more.
  • the present inventors have, T i C 1 4 using the deposition gas containing the gas by CVD Upon forming a film of the T i layer, the contact resistance with stabilizing I ⁇ of T i layer and the underlying interface between S i As a result of repeated studies to improve the morphology, it was found that the film should be formed with a constant thickness of, for example, a natural oxide film formed on the underlying Si.
  • Ti films as contact metals are often formed by PVD, and if a natural oxide film remains on the underlying Si at that time, the contact resistance after Ti film formation increases. Therefore, the natural oxide film was removed. Therefore, the native oxide film was similarly removed when forming the Ti film by CVD.
  • washing step in the preceding step can be omitted, the number of steps is reduced, and the production efficiency can be made extremely high.
  • the present invention has been made against the stereotype that the silicon natural oxide film on Si is to be removed, and furthermore, it has an extremely large effect as described above.
  • the target value is high.
  • FIG. 1 is a cross-sectional view showing an example of a film forming apparatus for performing a method of forming a Ti film by CVD according to the present invention.
  • FIG. 2 is a sectional view showing an Si wafer to which the present invention is applied.
  • FIG. 3 is a schematic diagram for explaining Ti film formation in the present invention.
  • FIG. 4 is a schematic diagram for explaining conventional Ti film formation.
  • FIG. 1 is a cross-sectional view showing an example of a Ti film forming apparatus used for carrying out the present invention.
  • This film-forming apparatus has a substantially cylindrical chamber 11 which is airtightly arranged, and a susceptor 2 for horizontally supporting a Si wafer W as an object to be processed is provided at the center thereof. It is arranged in a state where it is supported by a cylindrical support member 3 that can move up and down. Further, the heater 15 is embedded in the susceptor 1 for 4 hours, and the heater 15 is heated by a power source (not shown) to heat the Si wafer W as a processing target to a predetermined temperature.
  • a power source not shown
  • a shower head 10 is provided at an upper end portion of the chamber 11 so as to face the semiconductor wafer W supported by the susceptor 2, and a plurality of gas discharge holes are provided on a lower surface facing the wafer W. 10 & mosquitoes are formed. Inside the shower head 10, a space 11 is formed, and a dispersion plate 12 having a large number of holes formed therein is provided horizontally. A gas inlet 13 for introducing a gas into the shower head 10 is formed at an upper portion of the shower head 10, and a gas supply pipe 15 is connected to the gas inlet 13.
  • An H 2 (hydrogen) gas source 16, an Ar (argon) gas source 17, and a TiC 14 (tetrashidani titanium) gas source 18 are connected to the gas supply pipe 15. Each gas is supplied from these gas sources into the chamber 1 through the gas supply pipe 15 and the shower head 10, and a Ti film is formed on the Si wafer W.
  • the piping connected to each gas source is provided with a valve 19 and a mass opening controller 20 times.
  • a high-frequency power supply 23 is connected to the shower head 10 via a matching circuit 22 so that high-frequency power can be applied to the shower head 10 from the high-frequency power supply 23. With this high frequency power, a plasma force of the film forming gas is formed in the chamber 11.
  • the shower head 10 and the chamber 1 are electrically insulated by an insulating member 14, and the chamber 11 is grounded.
  • An exhaust port 8 is provided on the bottom wall of the chamber 1. Is connected to an exhaust system 9 for exhausting the inside of the chamber 11. Further, a loading / unloading port 24 for the wafer W is provided below the side wall of the chamber 1, and the loading / unloading port 24 can be opened and closed by a gate valve 25. The loading and unloading of wafer W is performed with susceptor 2 lowered.
  • the gate valve 25 is opened, the Si wafer W is loaded into the chamber 1, and is placed on the susceptor 2. and evacuated to a high vacuum state by S i wafer W while heating the vacuum pump of the exhaust system 9 by one coater 4, subsequently, T i C 1 4 gas, H 2 gas, is introduced to a r gas, high frequency Plasma is generated by applying high frequency power from the power supply 23.
  • the target for forming the T i layer as shown in FIG. 2 A, S i board 4 1 S i 0 2 film 4 2 as an insulating film on are formed, there contactor Tohoru 4 3 forms As shown in FIG. 2B, and as shown in FIG. 2B, the Si 0 2 film 4 5 is formed as an interlayer insulating film on the polysilicon film 44 directly or via an insulating film. A via hole 46 is formed there.
  • the Ti film is formed as described above without previously removing the natural oxide film formed on the base Si.
  • the TiCl + gas, H 2 gas and Ar gas are introduced, and a high frequency power is applied from a high frequency power source 23 to generate plasma to form a Ti film.
  • the interdiffusion between T i and S i is suppressed by the presence of a natural oxide film 5 0, and the etching of S i by T i C 1 4 gas is suppressed. Therefore, as shown in FIG. 3B, the morphology of the interface between the Ti Si 2 film 51 and the underlying Si substrate 41 caused by the diffusion of Ti and Si is improved.
  • the conventional oxide film is formed with the natural oxide film remaining without passing through the step of removing the natural oxide film.
  • the morphology does not deteriorate as in the case of removing the natural oxide film, and it is difficult to cause a junction leak or the like.
  • there is a great advantage in the process that the number of steps is reduced because the washing step is not required, and it is not necessary to consider variations in electrical characteristics due to the washing step.
  • natural oxide film of silicon silicon
  • Si 0 2 film is the surface of the silicon is formed instantaneously when exposed to the atmosphere.
  • the thickness of the silicon oxide film formed instantaneously is about 10 angstroms. Oxide thickness increases gradually with continued exposure to silicon-based surface air and typically saturates at thicknesses of 30-40 Angstroms.
  • the thickness of the native oxide film is preferably in the range of about 10 to 40 ⁇ . More preferably, it is in the range of about 20 to 30 angstroms.
  • the amount of T i C 1 4 gas, H 2 gas, A r gas is deposition gas, respectively, 3 ⁇ 30 SCCM, 0. 5 ⁇ 3 SLM, 0. 5 ⁇ 3 in the range of SLM Is preferred.
  • input power to high-frequency power supply 100 to 1000 W
  • pressure in chamber 0.5 ⁇ 3. It is preferable to set within the range of OTorr.
  • chamber internal pressure 1.5 Torr
  • input power to high frequency power supply 13.56 MHz: 30 OW
  • H2 gas 3 ⁇ 4ifi 0.5 SLM
  • Ar gas flow rate 1.0 SLM
  • T i C 1 4 gas flow rate 7 SC CM
  • the same Ti film was formed on the wafer from which the natural oxide film was removed in the previous step.
  • T i C 1 4 gas as the film forming gas, H 2 gas, was used Ar gas, may contain other gases.
  • the manufacturing conditions are not limited to the above conditions, and may be appropriately set so that a desired Ti film is formed.
  • the silicon oxide film on the silicon surface is a natural oxide film
  • the natural oxide film is formed only by exposing the silicon surface to the atmosphere, it is not necessary to provide a new process for forming the oxide film.
  • the silicon oxide film remaining on the silicon surface is not limited to the natural oxide film.
  • a silicon oxide film with a thickness of about 10 to 40 angstroms is formed in the same chamber or another chamber in a reduced-pressure oxidizing atmosphere. good.
  • the oxide film may be formed with a thickness of about 10 to 40 angstroms, or may be left as it is, or once formed to be thicker than 40 angstroms, and then to a thickness of 10 to 40 angstroms. Etching may be done until it is.
  • the present invention when forming a Ti film by CVD in a hole of an insulating film formed on the Si substrate or on the Si film thereon, the underlying natural oxide film is Since the film is formed without being removed, the contact resistance is stabilized, and the morphology of the interface with the underlying Si can be improved.

Abstract

A CVD method by which a titanium film having stable contact resistance and a satisfactory homology of the interface between the film and a silicon substrate can be formed. The method comprises feeding a film-forming gas containing TiCl4 gas to a contact hole (46) at the bottom of which a silicon substrate (41) having an autoxidized silicon film (50) is present to form a titanium film on the silicon substrate (41) by CVD to thereby form a TiSi2 layer (51) on the silicon substrate (41).

Description

明 細 書  Specification
C V Dによるチタン膜の成膜方法 技 術 分 野 Method of forming titanium film by CVD
本発明は、 半導体装置において例えばコンタク トメタルまたはアドヒージョン 層として用いられる、 C V Dによる T i膜の成膜方法に関する。  The present invention relates to a method for forming a Ti film by CVD, which is used, for example, as a contact metal or an adhesion layer in a semiconductor device.
背 景 技 術  Background technology
半導体デバイスの製造においては、 最近の高密度化および高集積化の要請に対 応して、 回路構成を多層 Ifi^構造にする傾向にあり、 このため、 下層の半導体デ バイスと上層の配線層との接続部であるコンタクトホールや、 上下の IS^層同士 の接続部であるビアホールなどの層間の電気的接続のための埋め込み技術力く重要 になっている。  In the manufacture of semiconductor devices, the circuit configuration has tended to have a multilayer Ifi ^ structure in response to recent demands for higher density and higher integration. For this reason, the lower semiconductor device and the upper wiring layer have been developed. The embedding technology for electrical connection between layers such as contact holes, which are the connection parts between them, and via holes, which are the connection parts between the upper and lower IS ^ layers, has become important.
このようなコンタクトホールやビアホールの埋め込みには、 一般的に A 1 (ァ ルミ二ゥム) や W (タングステン) 、 あるいはこれらを主体とする合金が用いら れるが、 このような金属や合金が下層の S i (シリコン) 基板や A 1配線と直接 接触すると、 これらの境界部分において A 1の吸い上げ効果等に起因して両金属 の合金が形成されるおそれがある。 このようにして形成される合金は抵抗値が大 きく、 このような合金が形成されることは近時デノ <イスに要求されている f«力 化および高速動作の 11^、から好ましくない。  In order to fill such contact holes and via holes, A 1 (aluminum), W (tungsten), or an alloy mainly composed of these is generally used. If it comes into direct contact with the underlying Si (silicon) substrate or A1 wiring, an alloy of both metals may be formed at these boundaries due to the absorption effect of A1. The alloy formed in this way has a large resistance value, and it is not preferable to form such an alloy because of the recent demands for high power and high speed operation 11 ^ .
また、 Wまたは W合金をコンタクトホールの埋め込み層として用いる場合には、 埋め込み層の形成に用いる W F 6ガスが S i基板に して電気的特性等を劣化 させる傾向となり、 やはり好ましくない結果をもたらす。 In the case of using a W or W alloy as a buried layer of the contact hole will result WF 6 gas used for forming the buried layer tends to degrade the electrical characteristics in the S i substrate, also not preferable .
そこで、 これらの不都合を防止するために、 コンタク トホールやビアホールに 埋め込み層を形成する前に、 これらの内壁にバリア層を形成し、 その上から埋め 込み層を形成することが行われている。 この場合のバリア層としては、 T i (チ タン) 膜および T i N (窒化チタン) 膜の 2層構造のものを用いるのが一般的で ある。 Therefore, in order to prevent these inconveniences, before forming a buried layer in the contact hole or via hole, a barrier layer is formed on these inner walls, and the barrier layer is buried from above. The formation of the embedded layer is performed. In this case, a barrier layer having a two-layer structure of a Ti (titanium) film and a TiN (titanium nitride) film is generally used.
従来、 このようなバリア層は、 物理的蒸着 (P V D) を用いて成膜されていた が、 最近のようにデバイスの微細化および高集積化力特に要求され、 デザインル —ルが特に厳しくなつて、 それにともなって線幅やホールの開口径が一層小さく なり、 しかも高アスペク ト比化されるにつれ、 P V D膜では電気抵抗力増加し、 要求に対応することが困難となってきた。  Traditionally, such barrier layers have been formed using physical vapor deposition (PVD), but recently the demand for device miniaturization and high integration has become particularly demanding, and the design rules have become particularly severe. Accordingly, as the line width and hole opening diameter become smaller and the aspect ratio becomes higher, the electrical resistance of PVD films increases, making it difficult to meet the demands.
そこで、 バリア層を構成する T i膜および T i N膜を、 より良質の膜を形成す ることが期待できる化学的蒸着 (C V D) で成膜することが行われている。 この 場合に、 まずコンタクトメタルである T i膜をホールの底の S i上に成膜する。 この場合には、 通常、 コンタク ト抵抗を下げるために、 前工程において下地の S i上に形成されたシリコンの自然酸化膜を 1 %の希フッ酸による洗浄処理によ つて除去している。  Therefore, the Ti film and the TiN film constituting the barrier layer are being formed by chemical vapor deposition (CVD), which can be expected to form a higher quality film. In this case, first, a Ti film as a contact metal is formed on Si at the bottom of the hole. In this case, in order to reduce the contact resistance, the natural oxide film of silicon formed on the underlying Si in the previous process is usually removed by a cleaning treatment with 1% diluted hydrofluoric acid.
しかしな力《ら、 このように自然酸化膜を除去するための洗浄処理を行うと、 洗 浄条件および洗浄後次の工程までの時間管理の如何により、 コンタクトの形成時 の電気特性力く異なつてしまうという問題がある。  However, if the cleaning process for removing the natural oxide film is performed as described above, the electrical characteristics at the time of forming the contact may vary depending on the cleaning conditions and the time management until the next process after the cleaning. There is a problem that it gets stuck.
また、 T i膜の成膜においては、 成膜ガスとして T i C 1 4を使用すると、 成 膜時に下地の S iと T i力反応して T i S i 2が形成されるが、 その反応の過程 で下地の S iとの界面のモホロジーが悪化し、 コンタクトホール形成のプロセス に使用した場合には、 ジャンクションリークを起こしやすくなるし、 ビアホール の場合にも悪影響を及ぼす。 In the formation of T i layer, the use of T i C 1 4 as a film-forming gas, during film formation is T i S i 2 reacts S i and T i force underlying are formed, the The morphology of the interface with the underlying Si deteriorates in the course of the reaction, and when used in the process of forming a contact hole, junction leakage is likely to occur, and also adversely affects the case of a via hole.
本発明は、 かかる事情に鑑みてなされたものであって、 コンタク ト抵抗力安定 し、 下地の S i との界面のモホロジ一が良好となる T i膜を成膜することができ る C V Dによる T i膜の成膜方法を提供することを目的とする。 発 明 の 開 示 The present invention has been made in view of the above circumstances, and is based on a CVD method capable of forming a Ti film that stabilizes contact resistance and improves morphology at the interface with the underlying Si. An object of the present invention is to provide a method for forming a Ti film. Disclosure of the invention
上記課題を解決するために、 本発明によれば、 シリコン基板またはポリシリコ ン配線のようなシリコン層の表面に T i C 1 4ガスを含む成膜ガスを用いて C V Dによりチタン膜を成膜する方法であつて、 前記シリコン層表面にシリコン酸化 膜の形成を許す工程と、 前記酸化膜を残存させた状態で T i C 1 4ガスを含む成 膜ガスをシリコン層表面に供給してチタン膜を成膜する工程と、 を含む C V Dに よるチタン膜の成膜方法力く提供される。 According to the present invention, a titanium film is formed on a surface of a silicon layer such as a silicon substrate or a polysilicon wiring by CVD using a film forming gas containing a TiC14 gas. shall apply in the method, a step of allowing the formation of a silicon oxide film on the silicon layer surface, the film gas containing T i C 1 4 gas in a state where the oxide film is left to be supplied to the silicon layer surface titanium film And a method for forming a titanium film by CVD comprising the steps of:
典型例においては、 シリコン層はシリコン基板上の絶縁膜に形成したコンタク トホールの底にその表面を露出するか、 またはポリシリコン配線層上の絶縁膜に 形成したビアホールの底にその表面を露出している。  In a typical example, the silicon layer has its surface exposed at the bottom of a contact hole formed in an insulating film on a silicon substrate, or has its surface exposed at the bottom of a via hole formed in an insulating film on a polysilicon wiring layer. ing.
成膜工程で、 成膜ガスのプラズマを励磁させること力 <望ましい。 また、 前記シ リコン自然酸ィ匕膜は、 約 1 0オングストローム以上の厚さの膜である。  Force to excite plasma of film forming gas in film forming process <desirable. Further, the silicon oxide film is a film having a thickness of about 10 Å or more.
本発明者は、 T i C 1 4ガスを含む成膜ガスを用いて C V Dにより T i膜を成 膜するにあたり、 コンタクト抵抗を安定ィ匕させるとともに T i膜と下地の S iと の界面のモホロジーを良好にすべく検討を重ねた結果、 下地の S iの上に形成さ れているたとえば自然酸化膜を一定の厚みで残存させた状態で成膜すればよいこ とを見出した。 The present inventors have, T i C 1 4 using the deposition gas containing the gas by CVD Upon forming a film of the T i layer, the contact resistance with stabilizing I匕of T i layer and the underlying interface between S i As a result of repeated studies to improve the morphology, it was found that the film should be formed with a constant thickness of, for example, a natural oxide film formed on the underlying Si.
従来、 コンタク トメタルとしての T i膜は P V Dで成膜されることが多く、 そ の際に下地の S iに自然酸化膜が残存していると T i成膜後のコンタク ト抵抗が 高くなるため、 自然酸化膜を除去していた。 そこで C V Dによる T i膜の成膜に おいても同様に自然酸化膜を除去していた。  Conventionally, Ti films as contact metals are often formed by PVD, and if a natural oxide film remains on the underlying Si at that time, the contact resistance after Ti film formation increases. Therefore, the natural oxide film was removed. Therefore, the native oxide film was similarly removed when forming the Ti film by CVD.
一方、 T i膜を C V Dで成膜する場合に、 T i膜と下地の S iとの界面のモホ ロジ一力く悪ィヒする原因について調査した結果、 T i と S i との界面ではこれらの 相互拡散が大きくそれにともなって界面の凹凸が大きくなること、 および T i C 1 4ガスにより下地の S iが等方エッチングされることが原因であること を見出した。 その時の反応式は次のように考えられる。 On the other hand, when the Ti film was formed by CVD, the morphology of the interface between the Ti film and the underlying Si was found to be as bad as possible. that these interdiffusion increases with it the unevenness of the surface increases, and T i C 1 4 by the gas of the underlying S i is due to be isotropic etching Was found. The reaction formula at that time is considered as follows.
T i C l4 + H2+3 S i- T i S i 2+S i C l 2+2HC l そして、 これらは下地の S iが露出していることにより生じるのであり、 シリ コンの自然酸化膜を残存させることによりこのような不都合が解消されることを 知見した。 つまり、 一定の厚みの酸化膜が残存していることにより、 T 1と S iとの相互拡散を抑制し、 また T i C 14ガスのエッチングのバリアとして作 用するのである。 この場合の反応式は次のように考えられる。 T i Cl 4 + H2 + 3 S i- T i S i 2 + S i C l 2 + 2H l These are caused by the underlying Si being exposed, and the natural oxidation of silicon It has been found that such inconvenience is eliminated by leaving the film. That is, by oxide film of constant thickness is left, to suppress mutual diffusion between T 1 and S i, also it is to a work as an etch barrier of T i C 1 4 gas. The reaction formula in this case is considered as follows.
T i C 14 + 4H2+ S i 02+S i→T i S i 2+2H20 + 4HC 1 また、 CVD成膜の場合には、 自然酸化膜が残存していても、 プロセスガスに よる還元反応によって酸化膜が S iと T iとの間の界面から消失するため、 T i 膜のコンタクト抵抗が高いという問題も生じず、 酸化膜を除去する必要がないた め、 コンタク ト抵抗の安定性も高い。 T i C 14 + 4H 2 + S i 0 2 + S i → T i S i 2 + 2H 2 0 + 4HC 1 In the case of CVD deposition, be left natural oxide film, the process gas The oxide film disappears from the interface between Si and Ti due to the reduction reaction, so that the problem that the contact resistance of the Ti film is high does not occur, and there is no need to remove the oxide film. Resistance stability is also high.
さらに、 前工程での洗净工程を省略することができるため、 工程数が減少する ことにより製造効率を極めて高いものとすることができる。  Furthermore, since the washing step in the preceding step can be omitted, the number of steps is reduced, and the production efficiency can be made extremely high.
本発明は、 S i上のシリコン自然酸化膜は除去するものであるという固定観念 に抗してなされたものであり、 しかもこれにより上述のように極めて大きな効果 を奏するものであって、 その工業的価値は高い。  The present invention has been made against the stereotype that the silicon natural oxide film on Si is to be removed, and furthermore, it has an extremely large effect as described above. The target value is high.
図面の簡単な説明  BRIEF DESCRIPTION OF THE FIGURES
図 1は本発明に係る、 CVDによる T i膜の成膜方法を実施するための成膜装 置の一例を示す断面図である。  FIG. 1 is a cross-sectional view showing an example of a film forming apparatus for performing a method of forming a Ti film by CVD according to the present invention.
図 2は本発明が適用される S iウェハを示す断面図である。  FIG. 2 is a sectional view showing an Si wafer to which the present invention is applied.
図 3は本発明における T i成膜を説明するための模式図である。  FIG. 3 is a schematic diagram for explaining Ti film formation in the present invention.
図 4は従来の T i成膜を説明するための模式図である。  FIG. 4 is a schematic diagram for explaining conventional Ti film formation.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
以下、 添付図面を参照して、 本発明の実施の形態について詳細に説明する。 図 1は、 本発明の実施に用いられる T i成膜装置の一例を示す断面図である。 この成膜装置は、 気密に構成された略円筒状のチャンバ一 1を有しており、 その 中には被処理体である S iウェハ Wを水平に支持するためのサセプター 2がその 中央を昇降可能な円筒状の支持部材 3により支持された状態で配置されている。 また、 サセプ夕一 2にはヒ一夕一 4力埋め込まれており、 このヒータ一 5は図示 しない電源から給電されることにより被処理体である S iウェハ Wを所定の温度 に加熱する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an example of a Ti film forming apparatus used for carrying out the present invention. This film-forming apparatus has a substantially cylindrical chamber 11 which is airtightly arranged, and a susceptor 2 for horizontally supporting a Si wafer W as an object to be processed is provided at the center thereof. It is arranged in a state where it is supported by a cylindrical support member 3 that can move up and down. Further, the heater 15 is embedded in the susceptor 1 for 4 hours, and the heater 15 is heated by a power source (not shown) to heat the Si wafer W as a processing target to a predetermined temperature.
チャンバ一 1の上端部分には、 シャワーへッ ド 1 0がサセプター 2に支持され た半導体ウェハ Wと対向するように設けられており、 そのウェハ Wと対向する下 面には多数のガス吐出孔 1 0 &カ形成されている。 シャワーへッ ド 1 0の内部に は空間 1 1力形成されており、 その中に多数の孔が形成された分散板 1 2が水平 に設けられている。 シャワーヘッド 1 0の上部には、 その中にガスを導入するガ ス導入口 1 3が形成されており、 このガス導入口 1 3にはガス供給管 1 5が接続 されている。  A shower head 10 is provided at an upper end portion of the chamber 11 so as to face the semiconductor wafer W supported by the susceptor 2, and a plurality of gas discharge holes are provided on a lower surface facing the wafer W. 10 & mosquitoes are formed. Inside the shower head 10, a space 11 is formed, and a dispersion plate 12 having a large number of holes formed therein is provided horizontally. A gas inlet 13 for introducing a gas into the shower head 10 is formed at an upper portion of the shower head 10, and a gas supply pipe 15 is connected to the gas inlet 13.
ガス供給管 1 5には、 H2 (水素) ガス源 1 6, A r (アルゴン) ガス源 1 7, T i C 1 4 (四塩ィ匕チタン) ガス源 1 8が接続されており、 これらガス源から各 ガスがガス供給管 1 5およびシャワーへッ ド 1 0を通ってチヤンバー 1内に供給 され、 S iウェハ Wに T i膜が成膜される。 なお、 各ガス源に接続される配管に は、 いずれもバルブ 1 9およびマスフ口一コントローラー 2 0力く設けられている。 シャワーへッ ド 1 0にはマッチング回路 2 2を介して高周波電源 2 3が接続さ れており、 この高周波電源 2 3からシャワーヘッ ド 1 0に高周波電力が印加され 得るようになつている。 この高周波電力により、 チャンバ一 1内に成膜ガスのプ ラズマ力形成される。 なお、 シャワーヘッ ド 1 0とチヤンバー 1との間は、 絶縁 部材 1 4により電気的に絶縁されており、 チャンバ一 1は接地されている。 An H 2 (hydrogen) gas source 16, an Ar (argon) gas source 17, and a TiC 14 (tetrashidani titanium) gas source 18 are connected to the gas supply pipe 15. Each gas is supplied from these gas sources into the chamber 1 through the gas supply pipe 15 and the shower head 10, and a Ti film is formed on the Si wafer W. In addition, the piping connected to each gas source is provided with a valve 19 and a mass opening controller 20 times. A high-frequency power supply 23 is connected to the shower head 10 via a matching circuit 22 so that high-frequency power can be applied to the shower head 10 from the high-frequency power supply 23. With this high frequency power, a plasma force of the film forming gas is formed in the chamber 11. The shower head 10 and the chamber 1 are electrically insulated by an insulating member 14, and the chamber 11 is grounded.
チャンバ一 1の底壁には、 排気ポート 8が設けられており、 この排気ポート 8 にはチャンバ一 1内を排気するための排気系 9力接続されている。 また、 チャン バ一1の側壁下部にはウェハ Wの搬入出口 2 4が設けられており、 この搬入出口 2 4はゲートバルブ 2 5により開閉可能となっている。 ウェハ Wの搬入出はサセ プ夕 2を下降させた状態で行われる。 An exhaust port 8 is provided on the bottom wall of the chamber 1. Is connected to an exhaust system 9 for exhausting the inside of the chamber 11. Further, a loading / unloading port 24 for the wafer W is provided below the side wall of the chamber 1, and the loading / unloading port 24 can be opened and closed by a gate valve 25. The loading and unloading of wafer W is performed with susceptor 2 lowered.
このような成膜装置により、 T i膜を成膜するためには、 ゲートバルブ 2 5を 開にしてチヤンバー 1内に S iウェハ Wを装入してサセプ夕 2上に載置し、 ヒ一 ター 4により S iウェハ Wを加熱しながら排気系 9の真空ポンプにより真空引き して高真空状態にし、 引き続き、 T i C 1 4ガス、 H2ガス、 A rガスを導入する とともに、 高周波電源 2 3から高周波電力を印加することによりプラズマを生成 させる。 In order to form a Ti film by such a film forming apparatus, the gate valve 25 is opened, the Si wafer W is loaded into the chamber 1, and is placed on the susceptor 2. and evacuated to a high vacuum state by S i wafer W while heating the vacuum pump of the exhaust system 9 by one coater 4, subsequently, T i C 1 4 gas, H 2 gas, is introduced to a r gas, high frequency Plasma is generated by applying high frequency power from the power supply 23.
ここで、 T i膜を形成する対象としては、 図 2 Aに示すように、 S i基板 4 1 上に絶縁膜として S i 02膜 4 2が形成され、 そこにコンタク トホール 4 3が形 成されたもの、 および図 2 Bに示すように、 S i基板 4 1に直接もしくは絶縁膜 を介して形成されたポリシリコン膜 4 4の上に層間絶縁膜として S i 02膜 4 5 力形成され、 そこにビアホール 4 6力く形成されたものが例示される。 Here, the target for forming the T i layer, as shown in FIG. 2 A, S i board 4 1 S i 0 2 film 4 2 as an insulating film on are formed, there contactor Tohoru 4 3 forms As shown in FIG. 2B, and as shown in FIG. 2B, the Si 0 2 film 4 5 is formed as an interlayer insulating film on the polysilicon film 44 directly or via an insulating film. A via hole 46 is formed there.
本実施の形態においては、 下地 S i上に形成された自然酸化膜を予め除去する ことなく上述のように T i膜を成膜する。 この場合には、 具体的には、 図 3 Aの のようにホール 4 3の底の S i基板 4 1上にシリコン自然酸化膜 5 0が残存した 状態で、 T i C l ^ガス、 H 2ガス、 A rガスを導入するとともに、 高周波電源 2 3から高周波電力を印加することによりプラズマを生成させて T i膜を形成す る。 この場合には、 自然酸化膜 5 0の存在により T iと S iとの相互拡散が抑制 され、 かつ T i C 1 4ガスによる S iのエッチングも抑制される。 したがって図 3 Bに示すように、 T iと S iとの拡散によって生じた T i S i 2膜 5 1と下地 の S i基板 4 1との界面のモホロジ一が良好になる。 In the present embodiment, the Ti film is formed as described above without previously removing the natural oxide film formed on the base Si. In this case, specifically, as shown in FIG. 3A, with the silicon natural oxide film 50 remaining on the Si substrate 41 at the bottom of the hole 43, the TiCl + gas, H 2 gas and Ar gas are introduced, and a high frequency power is applied from a high frequency power source 23 to generate plasma to form a Ti film. In this case, the interdiffusion between T i and S i is suppressed by the presence of a natural oxide film 5 0, and the etching of S i by T i C 1 4 gas is suppressed. Therefore, as shown in FIG. 3B, the morphology of the interface between the Ti Si 2 film 51 and the underlying Si substrate 41 caused by the diffusion of Ti and Si is improved.
それに対して、 従来のように自然酸化膜を除去すると、 図 4 Aに示すように、 T i C 14が下地の S i基板 41を直接エッチングするとともに、 S iおよび T iの間に介在する層がないため、 これらの相互拡散が激しくなり、 結果として、 図 4 Bに示すように、 T i S i 2膜 51と下地の S i基板 41との界面のモホロ ジ一が悪くなる。 この場合に、 T i C 14のエッチングは等方的であるから、 S i基板が深さ方向のみならず横方向にもエッチングされ、 ジャンクションリー クが生じやすくなる。 On the other hand, if the native oxide film is removed as before, as shown in Fig. 4A, With T i C 1 4 is directly etched S i substrate 41 underlying, since there is no intervening layers between S i and T i, these interdiffusion intensified, as a result, as shown in FIG. 4 B Furthermore, the morphology at the interface between the TiSi 2 film 51 and the underlying Si substrate 41 deteriorates. In this case, since the etching of T i C 1 4 is isotropic, also etched in the transverse direction as well as S i substrate depth direction only, the junction leakage is likely to occur.
このように、 S i上に T i膜を CVDで形成する場合に、 自然酸化膜を除去す る工程を経ることなく、 自然酸化膜を残存させた状態で成膜することにより、 従 来の自然酸化膜を除去する場合のようなモホロジ一の悪化が生じず、 ジャンクシ ヨンリーク等が生じにく くなる。 また、 洗浄工程が不要になることから工程数の 減少というプロセス上大きなメリツ 卜があり、 また洗浄工程を経ることによる電 気特性のばらつきも考慮する必要がなくなる。 なお、 シリコンの自然酸化膜  As described above, when a Ti film is formed on Si by CVD, the conventional oxide film is formed with the natural oxide film remaining without passing through the step of removing the natural oxide film. The morphology does not deteriorate as in the case of removing the natural oxide film, and it is difficult to cause a junction leak or the like. In addition, there is a great advantage in the process that the number of steps is reduced because the washing step is not required, and it is not necessary to consider variations in electrical characteristics due to the washing step. In addition, natural oxide film of silicon
(S i 02膜) はシリコンの表面が大気に露呈されると瞬時に形成される。 瞬時 に形成されるシリコン酸化膜の厚さは約 10オングストロームである。 シリコン ベースの面力大気に露呈され続けると酸化膜厚は漸次増大し、 通常、 30〜40 オングストロームの膜厚で飽和する。 (S i 0 2 film) is the surface of the silicon is formed instantaneously when exposed to the atmosphere. The thickness of the silicon oxide film formed instantaneously is about 10 angstroms. Oxide thickness increases gradually with continued exposure to silicon-based surface air and typically saturates at thicknesses of 30-40 Angstroms.
なお、 〇¥0の場合は? 0の場合と異なり、 自然酸化膜を除去しなくても最 終的に酸素が界面に残存することはなく、 化学反応により除去される。  If 〇 ¥ 0? Unlike the case of 0, even if the native oxide film is not removed, oxygen does not ultimately remain at the interface but is removed by a chemical reaction.
次に、 本発明における好ましい条件について説明する。 良好な界面モホロジー を維持しつつ良好な電気的コンタク トを得る観点からは、 自然酸化膜の厚さは 10-40オングストローム程度の範囲力、'好ましい。 より好ましくは 20〜30 オングストローム程度の範囲である。 また、 成膜ガスである T i C 14ガス、 H2 ガス、 A rガスの量は、 それぞれ、 3〜30 SCCM, 0. 5〜3 SLM, 0. 5〜3 SLMの範囲とすることが好ましい。 さらに、 基板温度: 400〜700 °C、 高周波電源への投入電力: 100〜 1000 W、 チヤンバー内圧力: 0. 5 〜3. OTo r rの範囲に設定することが好ましい。 Next, preferable conditions in the present invention will be described. From the viewpoint of obtaining good electrical contact while maintaining good interface morphology, the thickness of the native oxide film is preferably in the range of about 10 to 40 Å. More preferably, it is in the range of about 20 to 30 angstroms. The amount of T i C 1 4 gas, H 2 gas, A r gas is deposition gas, respectively, 3~30 SCCM, 0. 5~3 SLM, 0. 5~3 in the range of SLM Is preferred. Substrate temperature: 400 to 700 ° C, input power to high-frequency power supply: 100 to 1000 W, pressure in chamber: 0.5 ~ 3. It is preferable to set within the range of OTorr.
一例として、 チャンバ一内圧力: 1. 5To r r、 高周波電源 (13. 56 MH z) への投入電力: 30 OW, H2ガス ¾ifi: 0. 5SLM, A rガス流量 : 1. 0 S LM, T i C 14ガス流量: 7 S C CM、 基板温度 600°C条件で、 自 然酸化膜を除去することなく、 S i 02膜に形成されたコンタク トホールに T i 膜の成膜を行った。 比較のため、 前工程で自然酸化膜を除去したウェハについて も同様の T i膜の成膜を行った。 As an example, chamber internal pressure: 1.5 Torr, input power to high frequency power supply (13.56 MHz): 30 OW, H2 gas ¾ifi: 0.5 SLM, Ar gas flow rate: 1.0 SLM, T i C 1 4 gas flow rate: 7 SC CM, at a substrate temperature of 600 ° C conditions, without removing the natural oxide film, a film was formed of T i membrane contactor Tohoru formed S i 0 2 film . For comparison, the same Ti film was formed on the wafer from which the natural oxide film was removed in the previous step.
その結果、 自然酸化膜を除去した直後に T i成膜を行なった場合には、 上述の 図 4に示すように、 ホール部分の T i S i 2と下地 S i基板との界面モホロジー が悪く、 またその界面が、 S iが T i C 14によりエッチングされることにより、 横方向に拡がっていることが確認された。 一方、 約 10オングストローム以上の 厚みの自然酸化膜を残存させた本発明例では、 上述の図 3に示すように、 Ti S i 2層は薄く均一であり、 良好な界面モホロジ一力得られること力確認された。 なお、 本発明は、 上記 の形態に限定されることなく種々変形可能である。 例えば、 上記実施の形態では、 成膜ガスとして T i C 14ガス、 H2ガス、 Arガ スを用いたが、 他のガスが含まれていてもよい。 また、 製造条件についても上記 条件に限るものではなく、 所望の T i膜が形成されるよう適宜設定すればよい。 なお、 以上の説明ではシリコン表面のシリコン酸化膜が自然酸化膜である例を 用いて説明した。 自然酸化膜はシリコン表面を大気に露呈するだけで形成される ため、 酸化膜形成のために改めて工程を設ける必要が無い。 しかし、 シリコン表 面に残存させるシリコン酸化膜は自然酸化膜にかぎられない。 たとえば、 エッチ ングなどの前工程でシリコン表面が露出したあと、 同一チヤンバーあるいは別チ ャンバ一内で減圧酸化雰囲気中で約 10〜40オングストロームの厚さのシリコ ン酸ィヒ膜を形成しても良い。 As a result, when subjected to T i deposition immediately after removing the native oxide film, as shown in FIG. 4 described above, poor interfacial morphology of the T i S i 2 and the base S i board hole portion and the interface is, by S i is etched by T i C 1 4, it was confirmed that the spread in the lateral direction. On the other hand, in the example of the present invention in which a native oxide film having a thickness of about 10 angstroms or more was left, as shown in FIG. Power was confirmed. The present invention can be variously modified without being limited to the above embodiment. For example, in the above embodiment, T i C 1 4 gas as the film forming gas, H 2 gas, was used Ar gas, may contain other gases. Further, the manufacturing conditions are not limited to the above conditions, and may be appropriately set so that a desired Ti film is formed. In the above description, an example in which the silicon oxide film on the silicon surface is a natural oxide film has been described. Since the natural oxide film is formed only by exposing the silicon surface to the atmosphere, it is not necessary to provide a new process for forming the oxide film. However, the silicon oxide film remaining on the silicon surface is not limited to the natural oxide film. For example, after the silicon surface is exposed in a previous process such as etching, a silicon oxide film with a thickness of about 10 to 40 angstroms is formed in the same chamber or another chamber in a reduced-pressure oxidizing atmosphere. good.
すなわち、 CVD— T i膜の成膜時に、 シリコン表面に一定範囲の厚みがシリ コン酸化膜が残存していることが重要であって、 そのシリコン酸化膜がどのよう に形成されたかは問わない。 また酸化膜は、 約 1 0 ~ 4 0オングストロームの厚 さで形成したものをそのまま残存させても良いし、 一度 4 0オングストロームよ りも厚く形成してから、 1 0 ~ 4 0オングストロームの厚みになるまでエツチン グしても良い。 That is, a certain range of thickness is deposited on the silicon surface during CVD-Ti film formation. It is important that the silicon oxide film remains, regardless of how the silicon oxide film was formed. The oxide film may be formed with a thickness of about 10 to 40 angstroms, or may be left as it is, or once formed to be thicker than 40 angstroms, and then to a thickness of 10 to 40 angstroms. Etching may be done until it is.
以上説明したように、 本発明によれば、 S i基板上またはその上の S i膜上に 形成された絶縁膜のホールに C V Dによって T i膜を成膜するにあたり、 下地の 自然酸化膜を除去せずに成膜するので、 コンタク ト抵抗が安定し、 下地の S iと の界面のモホロジ一を良好にすることができる。  As described above, according to the present invention, when forming a Ti film by CVD in a hole of an insulating film formed on the Si substrate or on the Si film thereon, the underlying natural oxide film is Since the film is formed without being removed, the contact resistance is stabilized, and the morphology of the interface with the underlying Si can be improved.

Claims

請 求 の 範 囲 The scope of the claims
1. シリコン層上に T i Cしガスを含む成膜ガスを用いて CVDによりチ 夕ン膜を成膜する方法であつて、 1. A method of depositing a titanium film on a silicon layer by CVD using a deposition gas containing a TiC gas,
前記シリコン層表面上にシリコン自然酸化膜の形成を許す工程と、  Allowing formation of a silicon native oxide film on the silicon layer surface;
前記自然酸化膜を残存させた状態で T i C 14ガスを含む成膜ガスを前記シリ コン層上に供給してチタン膜を成膜する工程と、 A step of forming the titanium film by supplying a deposition gas containing T i C 1 4 gas into the silicon layer in a state of being left to the natural oxide film,
を含む CVDによるチタン膜の成膜方法。  A method for forming a titanium film by CVD.
2. 前記シリコン自然酸化膜力 <約 10オングストローム以上の厚さの膜であ る請求項 1記載の C V Dによるチタン膜の成膜方法。  2. The method for forming a titanium film by CVD according to claim 1, wherein the natural silicon oxide film has a thickness of not less than about 10 angstroms.
3. 前記シリコン自然酸化膜が約 20〜40オングストロームの厚さである 請求項 1記載の CVDによるチタン膜の成膜方法。  3. The method according to claim 1, wherein the silicon native oxide film has a thickness of about 20 to 40 angstroms.
4. シリコンの露出面を有する基板表面に CVDによりチタン膜を形成する 方法であって、 次の工程を含むもの、  4. A method of forming a titanium film by CVD on a substrate surface having an exposed surface of silicon, comprising the following steps:
基板表面のシリコン露出面の表面に少なくとも約 10オングストロームの厚さ のシリコン酸化膜を形成する工程、  Forming a silicon oxide film at least about 10 angstroms thick on the exposed silicon surface of the substrate surface;
該シリコン酸化膜を約 10〜 40オングストロームの厚みで残した状態で、 T i C 14を含むガスの供給を行い、 CVD法により該基板表面にチタン膜を成 膜する工程。 While leaving the silicon oxide film with a thickness of about 10 to 40 Angstroms, T i C 1 4 performs the supply of the gas containing the step of deposition of the titanium film on the substrate surface by CVD.
PCT/JP1999/000033 1998-01-09 1999-01-08 Method for forming titanium film by cvd WO1999035675A1 (en)

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JP1348398A JPH11204457A (en) 1998-01-09 1998-01-09 Method for forming cvd-ti film
JP10/13483 1998-01-09

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