WO2010087362A1 - Film formation method, and plasma film formation apparatus - Google Patents

Film formation method, and plasma film formation apparatus Download PDF

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Publication number
WO2010087362A1
WO2010087362A1 PCT/JP2010/051025 JP2010051025W WO2010087362A1 WO 2010087362 A1 WO2010087362 A1 WO 2010087362A1 JP 2010051025 W JP2010051025 W JP 2010051025W WO 2010087362 A1 WO2010087362 A1 WO 2010087362A1
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gas
film forming
plasma
film
nitriding
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PCT/JP2010/051025
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French (fr)
Japanese (ja)
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山▲崎▼　英亮
正人 小堆
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東京エレクトロン株式会社
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Priority to CN2010800059397A priority Critical patent/CN102301454A/en
Publication of WO2010087362A1 publication Critical patent/WO2010087362A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the shower head 40 is formed in a circular shape, and is provided so as to face the entire upper surface of the mounting table 36 so as to cover the mounting table 36, and a processing space S is formed between the shower head 40 and the mounting table 36.
  • This shower head 40 introduces various gases into the processing space S in a shower shape, and a plurality of injection holes 46 for injecting gas are formed on the injection surface on the lower surface of the shower head 40.
  • a gate valve 80 that is airtightly opened and closed when the semiconductor wafer W is loaded and unloaded is provided on the side wall of the processing chamber 22.
  • ⁇ Plasma TiN film formation (thin film formation process)> After the Ti film 8 is formed as described above, a thin film forming process for forming a thin film made of a TiN film (titanium nitride film) using plasma is performed (S2). This thin film forming process is continuously performed in the same processing vessel 22 following the above process.
  • a thin film made of the film 10 is formed by a plasma CVD method.
  • the semiconductor wafer W is heated and maintained at a predetermined temperature by the heating means 38 including a resistance heater.
  • the TiN film 10 is deposited not only on the top surface of the semiconductor wafer W but also on the bottom surface and side surfaces in the recess 6.
  • the TiN film 10 is formed by the plasma CVD method having a higher directivity of film formation than the normal thermal CVD method, it is compared with the case of film formation by the conventional thermal CVD method.
  • a very thin TiN film 10 is formed on the side surface of the recess 6, which is difficult to deposit.
  • the applied high frequency power is, for example, in the range of 400 to 1000 W (watts).
  • the process time is set so that the thickness of the TiN film 10 deposited on the bottom of the recess 6 falls within a range of 2 to 10 nm, for example.
  • the nitriding of the TiN film 10 is appropriately performed, and the film quality is improved and stabilized.
  • the barrier property is improved and the specific resistance is also reduced.
  • the process pressure is in the range of 400 to 667 Pa as described later, and the process temperature is in the range of 400 to 700 ° C., for example.
  • the flow rate of each gas is Ar gas in the range of 500 to 2000 sccm, H 2 gas in the range of 500 to 5000 sccm, and NH 3 gas in the range of 100 to 2000 sccm, for example.
  • the partial pressure of NH 3 gas is in the range of 44 to 308 Pa, for example.
  • the applied high frequency power is, for example, in the range of 400 to 1000 W (watts).
  • the process time of this nitriding treatment is in the range of 5 to 60 sec, preferably in the range of 10 to 40 sec, more preferably in the range of 15 to 30 sec, as will be described later. If this process time is shorter than 5 seconds, the effect of the nitriding treatment is insufficient, and not only the barrier property becomes insufficient but also the specific resistance becomes high, which is not preferable. On the other hand, when the process time is longer than 60 sec, nitriding is excessively performed, which is not preferable because not only the barrier property is insufficient but also the specific resistance is increased.
  • the film quality characteristics composed of the Ti film 8 and the plasma nitriding TiN film 10 are suitable as a good barrier layer 12.
  • the recess 6 is filled with the conductive film 9.
  • a tungsten film is embedded as the conductive material by a thermal CVD process, or copper is embedded as the conductive material by a plating process.
  • this conductive material is not limited to tungsten or copper.
  • the unnecessary conductive film 9 on the upper surface of the semiconductor wafer W is scraped off and removed.
  • the removal method for example, an etching process or CMP (Chemical Mechanical Polishing) or the like is used.
  • the Ti film 8 is formed in the lower layer of the TiN film 10, but an embodiment in which only the TiN film 10 is formed without forming the Ti film 8 may be employed.
  • the barrier layer 12 has a single layer structure consisting of only the TiN film 10.
  • FIG. 4 is a table illustrating the evaluation of barrier properties between a TiN film that has not been subjected to plasma nitriding and a TiN film that has been subjected to plasma nitriding.
  • FIG. 5 is a table for explaining the evaluation of barrier properties when a plasmaless annealing process is performed on a TiN film formed by a thermal CVD method or an SFD method, which is a conventional film forming method.
  • FIG. 6 is a graph showing the relationship between the plasma nitriding time and the increasing point rate of the sheet resistance (Rs) before and after the plasma nitriding treatment.
  • the barrier property in the evaluation is approximately the same as the barrier property of the two-layered barrier layer composed of the Ti film and the TiN film. It can be said.
  • a TiN film was formed on a silicon substrate by a plasma CVD method to form a barrier layer, and a Cu film was formed without plasma nitriding treatment.
  • a plasma CVD method to form a barrier layer
  • a Cu film was formed without plasma nitriding treatment.
  • three samples of Comparative Examples 1 to 3 were prepared by changing the flow rate of the TiCl 4 gas as the source gas or changing the process pressure. These samples were annealed for 30 minutes in an Ar atmosphere at 400 ° C. and 10 Torr (1333 Pa).
  • the method of evaluation is the same as in Examples 1 to 4. That is, the barrier property was evaluated by measuring the sheet resistance before and after the annealing treatment.
  • the thickness of the TiN film was all set to 10 nm except for Example 4.
  • Example 1 Same as Example 3 During film formation: Example 1 except that the process pressure was lowered to 400 Pa Same as in plasma nitriding: same as Example 1 [Example 4] During film formation: Same as Example 1 except that the film thickness was set to 2 nm. Plasma nitridation: Same as Example 1
  • Process conditions of Comparative Examples 1 to 3 that is, process temperature, process pressure, gas flow rate, applied high frequency power, and film thickness are as follows (see FIG. 4).
  • FIG. 4 shows the Rs increase point rate after 30 min annealing and its evaluation in Comparative Examples 1 to 3 and Examples 1 to 4.
  • “x” indicates NG (defective), and “ ⁇ ” indicates good.
  • the Rs increase point rates of Comparative Examples 1 to 3 were 15.7%, 94.2%, and 32.2%, respectively, and the barrier properties of the TiN film were not so good.
  • they are 3.3%, 8.3%, 4.1%, and 0.0%, which are all lower than the standard value of 10%, and the barrier property is greatly increased. It was found that it was improved.
  • Each Rs increase point rate (excluding Comparative Example 2) is also represented as a graph in FIG. From the above, it can be seen that in order to improve the barrier property of the TiN film, it is necessary to perform plasma nitriding after the formation of the TiN film by plasma. Further, according to FIG. 6, it can be recognized that the longer the plasma nitriding treatment, the lower the Rs increase point rate and the higher the barrier property. As will be described later, this Rs increase point rate is It is considered that the time is about 30 seconds and the bottom starts and then rises.
  • the barrier property can be improved by subjecting the TiN film to plasma nitriding.
  • the improvement of the barrier property by the method of the present invention is effective when the thickness of the TiN film is 2 to 10 nm. In other words, it has been found that sufficient barrier properties can be obtained even if the barrier layer is thinned to 2 nm.
  • a plasma is not used to form a TiN film on a silicon substrate, a TiN film is formed by a thermal CVD method or SFD method as a barrier layer, and plasma is not used for this.
  • the sample was subjected to NH 3 nitridation treatment according to, and a Cu film was further formed on the TiN film by sputtering.
  • four samples of Comparative Examples 4 to 7 were made by changing the process temperature and film thickness. These samples were annealed for 30 minutes in an Ar atmosphere at 400 ° C. and 10 Torr (1333 Pa). Then, the sheet resistance before and after the annealing treatment was measured as in the previous evaluation experiment, and the barrier property was evaluated. The result at this time is shown in FIG.
  • the SFD film formation is a film formation method in which deposition (deposition) and nitridation are alternately repeated while flowing each gas flow rate, and a thin film is laminated over a plurality of layers. And one cycle.
  • the plasma nitriding time in the nitriding step is preferably in the range of 5 to 60 seconds. If this time is shorter than 5 sec, not only the Rs value is large, but also the barrier property cannot be sufficiently exhibited. On the other hand, if this time is longer than 60 sec, the Rs value becomes excessively large, which is not preferable. In this case, as shown below, the graph shown in FIG. 6 is also expected to draw a downward characteristic curve, that is, it is presumed that the barrier property is also deteriorated.
  • a more preferable range of the plasma nitriding time is in the range of 10 to 40 sec.
  • a more preferable range is within the range of 15 to 30 sec which is the bottom portion of the curve.
  • Ar gas is used as the plasma gas, but the present invention is not limited to this.
  • Other noble gases such as He and Ne may be used.
  • NH 3 gas is used as the nitriding gas in the plasma nitriding step, the present invention is not limited to this.
  • N 2 gas, hydrazine (H 2 N—NH 2 ) gas, monomethyl hydrazine (CH 3 —NH—NH 2 ) gas, or the like may be used.
  • TiCl 4 gas is used as the source gas, but the present invention is not limited to this.
  • TDMAT (Ti [N (CH 3 ) 2 ] 4 : tetrakisdimethylaminotitanium) gas, TDEAT (Ti [N (C 2 H 5 ) 2 ] 4 : tetrakisdiethylaminotitanium) gas, or the like may be used.
  • a semiconductor wafer has been described as an example of the object to be processed, but the semiconductor wafer includes a silicon substrate or a compound semiconductor substrate such as GaAs, SiC, GaN. Furthermore, the present invention is not limited to these substrates, and the present invention can also be applied to glass substrates, ceramic substrates, and the like used in liquid crystal display devices.

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Abstract

Disclosed is a film formation method which can form a thin film on an object that has, formed on the surface thereof, an insulating layer having a depressed portion.  The method is characterized by comprising the following steps: a thin film formation step of forming a thin titanium nitride film on the surface of the object including the surface in the depressed portion by a plasma CVD technique; and a nitriding step of subjecting the thin film to a nitriding process using plasma in the presence of a nitrogen gas to nitride the thin film.

Description

成膜方法及びプラズマ成膜装置Film forming method and plasma film forming apparatus
　本発明は、成膜方法及びプラズマ成膜装置に係り、特に半導体ウエハ等の被処理体の表面にバリヤ層等の薄膜を形成する成膜方法及びプラズマ成膜装置に関する。 The present invention relates to a film forming method and a plasma film forming apparatus, and more particularly to a film forming method and a plasma film forming apparatus for forming a thin film such as a barrier layer on the surface of an object to be processed such as a semiconductor wafer.
　一般に、半導体デバイスを製造する際には、半導体ウエハに対して、成膜処理、エッチング処理、アニール処理、酸化拡散処理等の各種の処理が繰り返し行われる。これにより、所望のデバイスが製造される。半導体デバイスの製造工程の途中における配線材料や埋め込み材料としては、従来は主として、アルミニウム合金が用いられていた。しかし、最近は、線幅やホール径が益々微細化されて、且つ、動作速度の高速化が望まれていることから、タングステン（Ｗ）や銅（Ｃｕ）等も用いられる傾向にある。 Generally, when manufacturing a semiconductor device, various processes such as a film forming process, an etching process, an annealing process, and an oxidative diffusion process are repeatedly performed on a semiconductor wafer. Thereby, a desired device is manufactured. Conventionally, aluminum alloys have been mainly used as wiring materials and embedding materials in the process of manufacturing semiconductor devices. However, recently, since the line width and hole diameter are further miniaturized and an increase in operation speed is desired, tungsten (W), copper (Cu), and the like tend to be used.
　そして、前記Ａｌ、Ｗ、Ｃｕ等の金属材料を配線材料やコンタクトのためのホールの埋め込み材料として用いる場合には、例えばシリコン酸化膜（ＳｉＯ２　）等の絶縁材料と前記金属材料との間で、例えばシリコンの拡散が生ずることを防止する目的で、あるいは、膜の密着性を向上させるという目的で、あるいは、ホールの底部でコンタクトされる下層の電極や配線層等の導電層との間の密着性等を向上する目的で、前記絶縁材料や下層の導電層との間の境界部分にバリヤ層を介在させることが行われている。当該バリヤ層としては、Ｔａ膜、ＴａＮ膜、Ｔｉ膜、ＴｉＮ膜等が広く知られている（特開平１１－１８６１９７号公報、特開　２００４－２３２０８０号公報、特開２００３－１４２４２５号公報、特開２００６－１４８０７４号公報、及び、特表平１０－５０１１００号公報参照）。この点について、図８Ａ乃至図８Ｃを参照して説明する。 When the metal material such as Al, W, or Cu is used as a wiring material or a hole filling material for a contact, for example, between an insulating material such as a silicon oxide film (SiO 2 ) and the metal material. For example, for the purpose of preventing the diffusion of silicon, for the purpose of improving the adhesion of the film, or between conductive layers such as lower electrodes and wiring layers that are contacted at the bottom of the hole In order to improve the adhesion and the like, a barrier layer is interposed at the boundary portion between the insulating material and the lower conductive layer. As the barrier layer, a Ta film, a TaN film, a Ti film, a TiN film, and the like are widely known (Japanese Patent Laid-Open Nos. 11-186197, 2004-232080, 2003-142425, (See Kaikai 2006-148074 and JP-T-10-501100). This point will be described with reference to FIGS. 8A to 8C.
　図８Ａ乃至図８Ｃは、半導体ウエハの表面の凹部の埋め込み時の成膜方法を示す工程図である。図８Ａに示すように、被処理体としての例えばシリコン基板等よりなる半導体ウエハＷの表面に、例えば配線層等となる導電層１０２が形成されている。この導電層１０２を覆うようにして、半導体ウエハＷの表面全体に、例えばＳｉＯ２　膜等よりなる絶縁層１０４が所定の厚さで形成されている。前記導電層１０２は、例えば不純物がドープされたシリコン層よりなり、具体的には、トランジスタやコンデンサ等の電極等に対応する場合もある。特にトランジスタに対するコンタクトの場合には、ＮｉＳｉ（ニッケルシリサイド）等により形成される。 8A to 8C are process diagrams showing a film forming method at the time of embedding a concave portion on the surface of a semiconductor wafer. As shown in FIG. 8A, a conductive layer 102 that becomes a wiring layer or the like is formed on the surface of a semiconductor wafer W made of, for example, a silicon substrate or the like as an object to be processed. An insulating layer 104 made of, for example, a SiO 2 film is formed with a predetermined thickness on the entire surface of the semiconductor wafer W so as to cover the conductive layer 102. The conductive layer 102 is made of, for example, a silicon layer doped with impurities, and specifically corresponds to an electrode of a transistor or a capacitor. In particular, in the case of a contact with a transistor, it is formed of NiSi (nickel silicide) or the like.
　そして、前記絶縁層１０４に、前記導電層１０２に対して電気的コンタクトを図るためのスルーホールやビアホール等のコンタクト用の凹部１０６が形成されている。凹部１０６として、細長いトレンチ（溝）が形成される場合もある。この凹部１０６の底部で、導電層１０２の表面が露出した状態となっている。そして、この凹部１０６の底面及び側面を含めた半導体ウエハＷの表面全体に、すなわち、絶縁層１０４の上面全体に、前述したような機能を有するバリヤ層を形成するべく、図８Ｂに示すように、凹部１０６の表面（内面）全体も含めたウエハ表面全体（上面全体）に、例えばＴｉ膜１０８が成膜され、更に当該Ｔｉ膜８上に、図８Ｃに示すように、ＴｉＮ膜１１０が成形され、Ｔｉ膜１０８とＴｉＮ膜１１０との２層構造よりなるバリヤ層１１２が形成される。そして、ＴｉＮ膜１１０を安定化するために、ＮＨ３ 雰囲気中でこれを加熱することによって、窒化処理が加えられる。（尚、ＴｉＮ膜１１０を形成しないで、Ｔｉ膜１０８だけでバリヤ層１１２が構成される場合もある。）
　前記Ｔｉ膜１０８は、例えばスパッタ成膜処理やＴｉＣｌ４ を用いたプラズマＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法によって形成され、前記ＴｉＮ膜１１０は、例えばＴｉＣｌ４ ガス等を用いた熱ＣＶＤ法や原料ガスと窒化ガスとを交互に流すＳＦＤ（Ｓｅｑｕｅｎｔｉａｌ Ｆｌｏｗ Ｄｅｐｏｓｉｔｉｏｎ）法によって形成される。前記のようにしてバリヤ層１１２が形成されたならば、凹部１０６内がタングステン等の導電材料で埋め込められ、その後、余分な導電材料がエッチング等によって削り取られる。 A concave portion 106 for contact such as a through hole or a via hole for making electrical contact with the conductive layer 102 is formed in the insulating layer 104. An elongated trench (groove) may be formed as the recess 106. The surface of the conductive layer 102 is exposed at the bottom of the recess 106. Then, as shown in FIG. 8B, in order to form a barrier layer having the above-described function on the entire surface of the semiconductor wafer W including the bottom and side surfaces of the recess 106, that is, on the entire top surface of the insulating layer 104. For example, a Ti film 108 is formed on the entire wafer surface (entire upper surface) including the entire surface (inner surface) of the recess 106, and a TiN film 110 is formed on the Ti film 8 as shown in FIG. 8C. Thus, the barrier layer 112 having a two-layer structure of the Ti film 108 and the TiN film 110 is formed. Then, in order to stabilize the TiN film 110 by heating it in an NH 3 atmosphere, nitriding treatment is applied. (In some cases, the TiN film 110 is not formed, and the Ti layer 108 alone is used to form the barrier layer 112.)
The Ti film 108 is formed by, for example, a sputtering film forming process or a plasma CVD (Chemical Vapor Deposition) method using TiCl 4 , and the TiN film 110 is formed by, for example, a thermal CVD method using TiCl 4 gas or the like and a source gas It is formed by an SFD (Sequential Flow Deposition) method in which a nitriding gas is alternately flowed. When the barrier layer 112 is formed as described above, the recess 106 is filled with a conductive material such as tungsten, and then the excess conductive material is removed by etching or the like.
　最近にあっては、前記したバリヤ層１１２の材質の中で、図８Ａ乃至図８Ｃを用いて説明したように、特にＴｉＮ膜を含むバリヤ層１１２が注目されている。その理由は、ＴｉＮ膜を含むバリヤ層は、金属等の拡散を特に抑制でき、電気抵抗も非常に小さく、更には体積膨張率も小さく、配線材料との密着性も良好である等の利点を有するからである。 Recently, among the materials of the barrier layer 112 described above, as explained with reference to FIGS. 8A to 8C, the barrier layer 112 including a TiN film has attracted attention. The reason is that the barrier layer including the TiN film can particularly suppress the diffusion of metals, etc., has an extremely small electric resistance, and further has a small volume expansion coefficient and good adhesion to the wiring material. It is because it has.
　前述したようなバリヤ層１１２の形成方法は、線幅やホール径がそれ程厳しくなく設計基準が緩かった従来においては、それ程問題を生じていなかった。しかしながら、微細化傾向がより進んで線幅やホール径がより小さくなって設計基準が厳しくなった最近では、次のような問題が生じてきた。すなわち、前述したようにＴｉＮ膜を熱ＣＶＤ法やＳＦＤ法で形成する場合、これらの成膜方法はステップカバレジが良好なことから、凹部１０６の底部のみならず凹部１０６内の側壁の部分にも十分な厚さのＴｉＮ膜が堆積してしまうのである。 The method for forming the barrier layer 112 as described above has not caused much problems in the prior art in which the line width and hole diameter are not so strict and the design criteria are loose. However, in recent years when the trend toward miniaturization has further advanced and the line width and hole diameter have become smaller and the design standards have become stricter, the following problems have arisen. That is, as described above, when the TiN film is formed by the thermal CVD method or the SFD method, these film forming methods have good step coverage. A TiN film having a sufficient thickness is deposited.
　この結果、凹部１０６内に占めるＴｉＮ膜の比率が上がって、埋め込み金属材料例えばタングステンの比率が少なくなり、全体としてのコンタクト抵抗が増大してしまう、といった問題がある。特に、凹部１０６の穴径が５０ｎｍ以下になると、成膜時のステップカバレジの良さに起因して、コンタクト抵抗が急激に増大してしまう、といった問題がある。 As a result, there is a problem that the ratio of the TiN film in the recess 106 is increased, the ratio of the embedded metal material such as tungsten is decreased, and the contact resistance as a whole is increased. In particular, when the hole diameter of the recess 106 is 50 nm or less, there is a problem that the contact resistance increases rapidly due to good step coverage during film formation.
　そこで、熱ＣＶＤ法よりも指向性が高くて凹部の側壁に薄膜が堆積し難いプラズマを用いたＣＶＤ法によってＴｉＮ膜の薄膜を堆積することが行われている。これによれば、凹部内の底部にはある程度の厚さの薄膜が堆積するのに対して、凹部内の側壁部分には前記底部に対して僅かな厚さでしか薄膜が堆積しない。これにより、好都合なことに、凹部１０６内における埋め込み金属材料の比率（体積比）を高めることが可能である。 Therefore, a TiN film thin film is deposited by a CVD method using plasma, which has higher directivity than the thermal CVD method and is difficult to deposit a thin film on the side wall of the recess. According to this, a thin film having a certain thickness is deposited on the bottom portion in the concave portion, whereas the thin film is deposited on the side wall portion in the concave portion with a small thickness with respect to the bottom portion. This advantageously allows the ratio (volume ratio) of the embedded metal material in the recess 106 to be increased.
　しかしながら、この場合、バリヤ層の膜質がそれほど良好ではなく、バリヤ性が低下してしまう、といった問題がある。特に、微細化傾向によりバリヤ層自体をも薄膜化することが要請されているため、バリヤ性の維持がより困難になる、といった問題がある。 However, in this case, there is a problem that the film quality of the barrier layer is not so good and the barrier property is lowered. In particular, since there is a demand for thinning the barrier layer itself due to the trend toward miniaturization, there is a problem that it is more difficult to maintain barrier properties.
発明の要旨Summary of the Invention
　本発明は、以上のような問題点に着目し、これを有効に解決すべく創案されたものである。本発明の目的は、コンタクト抵抗を小さく維持し且つバリヤ性は高いというような薄膜を成膜する方法及び処理装置を提供することにある。 The present invention has been devised to pay attention to the above problems and to effectively solve them. An object of the present invention is to provide a method and a processing apparatus for forming a thin film that maintains a low contact resistance and has a high barrier property.
　本発明は、凹部を有する絶縁層が表面に形成された被処理体に対して薄膜を形成する成膜方法において、前記凹部内の表面を含む前記被処理体の表面に、プラズマＣＶＤ法を用いて、窒化チタン膜の薄膜を形成する薄膜形成工程と、窒化ガスの存在下で、プラズマを用いた窒化処理を行うことにより、前記薄膜を窒化する窒化工程と、を備えたことを特徴とする成膜方法である。 The present invention provides a film forming method in which a thin film is formed on an object to be processed on which an insulating layer having a recess is formed, and a plasma CVD method is used on the surface of the object to be processed including the surface in the recess A thin film forming step of forming a thin film of a titanium nitride film, and a nitriding step of nitriding the thin film by performing a nitriding treatment using plasma in the presence of a nitriding gas. This is a film forming method.
　本発明によって形成される薄膜は、全体としてのコンタクト抵抗を小さく維持できる一方、バリヤ性が高く顕著に有用であるということが、本件発明者によって実際に確認された。 It was actually confirmed by the present inventors that the thin film formed according to the present invention can keep the contact resistance as a whole small and has a high barrier property and is extremely useful.
　好ましくは、前記薄膜形成工程では、原料ガスとして、ＴｉＣｌ４ ガスが用いられる。 Preferably, in the thin film forming step, TiCl 4 gas is used as a source gas.
　また、好ましくは、前記薄膜形成工程において、前期凹部内の底部に形成される前記薄膜の厚さは、２～１０ｎｍの範囲内である。 Preferably, in the thin film formation step, the thickness of the thin film formed at the bottom of the first recess is in the range of 2 to 10 nm.
　また、好ましくは、前記窒化工程におけるプロセス時間は、５～６０ｓｅｃの範囲内である。 Also preferably, the process time in the nitriding step is in the range of 5 to 60 sec.
　また、好ましくは、前記薄膜形成工程におけるプロセス圧力は、４００～６６７Ｐａの範囲内である。 Preferably, the process pressure in the thin film forming step is in the range of 400 to 667 Pa.
　また、好ましくは、前記窒化工程で用いられる前記窒化ガスは、ＮＨ３ ガスである。 Preferably, the nitriding gas used in the nitriding step is NH 3 gas.
　また、好ましくは、前記薄膜形成工程の前工程として、前記凹部内の表面を含む前記被処理体に、プラズマＣＶＤ法を用いて、チタン膜よりなる薄膜を形成するチタン膜形成工程が行われる。 Further, preferably, as a pre-process of the thin film forming step, a titanium film forming step of forming a thin film made of a titanium film on the target object including the surface in the concave portion using a plasma CVD method is performed.
　この場合、好ましくは、前記チタン膜形成工程と前記薄膜形成工程と前記窒化工程とは、同一の処理容器内で連続的に行われる。 In this case, preferably, the titanium film forming step, the thin film forming step, and the nitriding step are continuously performed in the same processing vessel.
　あるいは、好ましくは、前記チタン膜形成工程の後であって前記薄膜形成工程の前に、前記チタン膜よりなる薄膜を窒化ガスの存在下でプラズマを用いて窒化するチタン膜窒化工程が行われる。 Alternatively, preferably, after the titanium film forming step and before the thin film forming step, a titanium film nitriding step is performed in which a thin film made of the titanium film is nitrided using plasma in the presence of a nitriding gas.
　この場合、好ましくは、前記チタン膜形成工程と前記チタン膜窒化工程と前記薄膜形成工程と前記窒化工程とは、同一の処理容器内で連続的に行われる。 In this case, preferably, the titanium film forming step, the titanium film nitriding step, the thin film forming step, and the nitriding step are continuously performed in the same processing vessel.
　また、好ましくは、前記窒化工程の後に、前記凹部内を導電性材料で埋め込む埋め込み工程が行なわれる。 Preferably, after the nitriding step, an embedding step of filling the concave portion with a conductive material is performed.
　また、好ましくは、前記凹部の内径又は幅は、５０ｎｍ以下に設定されている。 Preferably, the inner diameter or width of the recess is set to 50 nm or less.
　また、本発明は、凹部を有する絶縁層が表面に形成された被処理体に対して薄膜を形成するプラズマ処理装置において、真空排気が可能になされた処理容器と、前記処理容器内に配置され、前記被処理体を載置すると共に下部電極として機能する載置台と、前記被処理体を加熱する加熱手段と、前記処理容器内に配置され、当該処理容器内へ所定のガスを導入すると共に上部電極として機能するガス導入手段と、前記ガス導入手段へ前記所定のガスを供給するガス供給手段と、前記載置台と前記ガス導入手段との間にプラズマを形成するプラズマ形成手段と、前記いずれかの特徴を有する成膜方法を実施するように前記各手段を制御する制御部と、を備えたことを特徴とするプラズマ処理装置である。 The present invention also provides a plasma processing apparatus for forming a thin film on a target object having an insulating layer having a recess formed on a surface thereof, a processing container that can be evacuated, and the processing container disposed in the processing container. And a mounting table for mounting the object to be processed and functioning as a lower electrode, a heating means for heating the object to be processed, and being disposed in the processing container, and introducing a predetermined gas into the processing container Gas introducing means that functions as an upper electrode, gas supply means for supplying the predetermined gas to the gas introducing means, plasma forming means for forming plasma between the mounting table and the gas introducing means, and any of the above And a control unit that controls each of the means so as to carry out the film forming method having the above characteristics.
　また、本発明は、凹部を有する絶縁層が表面に形成された被処理体に対して薄膜を形成するプラズマ処理装置であって、真空排気が可能になされた処理容器と、前記処理容器内に配置され、前記被処理体を載置すると共に下部電極として機能する載置台と、前記被処理体を加熱する加熱手段と、前記処理容器内に配置され、当該処理容器内へ所定のガスを導入すると共に上部電極として機能するガス導入手段と、前記ガス導入手段へ前記所定のガスを供給するガス供給手段と、前記載置台と前記ガス導入手段との間にプラズマを形成するプラズマ形成手段と、を備えたプラズマ処理装置を制御して、前記いずれかの特徴を有する成膜方法を実施するコンピュータ読み取り可能なプログラムを記憶することを特徴とする記憶媒体である。 The present invention also provides a plasma processing apparatus for forming a thin film on a target object having an insulating layer having a recess formed on a surface thereof, a processing container that can be evacuated, and the processing container A placement table that is placed and places the object to be treated and functions as a lower electrode, a heating means for heating the object to be treated, and a treatment gas that is disposed in the treatment container and introduces a predetermined gas into the treatment container And a gas introducing means that functions as an upper electrode, a gas supplying means for supplying the predetermined gas to the gas introducing means, a plasma forming means for forming plasma between the mounting table and the gas introducing means, A storage medium storing a computer-readable program for controlling the plasma processing apparatus including the above and performing the film forming method having any one of the above characteristics.
本発明方法を実施するプラズマ処理装置の一例を示す概略構成図である。It is a schematic block diagram which shows an example of the plasma processing apparatus which enforces the method of this invention. 本発明方法の好適な一実施形態の各工程を示す工程図である。It is process drawing which shows each process of suitable one Embodiment of the method of this invention. 本発明方法の好適な一実施形態の各工程を示す工程図である。It is process drawing which shows each process of suitable one Embodiment of the method of this invention. 本発明方法の好適な一実施形態の各工程を示す工程図である。It is process drawing which shows each process of suitable one Embodiment of the method of this invention. 本発明方法の好適な一実施形態の各工程を示す工程図である。It is process drawing which shows each process of suitable one Embodiment of the method of this invention. 本発明方法の好適な一実施形態の各工程を示す工程図である。It is process drawing which shows each process of suitable one Embodiment of the method of this invention. 本発明方法の好適な一実施形態を示すフローチャートである。It is a flowchart which shows suitable one Embodiment of this invention method. プラズマ窒化処理が行われなかったＴｉＮ膜とプラズマ窒化処理が行われたＴｉＮ膜とのバリヤ性の評価について説明する表図である。It is a table | surface explaining the evaluation of the barrier property of the TiN film | membrane which was not plasma-nitrided, and the TiN film | membrane which was plasma-nitrided. 従来の成膜方法である熱ＣＶＤ法やＳＦＤ法で成膜されたＴｉＮ膜に対してプラズマレスのアニール処理を施した時のバリヤ性の評価について説明する表図である。It is a table | surface explaining the evaluation of barrier property when the plasmaless annealing process is performed with respect to the TiN film | membrane formed into a film forming method by the conventional CVD method and SFD method. プラズマ窒化時間と、当該プラズマ窒化処理の前後におけるシート抵抗（Ｒｓ）の増加ポイント率と、の関係を示すグラフである。It is a graph which shows the relationship between plasma nitriding time and the increase point rate of sheet resistance (Rs) before and behind the said plasma nitriding process. プラズマ窒化時間と、膜のシート抵抗（Ｒｓ）と、の関係を示すグラフである。It is a graph which shows the relationship between plasma nitridation time and the sheet resistance (Rs) of a film | membrane. 半導体ウエハの表面の凹部の埋め込み時の成膜方法を示す工程図である。It is process drawing which shows the film-forming method at the time of embedding the recessed part of the surface of a semiconductor wafer. 半導体ウエハの表面の凹部の埋め込み時の成膜方法を示す工程図である。It is process drawing which shows the film-forming method at the time of embedding the recessed part of the surface of a semiconductor wafer. 半導体ウエハの表面の凹部の埋め込み時の成膜方法を示す工程図である。It is process drawing which shows the film-forming method at the time of embedding the recessed part of the surface of a semiconductor wafer.
　以下に、本発明に係る成膜方法及びプラズマ処理装置の好適な一実施形態を、添付図面に基づいて詳述する。図１は、本発明方法を実施するプラズマ処理装置の一例を示す概略構成図であり、図２Ａ乃至図２Ｅは、本発明の成膜方法の好適な一実施形態の各工程を示す工程図であり、図３は、本発明の成膜方法の好適な一実施形態を示すフローチャートである。 Hereinafter, a preferred embodiment of a film forming method and a plasma processing apparatus according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a schematic configuration diagram showing an example of a plasma processing apparatus for carrying out the method of the present invention, and FIGS. 2A to 2E are process diagrams showing respective steps of a preferred embodiment of the film forming method of the present invention. FIG. 3 is a flowchart showing a preferred embodiment of the film forming method of the present invention.
　図示するように、本実施形態のプラズマ処理装置２０は、例えばアルミニウム、アルミニウム合金、ステンレススチール等により円筒体状に成形された処理容器２２を有している。この処理容器２２は、接地されている。処理容器２２の底部２４には、容器内の雰囲気を排出するための排気口２６が設けられている。この排気口２６に、真空排気系２８が接続されている。真空排気系２８は、前記排気口２６に接続された排気通路２９を有しており、この排気通路２９に、その上流側から下流側に向けて圧力調整を行うために弁開度が調整可能になされた圧力調整弁３０及び真空ポンプ３２が順次介設されている。これにより、処理容器２２内をその底部から均一に真空引きできるようになっている。 As shown in the figure, the plasma processing apparatus 20 of the present embodiment has a processing vessel 22 formed into a cylindrical shape from, for example, aluminum, aluminum alloy, stainless steel or the like. The processing container 22 is grounded. An exhaust port 26 for exhausting the atmosphere in the container is provided at the bottom 24 of the processing container 22. A vacuum exhaust system 28 is connected to the exhaust port 26. The vacuum exhaust system 28 has an exhaust passage 29 connected to the exhaust port 26, and the valve opening degree can be adjusted in the exhaust passage 29 in order to adjust the pressure from the upstream side to the downstream side. The pressure regulating valve 30 and the vacuum pump 32 are sequentially installed. Thereby, the inside of the processing container 22 can be uniformly evacuated from the bottom thereof.
　処理容器２２内には、導電性材料よりなる支柱３４を介して、円板状の載置台３６が設けられている。当該載置台３６上に、被処理体として例えばシリコン基板等の半導体ウエハＷが載置されるようになっている。具体的には、載置台３６は、ＡｌＮ等のセラミックからなり、その表面が導電性材料によりコーティングされており、プラズマ用電極の一方である下部電極を兼ねる。この下部電極は接地されている。載置台３６には、例えば直径が３００ｍｍの半導体ウエハＷが載置されるようになっている。尚、下部電極として、載置台３６内に例えばメッシュ状の導電性部材が埋め込まれる場合もある。 In the processing container 22, a disk-shaped mounting table 36 is provided via a support 34 made of a conductive material. On the mounting table 36, a semiconductor wafer W such as a silicon substrate is mounted as an object to be processed. Specifically, the mounting table 36 is made of ceramic such as AlN, and the surface thereof is coated with a conductive material, and also serves as a lower electrode that is one of plasma electrodes. This lower electrode is grounded. For example, a semiconductor wafer W having a diameter of 300 mm is placed on the mounting table 36. For example, a mesh-like conductive member may be embedded in the mounting table 36 as the lower electrode.
　載置台３６内には、例えば抵抗加熱ヒータ等よりなる加熱手段３８が埋め込まれており、半導体ウエハＷを加熱すると共に、これを所望の温度に維持できるようになっている。また、載置台３６には、半導体ウエハＷの周辺部を押圧してこれを載置台３６上に固定する図示しないクランプリングや、半導体ウエハＷの搬入・搬出時に半導体ウエハＷを突き上げて昇降させる図示しないリフタピンが設けられている。 A heating means 38 such as a resistance heater is embedded in the mounting table 36, so that the semiconductor wafer W can be heated and maintained at a desired temperature. In addition, the mounting table 36 includes a clamp ring (not shown) that presses the peripheral portion of the semiconductor wafer W and fixes it on the mounting table 36, and an illustration that pushes the semiconductor wafer W up and down when the semiconductor wafer W is loaded and unloaded. A lifter pin is provided.
　処理容器２２の天井部には、プラズマ用電極の他方である上部電極を兼ねるガス導入手段としてのシャワーヘッド４０が設けられている。このシャワーヘッド４０は、天井板４２と一体的に形成されている。この天井板４２の周辺部は、容器側壁の上端部に対して、絶縁材４４を介して気密に取り付けられている。このシャワーヘッド４０は、例えばアルミニウムやアルミニウム合金等の導電材料により形成されている。 The shower head 40 is provided on the ceiling portion of the processing vessel 22 as a gas introduction means that also serves as the upper electrode that is the other of the plasma electrodes. The shower head 40 is formed integrally with the ceiling plate 42. The peripheral portion of the ceiling plate 42 is airtightly attached to the upper end portion of the container side wall via an insulating material 44. The shower head 40 is made of a conductive material such as aluminum or an aluminum alloy.
　このシャワーヘッド４０は、円形に形成され、前記載置台３６の上面の略全面を覆うように対向させて設けられており、載置台３６との間に処理空間Ｓを形成している。このシャワーヘッド４０は、処理空間Ｓに各種のガスをシャワー状に導入するものであり、シャワーヘッド４０の下面の噴射面にはガスを噴射するための多数の噴射孔４６が形成されている。 The shower head 40 is formed in a circular shape, and is provided so as to face the entire upper surface of the mounting table 36 so as to cover the mounting table 36, and a processing space S is formed between the shower head 40 and the mounting table 36. This shower head 40 introduces various gases into the processing space S in a shower shape, and a plurality of injection holes 46 for injecting gas are formed on the injection surface on the lower surface of the shower head 40.
　そして、このシャワーヘッド４０の上部には、当該ヘッド内にガスを導入するガス導入ポート４８が設けられており、このガス導入ポート４８には、各種のガスを供給するガス供給手段５０が取り付けられている。このガス供給手段５０は、前記ガス導入ポート４８に接続されている供給通路５２を有している。 A gas introduction port 48 for introducing gas into the head is provided above the shower head 40, and a gas supply means 50 for supplying various gases is attached to the gas introduction port 48. ing. The gas supply means 50 has a supply passage 52 connected to the gas introduction port 48.
　この供給通路５２には、複数の分岐管５４が接続されており、各分岐管５４には、成膜用の原料ガスとして、例えばＴｉＣｌ４ ガスを貯留するＴｉＣｌ４ ガス源５６、Ｈ２ ガスを貯留するＨ２ ガス源５８、プラズマガスとして例えばＡｒガスを貯留するＡｒガス源６０、窒化ガスとして例えばアンモニアを貯留するＮＨ３ ガス源６２及びパージガス等として例えばＮ２ ガスを貯留するＮ２ ガス源６４がそれぞれ接続されている。そして、各ガスの流量は、それぞれの分岐管５４に介設された例えばマスフローコントローラのような流量制御器６６により制御される。また、各分岐管５４の流量制御器６６の上流側と下流側とには、必要に応じて前記各ガスの供給及び供給停止を行なう開閉弁６８が介設されている。 A plurality of branch pipes 54 are connected to the supply passage 52, and a TiCl 4 gas source 56 that stores, for example, TiCl 4 gas, and H 2 gas are used as the source gas for film formation in each branch pipe 54. An H 2 gas source 58 for storing, an Ar gas source 60 for storing, for example, Ar gas as a plasma gas, an NH 3 gas source 62 for storing, for example, ammonia as a nitriding gas, and an N 2 gas source, for example, storing N 2 gas as a purge gas or the like 64 are connected to each other. The flow rate of each gas is controlled by a flow rate controller 66 such as a mass flow controller provided in each branch pipe 54. In addition, on the upstream side and the downstream side of the flow rate controller 66 of each branch pipe 54, an opening / closing valve 68 is provided to supply and stop the supply of each gas as necessary.
　尚、ここでは、各ガスを１つの供給通路５２にて混合状態で供給する場合を示しているが、これに限定されない。一部のガス或いは全てのガスを個別に異なる供給通路内に供給し、シャワーヘッド４０内で混合させるという態様も採用され得る。また、供給するガス種によっては、供給通路５２内やシャワーヘッド４０内で混合させずに、各ガスを処理空間Ｓにて混合させる（いわゆるポストミックス）というガス搬送形態が用いられる。 In addition, although the case where each gas is supplied in a mixed state through one supply passage 52 is shown here, the present invention is not limited to this. A mode in which some or all of the gases are individually supplied into different supply passages and mixed in the shower head 40 may be employed. In addition, depending on the type of gas to be supplied, a gas transport mode is used in which each gas is mixed in the processing space S (so-called postmix) without being mixed in the supply passage 52 or the shower head 40.
　また、処理容器２２内における前記シャワーヘッド４０の外周と処理容器２２の内壁との間には、例えば石英等よりなるリング状の絶縁部材６９が設けられ、その下面はシャワーヘッド４０の噴射面と同一水平レベルに設定されている。これにより、プラズマ（後述する）が偏在しないようになっている。また、前記シャワーヘッド４０の上面側には、ヘッド加熱ヒータ７２が設けられており、シャワーヘッド４０を所望の温度に調整できるようになっている。 In addition, a ring-shaped insulating member 69 made of, for example, quartz is provided between the outer periphery of the shower head 40 and the inner wall of the processing container 22 in the processing container 22, and the lower surface thereof is an ejection surface of the shower head 40. The same horizontal level is set. This prevents plasma (described later) from being unevenly distributed. A head heater 72 is provided on the upper surface side of the shower head 40 so that the shower head 40 can be adjusted to a desired temperature.
　また、この処理容器２２は、載置台３６とシャワーヘッド４０との間の処理空間Ｓにプラズマを形成するプラズマ形成手段７４を有している。具体的には、プラズマ形成手段７４は、前記シャワーヘッド４０の上部に接続されたリード線７６を有しており、このリード線７６に、途中にマッチング回路７８を介して例えば４５０ｋＨｚのプラズマ発生用電源である高周波電源７０が接続されている。ここで、この高周波電源７０にあっては、任意の大きさの電力を出力できるように、出力電力が可変となっている。 Further, the processing container 22 has plasma forming means 74 for forming plasma in the processing space S between the mounting table 36 and the shower head 40. Specifically, the plasma forming means 74 has a lead wire 76 connected to the upper portion of the shower head 40, and the lead wire 76 is connected to the lead wire 76 via a matching circuit 78 on the way for generating plasma of 450 kHz, for example. A high frequency power source 70 as a power source is connected. Here, in the high frequency power source 70, the output power is variable so that an arbitrary amount of power can be output.
　その他、処理容器２２の側壁には、半導体ウエハＷの搬入・搬出時に気密に開閉可能になされたゲートバルブ８０が設けられている。 In addition, a gate valve 80 that is airtightly opened and closed when the semiconductor wafer W is loaded and unloaded is provided on the side wall of the processing chamber 22.
　そして、プラズマ処理装置２０の全体の動作を制御するために、例えばコンピュータ等よりなる制御部８２が設けられている。制御部８２は、例えば、プロセス圧力、プロセス温度、各ガスの供給量の制御のための指示、高周波電力のオン・オフを含めた供給電力の指示、等を行うようになっている。そして、制御部８２は、前記制御に必要なコンピュータプログラムを記憶する記憶媒体８４を有している。この記憶媒体８４は、例えばフレキシブルディスク、ＣＤ（Ｃｏｍｐａｃｔ Ｄｉｓｃ）、ハードディスク、フラッシュメモリ或いはＤＶＤ等よりなる。 In order to control the overall operation of the plasma processing apparatus 20, a control unit 82 made of, for example, a computer is provided. For example, the control unit 82 is configured to give an instruction for controlling the process pressure, the process temperature, the supply amount of each gas, an instruction for supply power including on / off of high-frequency power, and the like. And the control part 82 has the storage medium 84 which memorize | stores the computer program required for the said control. The storage medium 84 includes, for example, a flexible disk, a CD (Compact Disc), a hard disk, a flash memory, or a DVD.
［成膜方法の説明］
　次に、以上のように構成されたプラズマ処理装置を用いて行われる本発明の成膜方法の一実施形態について、図１乃至図３を参照して説明する。ここでは、プラズマ処理方法の一例として、Ｔｉ膜及びＴｉＮ膜を成膜し、その後に窒化処理する場合を説明する。 [Description of deposition method]
Next, an embodiment of the film forming method of the present invention performed using the plasma processing apparatus configured as described above will be described with reference to FIGS. Here, as an example of the plasma processing method, a case where a Ti film and a TiN film are formed and then nitriding is described.
　まず、処理容器２２内へ、開放されたゲートバルブ８０を介して、例えば直径が３００ｍｍの半導体ウエハＷが搬入される。当該半導体ウエハＷが、載置台３６上に載置された後、処理容器２２内が密閉される。この半導体ウエハＷの表面は、図２Ａに示すようになっている。図２Ａに示す構造は、図８Ａに示した構造と同じである。 First, for example, a semiconductor wafer W having a diameter of 300 mm is loaded into the processing container 22 through the opened gate valve 80. After the semiconductor wafer W is mounted on the mounting table 36, the inside of the processing container 22 is sealed. The surface of the semiconductor wafer W is as shown in FIG. 2A. The structure shown in FIG. 2A is the same as the structure shown in FIG. 8A.
　すなわち、半導体ウエハＷの表面に、例えば配線層等となる導電層２が形成されており、この導電層２を覆うようにして、半導体ウエハＷの表面全体に、例えばＳｉＯ２ 膜等よりなる絶縁層４が所定の厚さで形成されている。導電層２は、例えば不純物がドープされたシリコン層よりなり、具体的には、トランジスタやコンデンサ等の電極等に対応する場合もある。特にトランジスタに対するコンタクトの場合には、ＮｉＳｉ（ニッケルシリサイド）等により形成される。 That is, a conductive layer 2 to be a wiring layer or the like is formed on the surface of the semiconductor wafer W, and an insulation made of a SiO 2 film or the like is formed on the entire surface of the semiconductor wafer W so as to cover the conductive layer 2. The layer 4 is formed with a predetermined thickness. The conductive layer 2 is made of, for example, a silicon layer doped with impurities, and specifically corresponds to an electrode of a transistor or a capacitor. In particular, in the case of a contact with a transistor, it is formed of NiSi (nickel silicide) or the like.
　そして、前記絶縁層４に、前記導電層２に対して電気的コンタクトを図るためのスルーホールやビアホール等のコンタクト用の凹部６が形成されている。凹部６の内径（凹部６が溝の場合は幅）は、例えば５０ｎｍ以下である（凹部６として、細長いトレンチ（溝）を形成する場合もある）。この凹部６の底部で、導電層２の表面が露出した状態となっている。そして、この凹部６内の底面及び側面を含めた半導体ウエハＷの表面全体に、すなわち、絶縁層４の上面全体に、前述したような機能を有するバリヤ層が形成される。 In the insulating layer 4, contact recesses 6 such as through holes and via holes for making electrical contact with the conductive layer 2 are formed. The inner diameter of the concave portion 6 (the width when the concave portion 6 is a groove) is, for example, 50 nm or less (the elongated trench (groove) may be formed as the concave portion 6). The surface of the conductive layer 2 is exposed at the bottom of the recess 6. Then, a barrier layer having the above-described function is formed on the entire surface of the semiconductor wafer W including the bottom surface and side surfaces in the recess 6, that is, on the entire top surface of the insulating layer 4.
＜Ｔｉ膜の成膜＞
　前述のように、半導体ウエハＷを搬入した後に処理容器２２内を密閉したならば、Ｔｉ膜の成膜が行われる（図３のＳ１）。まず、ガス供給手段５０から、原料ガスのＴｉＣｌ４ ガスと、還元ガスのＨ２ ガスと、プラズマ用ガスのＡｒガスとが、それぞれガス導入手段であるシャワーヘッド４０に所定の流量で流されると共に、これらの各ガスがシャワーヘッド４０から処理容器２２内に導入され、且つ、真空排気系２８の真空ポンプ３２により処理容器２２内が真空引きされて、所定の圧力が維持される。 <Ti film formation>
As described above, if the inside of the processing container 22 is sealed after the semiconductor wafer W is loaded, a Ti film is formed (S1 in FIG. 3). First, the source gas TiCl 4 gas, the reducing gas H 2 gas, and the plasma gas Ar gas are respectively supplied from the gas supply means 50 to the shower head 40 as the gas introduction means at a predetermined flow rate. These gases are introduced into the processing container 22 from the shower head 40, and the processing container 22 is evacuated by the vacuum pump 32 of the evacuation system 28 to maintain a predetermined pressure.
　これと同時に、プラズマ形成手段７４の高周波電源７０より、４５０ｋＨｚの高周波が上部電極であるシャワーヘッド４０に印加されて、シャワーヘッド４０と下部電極としての載置台３６との間に高周波電界が加えられる（電力投入される）。これにより、Ａｒガスがプラズマ化されて、ＴｉＣｌ４ ガスとＨ２ ガスとの還元反応が推進され、半導体ウエハＷの表面に図２Ｂに示すように薄膜としてのＴｉ膜８がプラズマＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法によって成膜される。半導体ウエハＷの温度は、載置台３６に埋め込まれた抵抗加熱ヒータよりなる加熱手段３８によって、所定の温度に加熱維持される。このような態様により、半導体ウエハＷの上面のみならず、凹部６内の底面や側面にもＴｉ膜８が堆積される。 At the same time, a 450 kHz high frequency is applied from the high frequency power supply 70 of the plasma forming means 74 to the shower head 40 as the upper electrode, and a high frequency electric field is applied between the shower head 40 and the mounting table 36 as the lower electrode. (Power is turned on). As a result, the Ar gas is turned into plasma, and the reduction reaction between the TiCl 4 gas and the H 2 gas is promoted, and the Ti film 8 as a thin film is formed on the surface of the semiconductor wafer W as shown in FIG. 2B by plasma CVD (Chemical Vapor). The film is formed by the Deposition method. The temperature of the semiconductor wafer W is maintained at a predetermined temperature by the heating means 38 made of a resistance heater embedded in the mounting table 36. In this manner, the Ti film 8 is deposited not only on the upper surface of the semiconductor wafer W but also on the bottom surface and side surfaces in the recess 6.
　ここでのプロセスの条件は、例えば、半導体ウエハＷの温度が、例えば４００～７００℃程度、プロセス圧力が、６６７Ｐａ（≒５Ｔｏｒｒ）程度である。また、ガス流量に関しては、ＴｉＣｌ４ ガスは、６．７～１２ｓｃｃｍ程度、Ｈ２ ガスは、１６００ｓｃｃｍ程度、Ａｒガスは、８００～４０００ｓｃｃｍ程度である。また、プロセス時間は、３０～５０ｓｅｃ程度で、得られるＴｉ膜の膜厚は、１０ｎｍ程度である。また、プラズマ発生用電源７０より供給される電力は、例えば８００ワットであ。 The process conditions here are, for example, that the temperature of the semiconductor wafer W is, for example, about 400 to 700 ° C., and the process pressure is about 667 Pa (≈5 Torr). Regarding the gas flow rate, TiCl 4 gas is about 6.7 to 12 sccm, H 2 gas is about 1600 sccm, and Ar gas is about 800 to 4000 sccm. The process time is about 30 to 50 sec, and the thickness of the obtained Ti film is about 10 nm. The power supplied from the plasma generating power supply 70 is, for example, 800 watts.
　尚、必要ならば、同一の処理容器２２内で、前記Ｔｉ膜８に対して窒化ガスであるＮＨ３ ガスとＮ２ ガスとの存在下でＡｒガスを加えてプラズマを立て、プラズマ窒化処理（チタン膜窒化処理）を施してもよい。 If necessary, plasma is generated by adding Ar gas in the presence of NH 3 gas and N 2 gas, which are nitriding gases, to the Ti film 8 in the same processing vessel 22, and plasma nitriding treatment ( Titanium film nitriding treatment) may be performed.
＜プラズマＴｉＮ成膜（薄膜成膜工程）＞
　以上のようにしてＴｉ膜８の成膜処理が行われたならば、次に、プラズマを用いてＴｉＮ膜（窒化チタン膜）よりなる薄膜を形成する薄膜成膜工程が行われる（Ｓ２）。この薄膜成膜工程は、同じ処理容器２２内で、前記工程に続いて連続的に行われる。 <Plasma TiN film formation (thin film formation process)>
After the Ti film 8 is formed as described above, a thin film forming process for forming a thin film made of a TiN film (titanium nitride film) using plasma is performed (S2). This thin film forming process is continuously performed in the same processing vessel 22 following the above process.
　まず、原料ガスのＴｉＣｌ４ ガスと、Ｎ２ ガスと、還元ガスのＨ２ ガスと、プラズマ用ガスのＡｒガスとが、それぞれシャワーヘッド４０より処理容器２２内へ所定の流量で導入され、且つ、処理容器２２内が真空ポンプ３２で真空引きされて、処理容器２２内が所定の圧力に維持される。 First, source gas TiCl 4 gas, N 2 gas, reducing gas H 2 gas, and plasma gas Ar gas are respectively introduced into the processing vessel 22 from the shower head 40 at a predetermined flow rate, and The inside of the processing container 22 is evacuated by the vacuum pump 32, and the inside of the processing container 22 is maintained at a predetermined pressure.
　これと同時に、シャワーヘッド４０と載置台３６との間に高周波電力が印加されてＡｒガスのプラズマが生成され、ＴｉＣｌ４ ガスとＮ２ ガスとが反応して、図２Ｃに示すように、ＴｉＮ膜１０よりなる薄膜がプラズマＣＶＤ法によって形成される。この時、半導体ウエハＷは、抵抗加熱ヒータよりなる加熱手段３８によって所定の温度に加熱維持されている。 At the same time, high-frequency power is applied between the shower head 40 and the mounting table 36 to generate Ar gas plasma, and the TiCl 4 gas and N 2 gas react to form TiN 4 as shown in FIG. 2C. A thin film made of the film 10 is formed by a plasma CVD method. At this time, the semiconductor wafer W is heated and maintained at a predetermined temperature by the heating means 38 including a resistance heater.
　これにより、半導体ウエハＷの上面のみならず、凹部６内の底面や側面にもＴｉＮ膜１０が堆積する。この場合、通常の熱ＣＶＤ法よりも成膜の指向性が高いプラズマＣＶＤ法によってＴｉＮ膜１０が成膜されるので、従来において一般的に行われている熱ＣＶＤ法による成膜の場合と比較して、凹部６内の底部には十分な厚さで薄膜が堆積する一方、凹部６内の側面には薄膜が堆積し難く非常に薄いＴｉＮ膜１０が形成されることになる。 Thereby, the TiN film 10 is deposited not only on the top surface of the semiconductor wafer W but also on the bottom surface and side surfaces in the recess 6. In this case, since the TiN film 10 is formed by the plasma CVD method having a higher directivity of film formation than the normal thermal CVD method, it is compared with the case of film formation by the conventional thermal CVD method. Thus, while a thin film is deposited with a sufficient thickness on the bottom of the recess 6, a very thin TiN film 10 is formed on the side surface of the recess 6, which is difficult to deposit.
　この時のプロセス条件は、プロセス圧力が、例えば３００～８００Ｐａの範囲内であり、プロセス温度が、例えば４００～７００℃の範囲内である。また、各ガスの流量は、ＴｉＣｌ４ ガスが例えば４～２０ｓｃｃｍの範囲内、Ａｒガスが例えば５００～２０００ｓｃｃｍの範囲内、Ｈ２ ガスが例えば５００～５０００ｓｃｃｍの範囲内、Ｎ２ ガスが例えば１０～１０００ｓｃｃｍの範囲内である。またＴｉＣｌ４　ガスとＮ２ ガスの分圧は、ＴｉＣｌ４　ガス分圧が例えば０．３～６．０Ｐａの範囲内、Ｎ２ ガス分圧が例えば１～１５０Ｐａの範囲内である。そして、印加される高周波電力は、例えば４００～１０００Ｗ（ワット）の範囲内である。ここでは、例えば凹部６の底部に堆積するＴｉＮ膜１０の厚さが、例えば２～１０ｎｍの範囲内になるように、プロセス時間が設定される。 The process conditions at this time include a process pressure in the range of 300 to 800 Pa, for example, and a process temperature in the range of 400 to 700 ° C., for example. The flow rates of the respective gases are as follows: TiCl 4 gas is in the range of 4 to 20 sccm, Ar gas is in the range of 500 to 2000 sccm, H 2 gas is in the range of 500 to 5000 sccm, and N 2 gas is in the range of 10 to Within the range of 1000 sccm. The partial pressures of TiCl 4 gas and N 2 gas are such that the TiCl 4 gas partial pressure is in the range of 0.3 to 6.0 Pa, for example, and the N 2 gas partial pressure is in the range of 1 to 150 Pa, for example. The applied high frequency power is, for example, in the range of 400 to 1000 W (watts). Here, for example, the process time is set so that the thickness of the TiN film 10 deposited on the bottom of the recess 6 falls within a range of 2 to 10 nm, for example.
＜窒化工程＞
　以上のようにしてＴｉＮ膜１０の成膜処理が行われたならば、次に、本発明の特徴であるプラズマを用いた窒化工程が行われる（Ｓ３）。この窒化工程は、同じ処理容器２２内で、前記前工程に続いて連続的に行われる。 <Nitriding process>
After the TiN film 10 is formed as described above, a nitriding step using plasma, which is a feature of the present invention, is then performed (S3). This nitriding step is continuously performed in the same processing vessel 22 following the previous step.
　まず、還元ガスのＨ２ ガスと、プラズマ用ガスのＡｒガスと、窒化ガスのＮＨ３ ガスとが、シャワーヘッド４０より処理容器２２内へそれぞれ所定の流量で導入され、且つ、真空ポンプ３２で真空引きされて、所定の圧力が維持される。これと同時に、シャワーヘッド４０と載置台３６との間に高周波電力が印加されて、Ａｒガスのプラズマが生成されて、ＮＨ３ ガスの活性種が作られる。この活性種（ＮＨ３ ＊）により、前記ＴｉＮ膜１０に対して、図２Ｄに示すような窒化処理が施される。 First, a reducing gas H 2 gas, a plasma gas Ar gas, and a nitriding gas NH 3 gas are introduced into the processing vessel 22 from the shower head 40 at a predetermined flow rate, respectively. A predetermined pressure is maintained by evacuation. At the same time, high-frequency power is applied between the shower head 40 and the mounting table 36 to generate Ar gas plasma, thereby producing NH 3 gas active species. With this active species (NH 3 *), the TiN film 10 is subjected to nitriding as shown in FIG. 2D.
　これにより、ＴｉＮ膜１０の窒化が適度になされて、膜質が改善されると共に安定化される。これにより、後述するように、バリヤ性が向上すると共に比抵抗も減少することになる。 Thereby, the nitriding of the TiN film 10 is appropriately performed, and the film quality is improved and stabilized. As a result, as will be described later, the barrier property is improved and the specific resistance is also reduced.
　この時のプロセス条件は、プロセス圧力が、後述するように４００～６６７Ｐａの範囲内であり、プロセス温度が、例えば４００～７００℃の範囲内である。また、各ガスの流量は、Ａｒガスが例えば５００～２０００ｓｃｃｍの範囲内であり、Ｈ２ ガスが例えば５００～５０００ｓｃｃｍの範囲内であり、ＮＨ３ ガスが例えば１００～２０００ｓｃｃｍの範囲内である。また、ＮＨ３　ガスの分圧は、例えば４４～３０８Ｐ ａの範囲内である。そして、印加される高周波電力は、例えば４００～１０００Ｗ（ワット）の範囲内である。 As process conditions at this time, the process pressure is in the range of 400 to 667 Pa as described later, and the process temperature is in the range of 400 to 700 ° C., for example. The flow rate of each gas is Ar gas in the range of 500 to 2000 sccm, H 2 gas in the range of 500 to 5000 sccm, and NH 3 gas in the range of 100 to 2000 sccm, for example. The partial pressure of NH 3 gas is in the range of 44 to 308 Pa, for example. The applied high frequency power is, for example, in the range of 400 to 1000 W (watts).
　更に、この窒化処理のプロセス時間は、後述するように、５～６０ｓｅｃの範囲内、好ましくは１０～４０ｓｅｃの範囲内、より好ましくは１５～３０ｓｅｃの範囲内である。このプロセス時間が５ｓｅｃよりも短い場合には、窒化処理の効果が不十分であって、バリヤ性が不十分になるばかりか比抵抗も高くなって好ましくない。一方、プロセス時間が６０ｓｅｃよりも長い場合には、窒化が過度に行われてしまって、やはりバリヤ性が不十分になるばかりか比抵抗も高くなって好ましくない。Ｔｉ膜８とプラズマ窒化処理されたＴｉＮ膜１０とからなる膜質特性は、良好なバリヤ層１２として好適である。 Furthermore, the process time of this nitriding treatment is in the range of 5 to 60 sec, preferably in the range of 10 to 40 sec, more preferably in the range of 15 to 30 sec, as will be described later. If this process time is shorter than 5 seconds, the effect of the nitriding treatment is insufficient, and not only the barrier property becomes insufficient but also the specific resistance becomes high, which is not preferable. On the other hand, when the process time is longer than 60 sec, nitriding is excessively performed, which is not preferable because not only the barrier property is insufficient but also the specific resistance is increased. The film quality characteristics composed of the Ti film 8 and the plasma nitriding TiN film 10 are suitable as a good barrier layer 12.
＜埋め込み工程＞
　以上のようにしてＴｉＮ膜の窒化工程が行われたならば、次に、半導体ウエハＷが処理容器２２内から搬出されて、埋め込み工程が行われる（Ｓ４）。この埋め込み工程では、例えば他の成膜装置によって、前記凹部６内を含む半導体ウエハＷの表面に導電性材料の成膜が行われる。これにより、図２Ｅに示すように、前記凹部６内に前記導電性材料が埋め込まれる（埋め込み工程）。 <Embedding process>
If the TiN film nitriding step is performed as described above, then the semiconductor wafer W is unloaded from the processing chamber 22 and a filling step is performed (S4). In this embedding process, a conductive material is formed on the surface of the semiconductor wafer W including the inside of the recess 6 by, for example, another film forming apparatus. Thereby, as shown in FIG. 2E, the conductive material is embedded in the recess 6 (embedding step).
　これにより、前記凹部６内は導電性膜９により埋め込まれることになる。この埋め込み工程では、例えば熱ＣＶＤ処理により前記導電性材料としてタングステン膜が埋め込まれたり、或いは、メッキ処理により前記導電性材料として銅が埋め込まれたりする。もっとも、この導電性材料は、タングステンや銅に限定されるものではない。 Thereby, the recess 6 is filled with the conductive film 9. In this embedding process, for example, a tungsten film is embedded as the conductive material by a thermal CVD process, or copper is embedded as the conductive material by a plating process. However, this conductive material is not limited to tungsten or copper.
　このようにして埋め込み工程が完了したならば、半導体ウエハＷの上面の不要な導電性膜９が削り取られて除去される。この除去の方法としては、例えばエッチング処理やＣＭＰ（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ）等が用いられる。 When the embedding process is completed in this way, the unnecessary conductive film 9 on the upper surface of the semiconductor wafer W is scraped off and removed. As the removal method, for example, an etching process or CMP (Chemical Mechanical Polishing) or the like is used.
　尚、前記実施形態では、ＴｉＮ膜１０の下層にＴｉ膜８が形成されたが、Ｔｉ膜８を形成することなくＴｉＮ膜１０のみを形成する態様も採用され得る。この場合には、バリヤ層１２は、ＴｉＮ膜１０だけの一層構造となる。 In the embodiment, the Ti film 8 is formed in the lower layer of the TiN film 10, but an embodiment in which only the TiN film 10 is formed without forming the Ti film 8 may be employed. In this case, the barrier layer 12 has a single layer structure consisting of only the TiN film 10.
　以上のような本実施形態によれば、凹部６を有する被処理体、例えば半導体ウエハＷの表面に、薄膜、例えばＴｉＮ膜１０を形成するに際して、凹部６内の表面を含む被処理体の表面にプラズマＣＶＤ法を用いて窒化チタン膜（ＴｉＮ膜）１０の薄膜を形成し、当該膜膜を例えばＮＨ３ の存在下でプラズマを用いて窒化することにより、全体としてのコンタクト抵抗を小さく維持できる一方、バリヤ性を顕著に高くすることができる。 According to the present embodiment as described above, when a thin film, for example, a TiN film 10 is formed on the surface of an object to be processed having a recess 6, for example, a semiconductor wafer W, the surface of the object to be processed including the surface in the recess 6. By forming a thin film of a titanium nitride film (TiN film) 10 using a plasma CVD method, and nitriding the film using, for example, plasma in the presence of NH 3 , the overall contact resistance can be kept small. On the other hand, the barrier property can be remarkably increased.
＜プラズマ窒化処理されたＴｉＮ膜の評価＞
　次に、前記実施形態に従ってプラズマ窒化処理されたＴｉＮ膜の評価が行われた。その評価結果について説明する。 <Evaluation of Plasma Nitrided TiN Film>
Next, evaluation of the plasma nitrided TiN film according to the embodiment was performed. The evaluation result will be described.
　図４は、プラズマ窒化処理が行われなかったＴｉＮ膜とプラズマ窒化処理が行われたＴｉＮ膜とのバリヤ性の評価について説明する表図である。図５は、従来の成膜方法である熱ＣＶＤ法やＳＦＤ法で成膜されたＴｉＮ膜に対してプラズマレスのアニール処理を施した時のバリヤ性の評価について説明する表図である。図６は、プラズマ窒化時間と、当該プラズマ窒化処理の前後におけるシート抵抗（Ｒｓ）の増加ポイント率と、の関係を示すグラフである。 FIG. 4 is a table illustrating the evaluation of barrier properties between a TiN film that has not been subjected to plasma nitriding and a TiN film that has been subjected to plasma nitriding. FIG. 5 is a table for explaining the evaluation of barrier properties when a plasmaless annealing process is performed on a TiN film formed by a thermal CVD method or an SFD method, which is a conventional film forming method. FIG. 6 is a graph showing the relationship between the plasma nitriding time and the increasing point rate of the sheet resistance (Rs) before and after the plasma nitriding treatment.
　ここでは、バリヤ層として、Ｔｉ膜が形成されていないＴｉＮ膜の単層構造の評価が行われた。Ｔｉ膜は、下地との密着性を改善するものであることから、当該評価におけるバリヤ性は、Ｔｉ膜とＴｉＮ膜とよりなる２層構造のバリヤ層のバリヤ性と略同じ程度のものであると言える。 Here, a single layer structure of a TiN film in which no Ti film was formed as a barrier layer was evaluated. Since the Ti film improves the adhesion to the base, the barrier property in the evaluation is approximately the same as the barrier property of the two-layered barrier layer composed of the Ti film and the TiN film. It can be said.
　評価のための具体的な実験として、シリコン基板の上に評価の対象となるＴｉＮ膜をプラズマＣＶＤ法によって形成してバリヤ層とし、このＴｉＮ膜をプラズマ窒化処理し、或いはプラズマ窒化処理しないで、それらＴｉＮ膜上にスパッタによりＣｕ膜を形成してサンプルとした。前記バリヤ層の作成に際しては、プラズマ窒化時間を変えたり、プロセス圧力を変えたり、膜厚を変えたりして、実施例１～４の４個のサンプルを作った。そして、これらのサンプルの作成直後と、これらのサンプルにＣｕの拡散を促進するためにアニール処理（４００℃、１０ＴｏｒｒのＡｒ雰囲気中で３０ｍｉｎ）を施した直後とで、薄膜のシート抵抗をそれぞれ１２１ポイントの箇所で測定して、Ｒｓ（シート抵抗）の値の変化が求められた。 As a specific experiment for evaluation, a TiN film to be evaluated is formed on a silicon substrate by a plasma CVD method to form a barrier layer, and this TiN film is plasma-nitrided or not plasma-nitrided. A Cu film was formed on the TiN film by sputtering to prepare a sample. In preparing the barrier layer, four samples of Examples 1 to 4 were prepared by changing the plasma nitriding time, changing the process pressure, and changing the film thickness. The sheet resistance of the thin film is 121 immediately after the preparation of these samples and immediately after the samples are annealed to promote the diffusion of Cu (400 ° C., 30 min in Ar atmosphere of 10 Torr). The change in the value of Rs (sheet resistance) was determined by measuring at the point.
　前記アニール処理の前後でＲｓ値が変化していない場合は、バリヤ性が高くて良好であると言える。アニール処理によってＲｓ値が上昇して高くなっている場合は、ＴｉＮ膜よりなるバリヤ層を介してＳｉとＣｕとが反応してしまっていることを意味するから、バリヤ性は低くて不良であると言える。尚、銅（Ｃｕ）はタングステン（Ｗ）と比較して熱拡散性が大きいので、銅を用いた評価でバリヤ性が良好ならば、タングステンに対しては更にバリヤ性が良好であると言える。 When the Rs value does not change before and after the annealing treatment, it can be said that the barrier property is high and good. When the Rs value is increased and increased by the annealing treatment, it means that Si and Cu have reacted through the barrier layer made of the TiN film, so that the barrier property is low and poor. It can be said. Since copper (Cu) has a higher thermal diffusivity than tungsten (W), it can be said that if the barrier property is good in the evaluation using copper, the barrier property is better for tungsten.
　比較例として、シリコン基板の上にプラズマＣＶＤ法によってＴｉＮ膜を形成してバリヤ層とし、これにプラズマ窒化処理を施すことなくＣｕ膜を形成した。バリヤ層の作成に際して、原料ガスであるＴｉＣｌ４ ガスの流量を変えたり、プロセス圧力を変えたりして、比較例１～３の３個のサンプルを作った。そして、これらのサンプルに、４００℃、１０Ｔｏｒｒ（１３３３Ｐａ）のＡｒ雰囲気中で３０ｍｉｎのアニール処理が施された。評価の仕方は、実施例１～４の場合と同じである。すなわち、アニール処理の前後のシート抵抗を測定して、バリヤ性の評価が行われた。なお、ＴｉＮ膜の膜厚は、実施例４を除いて、全て１０ｎｍに設定された。 As a comparative example, a TiN film was formed on a silicon substrate by a plasma CVD method to form a barrier layer, and a Cu film was formed without plasma nitriding treatment. When preparing the barrier layer, three samples of Comparative Examples 1 to 3 were prepared by changing the flow rate of the TiCl 4 gas as the source gas or changing the process pressure. These samples were annealed for 30 minutes in an Ar atmosphere at 400 ° C. and 10 Torr (1333 Pa). The method of evaluation is the same as in Examples 1 to 4. That is, the barrier property was evaluated by measuring the sheet resistance before and after the annealing treatment. The thickness of the TiN film was all set to 10 nm except for Example 4.
　実施例１～４の各プロセス条件、すなわち、プロセス温度、プロセス圧力、各ガス流量、印加する高周波電力、膜厚またはプロセス時間は、以下の通りである（図４参照）。 The process conditions of Examples 1 to 4, ie, process temperature, process pressure, gas flow rate, applied high frequency power, film thickness, or process time are as follows (see FIG. 4).
［実施例１］
　成膜時　　　　：５５０℃、６６７Ｐａ、
　　　　　　　　　ＴｉＣｌ４／Ａｒ／Ｈ２／Ｎ２
　　　　　　　　　　＝１２／１６００／４０００／２００ｓｃｃｍ、
　　　　　　　　　８００Ｗ、１０ｎｍ（標準）
　プラズマ窒化時：５５０℃、６６７Ｐａ、
　　　　　　　　　Ａｒ／Ｈ２／ＮＨ３
　　　　　　　　　　＝１６００／２０００／１５００ｓｃｃｍ
　　　　　　　　　８００Ｗ、３０ｓｅｃ
［実施例２］
　成膜時　　　　：実施例１と同じ
　プラズマ窒化時：プロセス時間を１５ｓｅｃに短くした以外は実施例１
　　　　　　　　　と同じ
［実施例３］
　成膜時　　　　：プロセス圧力を４００Ｐａに低くした以外は実施例１
　　　　　　　　　と同じ
　プラズマ窒化時：実施例１と同じ
［実施例４］
　成膜時　　　　：膜厚を２ｎｍに薄く設定した以外は実施例１と同じ
　プラズマ窒化時：実施例１と同じ [Example 1]
During film formation: 550 ° C., 667 Pa,
TiCl 4 / Ar / H 2 / N 2
= 12/1600/4000/200 sccm,
800W, 10nm (standard)
During plasma nitriding: 550 ° C., 667 Pa,
Ar / H 2 / NH 3
= 1600/2000 / 1500sccm
800W, 30sec
[Example 2]
During film formation: Same as Example 1 Plasma nitridation: Example 1 except that the process time was shortened to 15 sec.
Same as Example 3
During film formation: Example 1 except that the process pressure was lowered to 400 Pa
Same as in plasma nitriding: same as Example 1 [Example 4]
During film formation: Same as Example 1 except that the film thickness was set to 2 nm. Plasma nitridation: Same as Example 1
　比較例１～３（プラズマ窒化処理は無し）の各プロセス条件、すなわち、プロセス温度、プロセス圧力、各ガス流量、印加する高周波電力、膜厚は以下の通りである（図４参照）。 Process conditions of Comparative Examples 1 to 3 (no plasma nitriding treatment), that is, process temperature, process pressure, gas flow rate, applied high frequency power, and film thickness are as follows (see FIG. 4).
［比較例１］
　成膜時　　　　：５５０℃、６６７Ｐａ、
　　　　　　　　　ＴｉＣｌ４／Ａｒ／Ｈ２／Ｎ２
　　　　　　　　　　＝１２／１６００／４０００／２００ｓｃｃｍ、
　　　　　　　　　８００Ｗ、１０ｎｍ（標準）
［比較例２］
　成膜時　　　　：ＴｉＣｌ４を２０ｓｃｃｍに増加した以外は比較例１
　　　　　　　　　と同じ
［比較例３］
　成膜時　　　　：プロセス圧力を４００Ｐａに低くした以外は比較例１
　　　　　　　　　と同じ [Comparative Example 1]
During film formation: 550 ° C., 667 Pa,
TiCl 4 / Ar / H 2 / N 2
= 12/1600/4000/200 sccm,
800W, 10nm (standard)
[Comparative Example 2]
During film formation: Comparative Example 1 except that TiCl 4 was increased to 20 sccm
Same as Comparative Example 3
During film formation: Comparative Example 1 except that the process pressure was lowered to 400 Pa
Same as
　比較例１～３及び実施例１～４における３０ｍｉｎアニール後のＲｓ増加ポイント率及びその評価が、図４に示されている。図４中の”×”はＮＧ（不良）を示し、”○”は良好を示す。 FIG. 4 shows the Rs increase point rate after 30 min annealing and its evaluation in Comparative Examples 1 to 3 and Examples 1 to 4. In FIG. 4, “x” indicates NG (defective), and “◯” indicates good.
　これによれば、比較例１～３のＲｓ増加ポイント率は、それぞれ１５．７％、９４．２％、３２．２％であり、ＴｉＮ膜のバリヤ性がそれ程良好ではなかった。これに対して、実施例１～４では、３．３％、８．３％、４．１％、０．０％であり、基準値である１０％よりもいずれも低く、バリヤ性が大幅に向上されていることが判った。前記した各Ｒｓ増加ポイント率（比較例２を除く）は、図６中にグラフとしても表されている。以上により、ＴｉＮ膜のバリヤ性を高めるためには、プラズマによるＴｉＮ膜の成膜後にプラズマ窒化処理を施すことが必要であることが判る。また、図６によれば、プラズマ窒化処理を長くする程、Ｒｓ増加ポイント率が低下してバリヤ性を高めることができると認められるが、後述するように、このＲｓ増加ポイント率は、プラズマ窒化時間が３０ｓｅｃ程度近傍をボトムとして、その後は上昇に転じるものと考えられる。 According to this, the Rs increase point rates of Comparative Examples 1 to 3 were 15.7%, 94.2%, and 32.2%, respectively, and the barrier properties of the TiN film were not so good. On the other hand, in Examples 1 to 4, they are 3.3%, 8.3%, 4.1%, and 0.0%, which are all lower than the standard value of 10%, and the barrier property is greatly increased. It was found that it was improved. Each Rs increase point rate (excluding Comparative Example 2) is also represented as a graph in FIG. From the above, it can be seen that in order to improve the barrier property of the TiN film, it is necessary to perform plasma nitriding after the formation of the TiN film by plasma. Further, according to FIG. 6, it can be recognized that the longer the plasma nitriding treatment, the lower the Rs increase point rate and the higher the barrier property. As will be described later, this Rs increase point rate is It is considered that the time is about 30 seconds and the bottom starts and then rises.
　いずれにしても、ＴｉＮ膜にプラズマ窒化処理を施すことにより、バリヤ性を向上させることができることが確認された。特に注目すべき点は、薄膜化の要請によりＴｉＮ膜の厚さも薄くする必要がある状況下で、実施例４のように、ＴｉＮ膜の膜厚が２ｎｍの場合でも高いバリヤ性を発揮できることである。すなわち、本発明方法によるバリヤ性の向上は、ＴｉＮ膜の膜厚が２～１０ｎｍの範囲において有効であることが判った。換言すれば、バリヤ層を２ｎｍまで薄くしても十分なバリヤ性が得られることが判った。 In any case, it was confirmed that the barrier property can be improved by subjecting the TiN film to plasma nitriding. Particularly noteworthy is that, under the circumstances where it is necessary to reduce the thickness of the TiN film due to the demand for thinning, it is possible to exhibit high barrier properties even when the thickness of the TiN film is 2 nm as in Example 4. is there. That is, it has been found that the improvement of the barrier property by the method of the present invention is effective when the thickness of the TiN film is 2 to 10 nm. In other words, it has been found that sufficient barrier properties can be obtained even if the barrier layer is thinned to 2 nm.
　また、同様に、本発明方法によるバリヤ性を発揮するためには、プラズマＴｉＮ膜を形成する薄膜形成工程におけるプロセス圧力が４００～６６７Ｐａの範囲内において有効であることが判った。 Similarly, it was found that the process pressure in the thin film forming process for forming the plasma TiN film is effective in the range of 400 to 667 Pa in order to exhibit the barrier property by the method of the present invention.
　また、比較例１～３では、プラズマを用いてＴｉＮ膜を成膜しているが、プラズマを用いないで熱エネルギーのみによってＴｉＮ膜を成膜する従来一般的に行われている成膜方法で形成したＴｉＮ膜についても評価を行った。その評価結果について説明する。 In Comparative Examples 1 to 3, the TiN film is formed using plasma. However, the TiN film is formed only by thermal energy without using plasma. The formed TiN film was also evaluated. The evaluation result will be described.
　ここでは、シリコン基板上に、ＴｉＮ膜を形成するためにプラズマを用いず、熱ＣＶＤ法或いはＳＦＤ法によりＴｉＮ膜を形成してバリヤ層として、これにプラズマを用いない、いわゆるプラズマレスの、熱によるＮＨ３　窒化処理を施し、更にＴｉＮ膜上にスパッタによりＣｕ膜を形成してサンプルとした。ここでは、プロセス温度や膜厚を変えたりして、比較例４～７の４個のサンプルを作った。これらのサンプルに、４００℃、１０Ｔｏｒｒ（１３３３Ｐａ）のＡｒ雰囲気中で３０ｍｉｎのアニール処理が施された。そして、このアニール処理の前後のシート抵抗を先の評価実験のように測定して、バリヤ性の評価が行われた。この時の結果が図５に示されている。 Here, a plasma is not used to form a TiN film on a silicon substrate, a TiN film is formed by a thermal CVD method or SFD method as a barrier layer, and plasma is not used for this. The sample was subjected to NH 3 nitridation treatment according to, and a Cu film was further formed on the TiN film by sputtering. Here, four samples of Comparative Examples 4 to 7 were made by changing the process temperature and film thickness. These samples were annealed for 30 minutes in an Ar atmosphere at 400 ° C. and 10 Torr (1333 Pa). Then, the sheet resistance before and after the annealing treatment was measured as in the previous evaluation experiment, and the barrier property was evaluated. The result at this time is shown in FIG.
　比較例４～７の各プロセス条件、すなわち、プロセス温度、プロセス圧力、各ガスの流量、膜厚等は、以下の通りである。 The process conditions of Comparative Examples 4 to 7, that is, process temperature, process pressure, flow rate of each gas, film thickness, etc. are as follows.
［比較例４］
　成膜時　　　　：６５０℃、６６７Ｐａ、
　　　　　　　　　ＴｉＣｌ４／ＮＨ３／Ｎ２＝６０／６０／１００ｓｃｃｍ、
　　　　　　　　　１０ｎｍ
（成膜後の窒化　：６５０℃、６６７Ｐａ、
　　　　　　　　　ＮＨ３／Ｎ２＝２０００／５００ｓｃｃｍ、
　　　　　　　　　２５ｓｅｃ
［比較例５］
　成膜時　　　　：プロセス温度を５５０℃に低下させた以外は比較例４
　　　　　　　　　と同じ
　成膜後の窒化　：プロセス温度を５５０℃に低下させた以外は比較例４
　　　　　　　　　と同じ
［比較例６］（ＳＦＤ成膜）
　成膜時　　　　：５５０℃、２６０Ｐａ、
　　　　　　　　　ＴｉＣｌ４／ＮＨ３／Ｎ２＝６０／６０／３４０ｓｃｃｍ、
　窒化時　　　　：５５０℃、２６０Ｐａ、
　　　　　　　　　ＮＨ３／Ｎ２＝４５００／４００ｓｃｃｍ、
　　　　　　　　　１０サイクル、膜厚は１０ｎｍ
［比較例７］（ＳＦＤ成膜）
　成膜時　　　　：比較例６と同じ、
　窒化時　　　　：２サイクル、膜厚は２ｎｍである以外は比較例６と同じ [Comparative Example 4]
During film formation: 650 ° C., 667 Pa,
TiCl 4 / NH 3 / N 2 = 60/60/100 sccm,
10nm
(Nitriding after film formation: 650 ° C., 667 Pa,
NH 3 / N 2 = 2000/500 sccm,
25 sec
[Comparative Example 5]
During film formation: Comparative Example 4 except that the process temperature was lowered to 550 ° C
Same as nitriding after film formation: Comparative Example 4 except that the process temperature was lowered to 550 ° C
Same as Comparative Example 6 (SFD film formation)
During film formation: 550 ° C., 260 Pa,
TiCl 4 / NH 3 / N 2 = 60/60/340 sccm,
During nitriding: 550 ° C., 260 Pa,
NH 3 / N 2 = 4500/400 sccm,
10 cycles, film thickness is 10nm
[Comparative Example 7] (SFD film formation)
During film formation: Same as Comparative Example 6,
During nitriding: the same as Comparative Example 6 except that 2 cycles and the film thickness is 2 nm
　ここで、ＳＦＤ成膜とは、前記した各ガス流量を流しつつデポジション（堆積）と窒化とを交互に繰り返し行って薄膜を複数層に亘って積層する成膜方法であり、デポジションと窒化とで１サイクルである。 Here, the SFD film formation is a film formation method in which deposition (deposition) and nitridation are alternately repeated while flowing each gas flow rate, and a thin film is laminated over a plurality of layers. And one cycle.
　図５に示すように、比較例４～７のＲｓポイント増加率は、それぞれ４．１％、３．３％、５．０％、２８．９％であった。ここで比較例４～６では、従来一般的に用いられていた方法が採用され、且つ、従来方法で採用されていたＴｉＮ膜の膜厚と同様の膜厚である１０ｎｍの膜厚が採用されていた。そして、これらの場合には、基準値である１０％よりもいずれも低くて良好な結果が得られた。しかしながら、比較例７のように膜厚を２ｎｍに薄く設定すると、Ｒｓ増加ポイント率は２８．９％まで大幅に増加して、バリヤ性が低下してしまって好ましくなかった。この点、前述したように、図４中の実施例４のように本発明方法によれば、膜厚を２ｎｍまで薄くしたとしても、バリヤ性は十分に高く維持される。すなわち、本実験結果より、本発明方法の有効性を確認することができた。 As shown in FIG. 5, the Rs point increase rates of Comparative Examples 4 to 7 were 4.1%, 3.3%, 5.0%, and 28.9%, respectively. Here, in Comparative Examples 4 to 6, a method generally used in the past is adopted, and a film thickness of 10 nm which is the same as the thickness of the TiN film employed in the conventional method is adopted. It was. In these cases, good results were obtained, both lower than the reference value of 10%. However, when the film thickness was set as thin as 2 nm as in Comparative Example 7, the Rs increase point rate was significantly increased to 28.9%, and the barrier property was lowered, which was not preferable. In this regard, as described above, according to the method of the present invention as in Example 4 in FIG. 4, even if the film thickness is reduced to 2 nm, the barrier property is maintained sufficiently high. That is, the effectiveness of the method of the present invention could be confirmed from the results of this experiment.
＜膜の抵抗（Ｒｓ）の評価＞
　ところで、前述したように、バリヤ性が良好であっても、プラズマ窒化処理の結果、比抵抗が過度に増加してしまえば、バリヤ層として採用することはできない。そこで、プラズマ窒化時間に対するＲｓ値の依存性について実験を行った。その評価結果について説明する。 <Evaluation of film resistance (Rs)>
As described above, even if the barrier property is good, if the specific resistance increases excessively as a result of the plasma nitriding treatment, it cannot be adopted as a barrier layer. Therefore, an experiment was conducted on the dependence of the Rs value on the plasma nitriding time. The evaluation result will be described.
　図７は、プラズマ窒化時間と膜のシート抵抗（Ｒｓ）との関係を示すグラフである。ここでは、本発明方法の実施例１として記載したプロセス条件下でプラズマＣＶＤ法によりＴｉＮ膜を形成してバリヤ層とし、このＴｉＮ膜に実施例１として記載したプロセス条件下で時間を変えつつプラズマ窒化処理を行った時のバリヤ層のＲｓ値が測定された。このようにＴｉＮ膜に窒化処理を施す理由は、膜中に残留しているＣｌ原子を除去して、ＴｉＮ膜の膜質を向上させるためである。ここでは、膜厚を１０ｎｍで統一している。このため、シート抵抗Ｒｓを比較することは、膜の比抵抗を比較することと同義である。 FIG. 7 is a graph showing the relationship between the plasma nitriding time and the sheet resistance (Rs) of the film. Here, a TiN film is formed by plasma CVD under the process conditions described as Example 1 of the method of the present invention to form a barrier layer, and plasma is generated while changing the time under the process conditions described as Example 1 on this TiN film. The Rs value of the barrier layer when nitriding was performed was measured. The reason for nitriding the TiN film in this way is to remove Cl atoms remaining in the film and improve the quality of the TiN film. Here, the film thickness is unified at 10 nm. For this reason, comparing the sheet resistance Rs is synonymous with comparing the specific resistances of the films.
　図７に示すように、ＴｉＮ膜にプラズマ窒化処理が施されると、Ｒｓ値は当初は減少してゆくが、１５ｓｅｃ程度でボトムになる。そして、そのままボトム状態が３０ｓｅｃ程度まで続いて、その後はＲｓ値は上昇に転じ、窒化時間の経過と共に更に上昇して行く傾向が認められる（すなわち、下に凸の特性曲線を描く）。従って、窒化工程におけるプラズマ窒化処理の時間は、５～６０ｓｅｃの範囲が望ましい。この時間が５ｓｅｃより短いと、Ｒｓ値が大きいのみならず、バリヤ性も十分に発揮することができない。一方、この時間が６０ｓｅｃよりも長いと、Ｒｓ値が過度に大きくなって、やはり好ましくない。また、この場合、以下に示すように、図６に示すグラフも下に凸の特性曲線を描くと予想され、すなわち、バリヤ性も劣化すると推察される。 As shown in FIG. 7, when the plasma nitriding process is performed on the TiN film, the Rs value initially decreases, but reaches the bottom in about 15 seconds. Then, the bottom state continues to about 30 seconds, and thereafter, the Rs value starts to increase, and a tendency to further increase as the nitriding time elapses (that is, a downward characteristic curve is drawn). Therefore, the plasma nitriding time in the nitriding step is preferably in the range of 5 to 60 seconds. If this time is shorter than 5 sec, not only the Rs value is large, but also the barrier property cannot be sufficiently exhibited. On the other hand, if this time is longer than 60 sec, the Rs value becomes excessively large, which is not preferable. In this case, as shown below, the graph shown in FIG. 6 is also expected to draw a downward characteristic curve, that is, it is presumed that the barrier property is also deteriorated.
　すなわち、周知のように、比抵抗はＴｉＮよりもＴｉの方が大きいので、プラズマ窒化処理を行ってＴｉＮ化が促進されれば、その処理時間が長くなるにつれて次第にシート抵抗（比抵抗）も小さくなり（図７の左半分を参照）、それに伴ってバリヤ性も向上していく（図６参照）。一方、更にプラズマ窒化処理が行われてその処理時間が長くなり過ぎると、シート抵抗（比抵抗）が増加に転じてしまう（図７の右半分を参照）。このシート抵抗増加の理由は、ＴｉＮ膜の表面ラフネスの増加や、膜中における不純物の増加による膜質の劣化、であると考えられる。そして、膜質が劣化すると、バリヤ性も劣化するものと予想される。従って、図６中においてプラズマ窒化時間を更に長くすると、前述したようにＲｓ増加ポイント率が上昇に転じるのである。 That is, as is well known, since Ti has a larger specific resistance than TiN, if plasma nitriding is performed to promote TiN conversion, the sheet resistance (specific resistance) gradually decreases as the processing time increases. (Refer to the left half of FIG. 7), and the barrier property is improved accordingly (see FIG. 6). On the other hand, if plasma nitriding is further performed and the processing time becomes too long, the sheet resistance (specific resistance) starts to increase (see the right half of FIG. 7). The reason for this increase in sheet resistance is thought to be an increase in the surface roughness of the TiN film and a deterioration in film quality due to an increase in impurities in the film. And when film quality deteriorates, barrier property is also expected to deteriorate. Therefore, when the plasma nitriding time is further increased in FIG. 6, the Rs increase point rate starts to increase as described above.
　以上の結果より、プラズマ窒化処理の時間について、より好ましい範囲は１０～４０ｓｅｃの範囲内である。更に好ましい範囲は、曲線のボトム部分である１５～３０ｓｅｃの範囲内である。 From the above results, a more preferable range of the plasma nitriding time is in the range of 10 to 40 sec. A more preferable range is within the range of 15 to 30 sec which is the bottom portion of the curve.
　尚、前記実施形態では、プラズマ用ガスとしてＡｒガスが用いられたが、これに限定されない。Ｈｅ、Ｎｅ等の他の希ガスが用いられてもよい。また、プラズマ窒化工程における窒化ガスとしてＮＨ３ガスが用いられたが、これに限定されない。Ｎ２ガス、ヒドラジン（Ｈ２Ｎ－ＮＨ２）ガス、モノメチルヒドラジン（ＣＨ３－ＮＨ－ＮＨ２）ガス等が用いられてもよい。 In the embodiment, Ar gas is used as the plasma gas, but the present invention is not limited to this. Other noble gases such as He and Ne may be used. Further, although NH 3 gas is used as the nitriding gas in the plasma nitriding step, the present invention is not limited to this. N 2 gas, hydrazine (H 2 N—NH 2 ) gas, monomethyl hydrazine (CH 3 —NH—NH 2 ) gas, or the like may be used.
　更に、ここでは、原料ガスとしてＴｉＣｌ４ガスが用いられたが、これに限定されない。ＴＤＭＡＴ（Ｔｉ［Ｎ（ＣＨ３）２］４：テトラキスジメチルアミノチタン）ガスやＴＤＥＡＴ（Ｔｉ［Ｎ（Ｃ２Ｈ５）２］４：テトラキスジエチルアミノチタン）ガス等が用いられてもよい。 Further, here, TiCl 4 gas is used as the source gas, but the present invention is not limited to this. TDMAT (Ti [N (CH 3 ) 2 ] 4 : tetrakisdimethylaminotitanium) gas, TDEAT (Ti [N (C 2 H 5 ) 2 ] 4 : tetrakisdiethylaminotitanium) gas, or the like may be used.
　また、ここでは、被処理体として半導体ウエハが例として説明されたが、当該半導体ウエハには、シリコン基板やＧａＡｓ、ＳｉＣ、ＧａＮなどの化合物半導体基板が含まれる。更には、これらの基板に限定されず、液晶表示装置に用いられるガラス基板やセラミック基板等にも本発明は適用可能である。 Also, here, a semiconductor wafer has been described as an example of the object to be processed, but the semiconductor wafer includes a silicon substrate or a compound semiconductor substrate such as GaAs, SiC, GaN. Furthermore, the present invention is not limited to these substrates, and the present invention can also be applied to glass substrates, ceramic substrates, and the like used in liquid crystal display devices.

Claims (14)

  1. 　凹部を有する絶縁層が表面に形成された被処理体に対して薄膜を形成する成膜方法において、
    　前記凹部内の表面を含む前記被処理体の表面に、プラズマＣＶＤ法を用いて、窒化チタン膜の薄膜を形成する薄膜形成工程と、
    　窒化ガスの存在下で、プラズマを用いた窒化処理を行うことにより、前記薄膜を窒化する窒化工程と、
    を備えたことを特徴とする成膜方法。     In a film forming method for forming a thin film on an object having an insulating layer having a recess formed on a surface thereof,
    A thin film forming step of forming a thin film of a titanium nitride film on the surface of the object to be processed including the surface in the recess using a plasma CVD method;
    A nitriding step of nitriding the thin film by performing a nitriding treatment using plasma in the presence of a nitriding gas;
    A film forming method comprising:
  2. 　前記薄膜形成工程では、原料ガスとして、ＴｉＣｌ４ ガスが用いられる
    ことを特徴とする請求項１に記載の成膜方法。     2. The film forming method according to claim 1, wherein TiCl 4 gas is used as a source gas in the thin film forming step.
  3. 　前記薄膜形成工程において、前期凹部内の底部に形成される前記薄膜の厚さは、２～１０ｎｍの範囲内である
    ことを特徴とする請求項１または２に記載の成膜方法。     The film forming method according to claim 1 or 2, wherein, in the thin film forming step, the thickness of the thin film formed on the bottom of the first recess is in the range of 2 to 10 nm.
  4. 　前記窒化工程におけるプロセス時間は、５～６０ｓｅｃの範囲内である
    ことを特徴とする請求項１乃至３のいずれかに記載の成膜方法。     4. The film forming method according to claim 1, wherein a process time in the nitriding step is in a range of 5 to 60 sec.
  5. 　前記薄膜形成工程におけるプロセス圧力は、４００～６６７Ｐａの範囲内である
    ことを特徴とする請求項１乃至４のいずれかに記載の成膜方法。     The film forming method according to any one of claims 1 to 4, wherein a process pressure in the thin film forming step is in a range of 400 to 667 Pa.
  6. 　前記窒化工程で用いられる前記窒化ガスは、ＮＨ３ ガスである
    ことを特徴とする請求項１乃至５のいずれかに記載の成膜方法。     The film forming method according to claim 1, wherein the nitriding gas used in the nitriding step is NH 3 gas.
  7. 　前記薄膜形成工程の前工程として、前記凹部内の表面を含む前記被処理体に、プラズマＣＶＤ法を用いて、チタン膜よりなる薄膜を形成するチタン膜形成工程が行われる
    ことを特徴とする請求項１乃至６のいずれかに記載の成膜方法。     The titanium film forming step of forming a thin film made of a titanium film on the object to be processed including the surface in the concave portion by using a plasma CVD method is performed as a pre-process of the thin film forming step. Item 7. The film forming method according to any one of Items 1 to 6.
  8. 　前記チタン膜形成工程と前記薄膜形成工程と前記窒化工程とは、同一の処理容器内で連続的に行われる
    ことを特徴とする請求項７に記載の成膜方法。     The film forming method according to claim 7, wherein the titanium film forming step, the thin film forming step, and the nitriding step are continuously performed in the same processing vessel.
  9. 　前記チタン膜形成工程の後であって前記薄膜形成工程の前に、前記チタン膜よりなる薄膜を窒化ガスの存在下でプラズマを用いて窒化するチタン膜窒化工程が行われる
    ことを特徴とする請求項７に記載の成膜方法。     The titanium film nitriding step is performed after the titanium film forming step and before the thin film forming step, in which a thin film made of the titanium film is nitrided using plasma in the presence of a nitriding gas. Item 8. The film forming method according to Item 7.
  10. 　前記チタン膜形成工程と前記チタン膜窒化工程と前記薄膜形成工程と前記窒化工程とは、同一の処理容器内で連続的に行われる
    ことを特徴とする請求項９に記載の成膜方法。     The film forming method according to claim 9, wherein the titanium film forming step, the titanium film nitriding step, the thin film forming step, and the nitriding step are continuously performed in the same processing container.
  11. 　前記窒化工程の後に、前記凹部内を導電性材料で埋め込む埋め込み工程が行なわれる
    ことを特徴とする請求項１乃至１０のいずれかに記載の成膜方法。     The film forming method according to claim 1, wherein after the nitriding step, a burying step of filling the concave portion with a conductive material is performed.
  12. 　前記凹部の内径又は幅は、５０ｎｍ以下に設定されている
    ことを特徴とする請求項１乃至１１のいずれかに記載の成膜方法。     The film forming method according to claim 1, wherein an inner diameter or a width of the recess is set to 50 nm or less.
  13. 　凹部を有する絶縁層が表面に形成された被処理体に対して薄膜を形成するプラズマ処理装置において、
    　真空排気が可能になされた処理容器と、
    　前記処理容器内に配置され、前記被処理体を載置すると共に下部電極として機能する載置台と、
    　前記被処理体を加熱する加熱手段と、
    　前記処理容器内に配置され、当該処理容器内へ所定のガスを導入すると共に上部電極として機能するガス導入手段と、
    　前記ガス導入手段へ前記所定のガスを供給するガス供給手段と、
    　前記載置台と前記ガス導入手段との間にプラズマを形成するプラズマ形成手段と、
    　請求項１乃至１２のいずれかに記載の成膜方法を実施するように前記各手段を制御する制御部と、
    を備えたことを特徴とするプラズマ処理装置。     In a plasma processing apparatus for forming a thin film on a target object having an insulating layer having a recess formed on a surface thereof,
    A processing vessel that can be evacuated;
    A mounting table disposed in the processing container and mounting the object to be processed and functioning as a lower electrode;
    Heating means for heating the object to be processed;
    A gas introduction means which is arranged in the processing container and introduces a predetermined gas into the processing container and functions as an upper electrode;
    Gas supply means for supplying the predetermined gas to the gas introduction means;
    Plasma forming means for forming plasma between the mounting table and the gas introducing means;
    A control unit that controls each of the units so as to perform the film forming method according to claim 1;
    A plasma processing apparatus comprising:
  14. 　凹部を有する絶縁層が表面に形成された被処理体に対して薄膜を形成するプラズマ処理装置であって、
    　真空排気が可能になされた処理容器と、
    　前記処理容器内に配置され、前記被処理体を載置すると共に下部電極として機能する載置台と、
    　前記被処理体を加熱する加熱手段と、
    　前記処理容器内に配置され、当該処理容器内へ所定のガスを導入すると共に上部電極として機能するガス導入手段と、
    　前記ガス導入手段へ前記所定のガスを供給するガス供給手段と、
    　前記載置台と前記ガス導入手段との間にプラズマを形成するプラズマ形成手段と、
    を備えたプラズマ処理装置を制御して、請求項１乃至１２のいずれかに記載の成膜方法を実施する
    コンピュータ読み取り可能なプログラム
    を記憶することを特徴とする記憶媒体。     A plasma processing apparatus for forming a thin film on an object having an insulating layer having a recess formed on a surface thereof,
    A processing vessel that can be evacuated;
    A mounting table disposed in the processing container and mounting the object to be processed and functioning as a lower electrode;
    Heating means for heating the object to be processed;
    A gas introduction means which is arranged in the processing container and introduces a predetermined gas into the processing container and functions as an upper electrode;
    Gas supply means for supplying the predetermined gas to the gas introduction means;
    Plasma forming means for forming plasma between the mounting table and the gas introducing means;
    13. A storage medium for storing a computer-readable program for controlling a plasma processing apparatus comprising: a film forming method according to claim 1.
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