KR100224651B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100224651B1 KR100224651B1 KR1019920011636A KR920011636A KR100224651B1 KR 100224651 B1 KR100224651 B1 KR 100224651B1 KR 1019920011636 A KR1019920011636 A KR 1019920011636A KR 920011636 A KR920011636 A KR 920011636A KR 100224651 B1 KR100224651 B1 KR 100224651B1
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- field region
- planarization film
- film
- semiconductor device
- silicon substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Abstract
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 반도체장치의 소자간 분리방법에 있어서, 실리콘기판상에 패드산화막을 형성한 후, 필드 영역의 상기 실리콘기판을 트랜치 식각하는 공정; 식각결합을 보수하기 위한 보수산화막을 형성하는 공정; 트랜치부위를 채우기 위하여 평탄성막을 침적형성하는 공정; 상기 평탄성막을 평탄화하기 위한 열처리공정; 필드영역에만 상기 평탄성막을 채우는 사진식각공정을 구비하여 이루어진 것을 특징으로 한다. 따라서 상기한 본 발명의 방법에 의하면 필드영역으로 인한 피복단차성을 크게 감소시킬 수 있고, 실리콘 기판의 식각손상을 보수하여 누설전류상의 전기적 특성을 향상시킬 뿐아니라 버즈비크현상을 제거하여 반도체장치의 고집적에 유리한 이점이있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of separating devices between semiconductor devices, comprising: forming a pad oxide film on a silicon substrate and then trench etching the silicon substrate in a field region; Forming a repair oxide film for repairing the etch bond; Depositing a planarization film to fill trench portions; A heat treatment process for planarizing the planarization film; And a photolithography process of filling the planarization film only in the field region. Therefore, according to the method of the present invention, it is possible to greatly reduce the coating step due to the field region, and to repair the etching damage of the silicon substrate to improve the electrical characteristics of the leakage current, as well as to remove the phenomenon of the semiconductor device by removing the buzz beak phenomenon. There is a favorable advantage to high integration.
Description
제1도 내지 제3도는 종래의 LOCOS소자분리방법을 도시한 공정순서 단면도.1 to 3 are cross-sectional views of a process sequence showing a conventional LOCOS device isolation method.
제4도 내지 제8도는 본 발명의 바람직한 일실시예의 소자분리방법을 도시한 공정순서 단면도.4 to 8 are cross-sectional views of a process sequence showing a device isolation method of a preferred embodiment of the present invention.
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 트랜치식각 및 가능한 막의 리필링(refilling)기술을 이용한 소자분리장치방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a device isolation device method using trench etching and possible refilling of a film.
종래의 소자분리기술은 LOCOS(Local Oxidation of Sillcon)또는 SEPOX(Seletive Polysilicon Oxidatipn)등의 산화공정르 이용한 분리기법이 주로 이용되어 왔으나, LOCOS류의 소자분리기술로는 비즈비크(Bird's beak)현상, 응력에 의한 결정결함, 이온주입된 불순물 재분포등의 금본적으로 해결하지 못하고 있다.Conventional device isolation techniques have mainly used a separation method using an oxidation process such as LOCOS (Local Oxidation of Sillcon) or SEPOX (Seletive Polysilicon Oxidatipn). Crystal defects caused by stress and redistribution of impurities implanted with ions have not been solved in principle.
첨부된 도면 제1도 내지 제3도에 종래방법에 의한 상기의 LOCOS소자분리방법에 있어서 제조공정에 따른 형상단면을 순서적으로 도시하고 있으며, 상기한 도면을 참조하여 종래방법을 상세히 설명하기로 한다.In Figures 1 to 3 of the accompanying drawings, in the LOCOS device isolation method according to the conventional method, the cross-sectional view according to the manufacturing process is shown in sequence, and the conventional method will be described in detail with reference to the drawings. do.
먼저, 실리콘기판(10)상에 패드산화막(11)과 질화막(12)을 순차적으로 적층형성(제1도)한 다음, 필드영역위의 상기 질화막(12)을 사진식각공정으로 패러딩하여 제거시킨다.First, the pad oxide film 11 and the nitride film 12 are sequentially stacked on the silicon substrate 10 (FIG. 1), and then the nitride film 12 on the field region is parametrically removed by a photolithography process. Let's do it.
이때, 식각정도의 불일치로 인해 패드산화막(11)의 일부가 동시에 식각ㄷ리수 있다. 이어서 반전채널층을 저지하기 위한 채널저지이온을 필등여역에 이온주입(13)한다(제2도).At this time, a part of the pad oxide film 11 may be simultaneously etched due to the inconsistency of the etching degree. Subsequently, ion implantation 13 of channel blocking ions for blocking the inversion channel layer is carried out into the fill region (FIG. 2).
그다음, 상기 필드영역의 기판실리콘을 산화시켜 필드산화막(14)을 형성한다(제3도).Then, the substrate silicon in the field region is oxidized to form a field oxide film 14 (FIG. 3).
상기와 같은 종래 LOCOS소자분리방법은 반도체장치가 써브미크론 소자기술로 발전하면서 여러가지 결점을 나타내고 있는데, 그 결점으로는 패드산화막과 질화막응력에 의해 산화공정시 기판실리콘에 결정결함이 발생하고, 고온장시간 산화에 의해 기판실리콘내의 불순물 분포가 변화되어 소자으 전기적 특성을 약화시키며, 특히 액티브영역으로 질화막밑의 패드산화막이 산화되는 버즈비크(bird's beak)현상에 의해 유효소자면적을 감소시키므로 반되체장치의 고집적화에 큰 문제를 야기시키고 있다.The conventional LOCOS device isolation method described above exhibits various drawbacks as the semiconductor device develops to submicron device technology. The defects include crystal defects in the substrate silicon during the oxidation process due to pad oxide film and nitride film stress, and high temperature and long time. Oxidation changes the impurity distribution in the substrate silicon, weakening the electrical characteristics of the device, and in particular, the effective device area is reduced due to the bird's beak phenomenon in which the pad oxide film under the nitride film is oxidized to the active region. It is causing a big problem in high integration.
따라서 본 발명은 종래의 문제인 단자 피복성과 전기적 특성을 개선하고 유효소자면적을 증가시킬 수 있는 소자분리방법을 제고하는데 그 목적이 있다.Accordingly, an object of the present invention is to improve a device isolation method capable of improving terminal coverage and electrical characteristics and increasing an effective device area, which is a conventional problem.
상기한 본 발명의 목적을 달성하기 위한 바람직한 소자분리방법은 실리콘기판상에 패드산화막을 형성한 후, 필드영역의 상기 실리콘기판을 트랜치 식각하는 공정, 식각결함을 보수하기 위하여 평탄성막을 형성하는 공정, 트랜치부위를 채우기 위하여 평탄성막을 침적형성하는 공정, 상기 평탄성막을 평탄화하기 위한 열처리공정, 필드영역에만 상기 평탄성막을 채우는 사진식각공정을 구비하여 이루어진 것을 특징으로 한다.A preferred device isolation method for achieving the object of the present invention is to form a pad oxide film on a silicon substrate, and then trench etching the silicon substrate in the field region, forming a flat film to repair the etching defects, And depositing a planarization film to fill the trench, a heat treatment process to planarize the planarization film, and a photolithography process of filling the planarization film only in the field region.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제4도 내지 제8도를 본 발명의 방법에 의한 반되체 장치의 소자분리방법을 도시하고 있다.4 to 8 show a device separation method of the half body device according to the method of the present invention.
먼저, 실리콘기판(200)상에 패드산화막(21)을 성장시키고, 감광막(22)을 도포하여 사진공정으로 필드영역을 패터닝한다(제4도). 이어서, 상기 감광막패턴(22')을 식각마스크로 하여 필드영역의 실리콘기판(200)을 트랜치 식각한다(제5도). 상기 트랜치 식각후 실리콘기판(200)에 유발된 식각손상을 보수하기 위하여 약100Å∼300Å정도의 보수산화막(23)을 건식산화방법으로 형성하고, 이어서, 필드영역의 트랜치부위를 채우기 위해 BPSG(Borophosphorous Sillicte Glass) 또는 PSG(Phosphoerons Sillcste Glass)등의 평탄성막을 침적형성한 다음 열처리공정을 통하여 상기 평탄성막을 리플로우(Reflow)시켜 평탄화막(24)을 형성시킨다(제6도). 그다음 액티브영역상의 상기 보수산화막(23)으로부터 대략 1,000Å정도 두께의 평탄성막(24')을 식각 최종점(end point)으로 하여 상기 평탄화막(24)을 에치백한 다음, 필드영역을 한정한 감광막패턴(25)을 형성한다, 이때, 상기 감광막패턴은 상기 필드영역의 트랜치식각을 하기 위해 사용된 필드영역 패턴마스크의 역패턴마스크를 사용하여 형성된다. 또, 상기 에치백공정시 액티브영역의 실리콘기판(200)을 식각최종점으로 하여 전면 에치백할 수 도 있으며, 이 경우에는 후속공정의 필요없이 소자분리공정이 완성될 것이다(제7도). 이어서 상기 감광패턴(25)을 식각마스크로 하여 필드영역외의 상기 평탄성막(24')과 보수산화막(23)을 제거하여 본 발명의 소자분리가 완성된다(제8도).First, the pad oxide film 21 is grown on the silicon substrate 200, and the photoresist film 22 is applied to pattern the field region by a photographic process (FIG. 4). Subsequently, the silicon substrate 200 in the field region is trench-etched using the photoresist pattern 22 'as an etching mask (FIG. 5). In order to repair the etching damage caused to the silicon substrate 200 after the trench etching, a repair oxidation film 23 having a thickness of about 100 to 300 Å is formed by a dry oxidation method, and then BPSG (Borophosphorous) is used to fill the trench in the field region. A flattening film such as silica glass or PSG (Phosphoerons Sillcste Glass) is deposited to form a flattening film 24 by reflowing the flattening film through a heat treatment process (FIG. 6). Next, the planarization film 24 is etched back from the repair oxide film 23 on the active region with the planarization film 24 'having a thickness of about 1,000 ms as the etch end point, and then the field region is defined. A photoresist pattern 25 is formed, wherein the photoresist pattern is formed using an inverse pattern mask of a field region pattern mask used for trench etching the field region. Further, during the etch back process, the entire surface may be etched back using the silicon substrate 200 in the active region as an etching end point, and in this case, the device isolation process may be completed without the need for a subsequent process (FIG. 7). Subsequently, the planarization film 24 ′ and the repair oxide film 23 outside the field region are removed using the photosensitive pattern 25 as an etching mask to complete device isolation of the present invention (FIG. 8).
따라서 상기한 본 발명의 방법에 위하면 필드영역으로 인한 피복차단성을 크게 감소시킬 수 있고, 실리콘기판의 식각손상을 보수하여 누설전류등의 전기적 특성을 향상시킬 뿐만아니라 버즈비크현상을 제거하여 반도체장치의 고집적에 유리한 이점이 있다.Therefore, according to the method of the present invention, it is possible to greatly reduce the coating barrier property due to the field region, and to repair the etch damage of the silicon substrate to improve the electrical characteristics such as leakage current and to remove the phenomenon of buzz beak semiconductor. There is an advantage to the high integration of the device.
Claims (5)
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KR1019920011636A KR100224651B1 (en) | 1992-06-30 | 1992-06-30 | Method of manufacturing semiconductor device |
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KR1019920011636A KR100224651B1 (en) | 1992-06-30 | 1992-06-30 | Method of manufacturing semiconductor device |
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KR940001354A KR940001354A (en) | 1994-01-11 |
KR100224651B1 true KR100224651B1 (en) | 1999-10-15 |
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KR1019920011636A KR100224651B1 (en) | 1992-06-30 | 1992-06-30 | Method of manufacturing semiconductor device |
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