KR0142984B1 - Method of forming the elements isolation film on the semiconductor device - Google Patents

Method of forming the elements isolation film on the semiconductor device

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Publication number
KR0142984B1
KR0142984B1 KR1019950004885A KR19950004885A KR0142984B1 KR 0142984 B1 KR0142984 B1 KR 0142984B1 KR 1019950004885 A KR1019950004885 A KR 1019950004885A KR 19950004885 A KR19950004885 A KR 19950004885A KR 0142984 B1 KR0142984 B1 KR 0142984B1
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South Korea
Prior art keywords
film
forming
trench
silicon substrate
sequentially
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KR1019950004885A
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Korean (ko)
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KR960035956A (en
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황준
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김주용
현대전자산업주식회사
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Priority to KR1019950004885A priority Critical patent/KR0142984B1/en
Publication of KR960035956A publication Critical patent/KR960035956A/en
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Publication of KR0142984B1 publication Critical patent/KR0142984B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

Abstract

본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, 단차를 감소시키기 위하여 실리콘기판에 소정깊이의 미세트랜치를 형성한 후 플로우특성이 양호한 물질을 증착하고 평탄화시켜 단차를 최소화시키므로써 소자의 평탄성을 향상시키며 활성영역의 크기를 증대시킬 수 있도록 한 반도체 소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and to form a fine trench of a predetermined depth in a silicon substrate in order to reduce the step difference, by depositing and planarizing a material having good flow characteristics to minimize the step level flatness of the device The present invention relates to a method for forming a device isolation film of a semiconductor device to improve and increase the size of an active region.

Description

반도체 소자의 소자분리막 형성방법Device Separating Method of Semiconductor Device

제1a내지 제1d도는 본 발명의 제1실시예를 설명하기 위한 소자의 단면도1A to 1D are cross-sectional views of elements for explaining the first embodiment of the present invention.

제2a내지 제2c도는 본 발명의 제2실시예를 설명하기 위한 소자의 단면도.2A to 2C are cross-sectional views of elements for explaining the second embodiment of the present invention.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1및11:실리콘기판 2:제1산화막1 and 11: silicon substrate 2: first oxide film

3,8및14:감광막 4및15:트랜치3, 8 and 14: photoresist 4 and 15: trench

5:제2산화막 6및13:질화막5: second oxide film 6 and 13: nitride film

7:BPSG막 12:산화막7: BPSG film 12: oxide film

16:TEOS막 17:채널스토퍼16: TEOS film 17: channel stopper

본 발명은 반도체 소자의 소자분리막 형성방벙에 관한 것으로, 특히 실리콘기판에 소정깊이의 미세트랜치(Trench)를 형성한 후 플로우(Flow)특성이 양호한 물질을 증착하고 평탄화시켜 단차(Topology)를 최소화시키므로써 소자의 평탄성을 향상시키며 활성영역 (Active region)의 크기를 증대시킬 수 있도록 한 반도체 소자의 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device. In particular, after forming a micro trench having a predetermined depth in a silicon substrate, a material having good flow characteristics is deposited and planarized to minimize topologies. The present invention relates to a method of forming a device isolation film of a semiconductor device capable of improving device flatness and increasing the size of an active region.

일반적으로 반도체 소자의 제조공정에서 소자와 소자 또는 주변지역과 메로미셀지역을 전기적으로 분리시키기 위하여 소자분리막을 형성한다.In general, in the fabrication process of a semiconductor device, a device isolation film is formed to electrically separate a device from a device, a peripheral region, and a melomicell region.

종래에는 이와같은 소자분리막을 LOCOS(Local Oxidation of Silicon)공정을 이용하거나 또는 실리콘기판에 트랜치를 형성시킨후 그 내부에 절연물질을 매몰시키는 공정을 이용하였는데, 상기 LOCOS공정에 의해 형성되는 소자분리막은 그 두께가 6000 내지 9000Å정도로 두껍게 형성되기 때문에 높은 단차를 갖는 메모리셀지역과 상대적으로 낮은 단차를 갖는 주변지역간의 단차가 더욱 커지게 되며, 이러한 문제는 소자의 평탄성을 악화시켜 후속 사진공정을 통한 패턴형성공정시 균일한 패턴의 형성을 어렵게 만든다. 또한 산화공정시 산화제가 활성영역쪽으로 침투되어 들어가 활성영역의 크기가 축소되는 단점이 있다.Conventionally, a device isolation film is used by using a local oxide of silicon (LOCOS) process or by forming a trench in a silicon substrate and then embedding an insulating material therein. The device isolation film formed by the LOCOS process is Since the thickness is thick, such as 6000 to 9000Å, the step height between the memory cell region having a high level and the surrounding area having a relatively low level becomes larger. During the forming process, it is difficult to form a uniform pattern. In addition, during the oxidation process, the oxidant penetrates into the active region and has a disadvantage in that the size of the active region is reduced.

따라서 본 발명은 실리콘기판에 소정깊이의 미세트랜치를 형성한 후 플로우특성이 양호한 물질을 증착하고 평탄화시켜 단차를 최소화시키르므써 상기한 단점을 해소할 수 있는 반도체 소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a method of forming a device isolation film for a semiconductor device which can solve the above-mentioned disadvantages by minimizing the step by forming a fine trench of a predetermined depth on a silicon substrate and depositing and planarizing a material having good flow characteristics. Its purpose is.

상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 소자분리막 형성방법은 실리콘기판상에 제1산화막 및 감광막을 순차적으로 형성한 후 소자분리마스크를 이용하여 상기 감광막을 패터닝하고, 패터닝된 상기 감광막을 마스크로 이용한 식각공정을 통해 노출된 부분의 상기 제1산화막 및 실리콘기판을 순차적으로 식각하여 상기 실리콘기판에 소정깊이의 트랜치를 형성시키는 단계와, 상기 단계로부터 상기 패터닝된 감광막 및 제1산화막을 순차적으로 제거하고 전체면에 제2산화막 및 질화막을 순차적으로 형성한 다음 상기 트랜치내부가 완전히 매몰되도록 전체상부면에 BPSG막을 증착하는 단계와, 상기 단계로부터 상기 BPSG막을 플로우시킨후 전체 상부면에 감광막을 도포하여 표면을 완전히 평탄화시키는 단계와, 상기 단계로부터 애치백공정으로 상기 감광막과 BPSG막을 제거하여 평탄화 시킨후 노출된 질화막과 제2산화막을 순차적으로 제거하는 단계로 이루어지는 것을 특징으로 하며, 다른 반도체 소자의 소자분리막형성방법은 실리콘기판상에 산화막, 질화막 및 감광막을 순차적으로 형성한 후 소자분리 마스크를 이용하여 상기 감광막을 패터닝하고, 패터닝된 상기 감광막을 마스크로 이용한 식각공정을 통해 노출된 부분의 상기 질화막, 산화막 및 실리콘기판을 순차적으로 식각하여 상기 실리콘기판에 소정깊이의 트랜치를 형성시키는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 제거하고 채널스톱이온주입공정을 실시하여 상기 트랜치주위의 실리콘기판에 채널 스토퍼를 형성한 다음 상기 트랜치내부가 완전히 매몰되도록 전체상부면에 TEOS막을 증착하는 단계와, 상기 단계로부터 전체상부면에 감광막을 도포하여 표면을 완전히 평탄화시킨 후 애치백공정으로 상기 감광막과 TEOS막을 제거하여 평탄화시키고 노출된 질화막 및 산화막을 순차적으로 제거하는 단계로 이루어지는 것을 특징으로 한다.In the method of forming a device isolation film of a semiconductor device according to the present invention for achieving the above object, after forming a first oxide film and a photoresist film sequentially on a silicon substrate and patterning the photoresist film by using a device isolation mask, the patterned photoresist film Sequentially etching the first oxide film and the silicon substrate of the exposed portion through an etching process using a mask as a mask to form a trench having a predetermined depth in the silicon substrate, and forming the patterned photoresist film and the first oxide film from the step. Sequentially removing the second oxide film and the nitride film on the entire surface, and then depositing a BPSG film on the entire upper surface of the trench to completely bury the inside of the trench; Applying a planar to completely flatten the surface, and from the step Removing the planarized film and the BPSG film, and then sequentially removing the exposed nitride film and the second oxide film. The method of forming an isolation layer of another semiconductor device includes an oxide film, a nitride film, and a photoresist film on a silicon substrate. After sequentially forming the patterned photoresist using an isolation mask, and subsequently etching the nitride film, the oxide film and the silicon substrate of the exposed portion by an etching process using the patterned photosensitive film as a mask to the silicon substrate Forming a trench having a predetermined depth, removing the patterned photoresist from the step, and performing a channel stop ion implantation process to form a channel stopper on the silicon substrate around the trench, and then completely buried the inside of the trench. Depositing a TEOS film on the surface, and Characterized in that from the aechi back process was completely flatten the surface by coating a photosensitive film on the entire upper surface formed of planarizing to remove the photosensitive film and the TEOS film and sequentially removing the exposed nitride film and the oxide film.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제1a 내지 제1d도는 본 발명의 제1실시예를 설명하기 위한 소자의 단면도로서,1A to 1D are cross-sectional views of devices for describing the first embodiment of the present invention.

제1a도는 실리콘기판(10)상에 제1산화막(2)을 150내지 250Å의 두께로 형성하고 감광막(3)을 도포한 후 소자분리마스크를 이용하여 상기 감광막(3)을 패터닝하고, 패터닝된 상기 감광막(3)을 마스크로 이용한 식각공정을 통해 노출된 부분의 상기 제1산화막(2)및 실리콘기판(1)을 순차적으로 식각하여 상기 실리콘기판(1)에 소정깊이(A)의 트랜치(4)를 형성시킨 상태의 단면도인데, 상기 트랜치(4)의 깊이(A)는 채널스토퍼를 형성하지 않아도 소자분리효과가 충분히 나타나도록 1.0내지 2.0 μm정도로 비교적 깊게 형성하며, 이때 상기 제1산화막(2)는 실리콘기판(1)에 가해지는 스트레스(Stress)를 완화시키는 역할을 한다.FIG. 1A illustrates that the first oxide film 2 is formed to a thickness of 150 to 250 Å on the silicon substrate 10, the photoresist film 3 is applied, and the photoresist film 3 is patterned and patterned using an element isolation mask. The first oxide film 2 and the silicon substrate 1 of the exposed portion are sequentially etched through an etching process using the photosensitive film 3 as a mask, and a trench having a predetermined depth A is formed on the silicon substrate 1. 4) is a cross-sectional view of the trench 4, and the depth A of the trench 4 is formed relatively deep in the range of 1.0 to 2.0 μm so that the device isolation effect is sufficiently exhibited even without forming the channel stopper. 2) serves to relieve stress applied to the silicon substrate (1).

제1b도는 패터닝된 상기 감광막(3) 및 제1산화막(2)을 순차적으로 제거하고 전체면에 제2산화막(5) 및 질화막(6)을 순차적으로 형성한 다음 상기 트랜치(4) 내부가 완전히 매몰(Filling)되도록 전체상부면에 플로우특성이 양호한 BPSG(Borophospho Silicate Glass)막(7)을 증착한 상태의 단면도인데, 상기 제2산화막(5) 및 질화막(60은 후속열처리시 상기 BPSG막(7)내에 함유된 불순물이 상기 실리콘기판(1)으로 확산되는 것을 방지하기 위한 베리어(Barrier)역할을 한다.FIG. 1B illustrates that the patterned photosensitive film 3 and the first oxide film 2 are sequentially removed, the second oxide film 5 and the nitride film 6 are sequentially formed on the entire surface, and then the inside of the trench 4 is completely formed. A cross-sectional view of a BPSG (Borophospho Silicate Glass) film 7 having a good flow characteristic is deposited on the entire upper surface to be filled, and the second oxide film 5 and the nitride film 60 are the BPSG film during subsequent heat treatment. 7) serves as a barrier (barrier) to prevent the impurities contained in 7 to diffuse into the silicon substrate (1).

제1c도는 상기 BPSG막(7)을 플로우시켜 평탄화한 후 전체상부면에 감광막(8)을 도포하여 표면을 완전히 평탄화시킨 상태의 단면도이다.1C is a cross-sectional view of a state in which the BPSG film 7 is flattened by flow and then the photoresist film 8 is applied to the entire upper surface to completely flatten the surface.

제1d도는 제1c도의 상태에서 감광막과 BPSG의 식각비가 1:1인 조건에서 애치백(Etch back)공정으로 상기 감광막(8)과 BPSG막(7)을 제거하여 평탄화시킨 후 노출된 질화막(6)과 제2산화막(5)을 순차적으로 제거한 상태의 단면도인데, 이때 상기 제1b도의 상태에서 상기 BPSG막(7)을 플로우시켜 평탄화한 후 화학적기계연마(Chemical Mechanical Polishing:CMP)방법으로 상기 BPSG막(7)을 제거하여 평탄화시키고 노출된 질화막(6)과 제2산화막(5)을 순차적으로 제거하는 방법을 이용해도 된다.FIG. 1d illustrates the nitride film 6 that is exposed after planarization by removing the photoresist film 8 and the BPSG film 7 by an etching back process under an etching ratio of the photoresist film and the BPSG in the state of FIG. 1c. ) And the second oxide film 5 are sequentially removed, wherein the BPSG film 7 is flattened by flowing the BPSG film 7 in the state of FIG. 1b, and then the BPSG method is subjected to chemical mechanical polishing (CMP). The film 7 may be removed and planarized, and the exposed nitride film 6 and the second oxide film 5 may be sequentially removed.

제2a내지 제2c도는 본 발명의 제2실시예를 설명하기 위한 소자의 단면도로서, 제2a도는 실리콘기판(11)상에 산화막(12), 질화막(13) 및 감광막(14)을 순차적으로 형성한 후 소자분리마스크를 이용하여 상기 감광막(14)을 패터닝하고, 패터닝된 상기 감광막(14)을 마스크로 이용한 식각공정을 통해 노출된 부분의 상기 질화막(13), 산화막(12) 및 실리콘기판(11)을 순차적으로 식각하여 상기 실리콘기판(1)에 소정깊이(B)의 트랜치(15)를 형성시킨 상태의 단면도인데, 상기 트랜치(15)의 깊이(B)는 0.3 내지 0.7μm정도가 되도록 식각하며, 이때 상기 질화막(13)과 산화막(12)은 실리콘기판(11)에 가해지는 스트레스를 완화시키는 역할을 한다.2A through 2C are cross-sectional views of devices for explaining the second embodiment of the present invention, and FIG. 2A shows an oxide film 12, a nitride film 13, and a photosensitive film 14 sequentially formed on a silicon substrate 11. Afterwards, the photosensitive layer 14 is patterned using an isolation mask, and the nitride layer 13, the oxide layer 12, and the silicon substrate of the exposed portion are exposed through an etching process using the patterned photosensitive layer 14 as a mask. 11) are etched sequentially to form a trench 15 of a predetermined depth (B) in the silicon substrate 1, the depth (B) of the trench 15 so as to be about 0.3 to 0.7μm In the etching process, the nitride film 13 and the oxide film 12 serve to relieve stress applied to the silicon substrate 11.

제2b도는 패터닝된 상기 감광막914)을 제거하고 이온주입반응로내에서 채널스톱이온주입공정을 실시하여 상기 트랜치(15)주위의 실리콘기판(11)에 채널스토퍼(17)를 형성한 다음 상기 트랜치(15)내부가 완전히 매몰되도록 전체상부면에 TEOS막(16)을 증착한 상태의 단면도인데, 상기 채널스톱이온주입시 상기 질화막(13) 및 산화막(12)은 도핑 베리어(Doping barrier)역할을 하며, 상기 채널스토퍼(17)는 활성영역의 크기축소를 방지하기 위하여 상기 트랜치(15)의 외벽으로부터 0.2μm이하의 깊이에 얕게 형성되도록 한다.FIG. 2B illustrates the removal of the patterned photoresist 914 and performing a channel stop ion implantation process in an ion implantation reactor to form a channel stopper 17 on the silicon substrate 11 around the trench 15. 15 is a cross-sectional view of the TEOS film 16 deposited on the entire upper surface to completely buried the inside, and the nitride film 13 and the oxide film 12 serve as a doping barrier during the channel stop ion implantation. In addition, the channel stopper 17 is formed to be shallower at a depth of 0.2 μm or less from the outer wall of the trench 15 to prevent the size reduction of the active region.

제2c도는 전체상부면에 감광막(도시않됨)을 도포하여 표면을 완전히 평탄화시킨후 감광막과 TEOS의 식각비가 1:1인 조건에서 애치백공정으로 상기 감광막과 TEOS막(16)을 제거하여 평탄화시킨 후 노출된 질화막(13)과 산화막(12)을 순차적으로 제거한 상태의 단면도인데, 이때 상기 제2b도의 상태에서 화학적기계연마(CMP)방법으로 상기 TEOS막(16)을 제거하여 평탄화시킨 후 노출된 질화막(13)과 산화막(12)을 순차적으로 제거하는 방법을 이용해도 된다.FIG. 2C shows a planarization of the photoresist film (not shown) on the entire upper surface to completely planarize the surface, and then removes and planarizes the photoresist film and the TEOS film 16 by an ache-back process under an etching ratio of the photoresist film and the TEOS. The exposed nitride film 13 and the oxide film 12 are sequentially removed, wherein the TEOS film 16 is removed and planarized by chemical mechanical polishing (CMP) in the state of FIG. 2b. You may use the method of removing the nitride film 13 and the oxide film 12 sequentially.

상술한 바와 같이 본 발명에 의하면 실리콘 기판에 소정깊이의 미세 트랜치를 형성한 후 플로우특성이 양호한 물질을 증착하고 평탄화시켜 단차를 최소화시키므로써 소자의 평탄성을 향상시키며 활성영역의 크기를 증대시킬 수 있는 탁월한 효과가 있다.As described above, according to the present invention, after forming a fine trench of a predetermined depth on the silicon substrate, a material having good flow characteristics is deposited and planarized to minimize the step, thereby improving the flatness of the device and increasing the size of the active region. Excellent effect

Claims (8)

반도체 소자의 소자분리막 형성방법에 있어서, 실리콘기판상에 제1산화막 및 감광막을 순차적으로 형성한 후 소자분리마스크를 이용하여 상기 감광막을 패터닝하고, 패터냉된 상기 감광막을 마스크로 이용한 식각공정을 통해 노출된 부분의 상기 제1산화막 및 실리콘기판을 순차적으로 식각하여 상기 실리콘기판에 소정깊이의 트랜치를 형성시키는 단계와, 상기 단계로부터 상기 패터닝된 감광막 및 제1산화막을 순차적으로 제거하고 전체면에 제2산화막 및 질화막을 순차적으로 형성한 다음 상기 트랜치내부가 완전히 매몰되도록 전체상부면에 BPSG막을 증착하는 단계와, 상기 단계로부터 상기 BPSG막을 플로우시킨 후 전체상부면에 감광막을 도포하여 표면을 완전히 평탄화시키는 단계와, 상기 단계로부터 애치백공정으로 상기 감광막과 BPSG막을 제거하여 평탄화시킨 후 노출된 질화막과 제2산화막을 순차적으로 제거하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법In the method of forming a device isolation film of a semiconductor device, the first oxide film and the photoresist film are sequentially formed on a silicon substrate, and then the photoresist film is patterned using a device isolation mask, and the patterned photoresist film is used as an mask. Sequentially etching the exposed portions of the first oxide film and the silicon substrate to form trenches of a predetermined depth in the silicon substrate, and sequentially removing the patterned photoresist film and the first oxide film from the step, Forming a second oxide film and a nitride film sequentially and then depositing a BPSG film on the entire upper surface such that the trench is completely buried; and after flowing the BPSG film from the step, applying a photoresist to the entire upper surface to completely planarize the surface. And removing the photoresist film and the BPSG film from the step by an ashback process. W planarized after the device isolation film in a semiconductor device which comprises a nitride film and the second oxide film exposed by the step of sequentially removing the forming method 반도체 소자의 소자분리막 형성방법에 있어서, 실리콘기판상에 제1산화막 및 감광막을 순차적으로 형성한 후 소자분리마스크를 이용하여 상기 감광막을 패터닝하고, 패터닝된 상기 감광막을 마스크로 이용한 식각공정을 통해 노출된 부분의 상기 제1산화막 및 실리콘기판을 순차적으로 식각하여 상기 실리콘기판에 소정깊이의 트랜치를 형성시키는 단계와, 상기 단계로부터 상기 패터닝된 감광막 및 제1산화막을 순차적으로 제거하고 전체면에 제2산화막 및 질화막을 순차적으로 형성한 다음 상기 트랜치내부가 완전히 매몰되도록 전체 상부면에 BPSG막을 증착하는 단계와, 상기 단계로부터 상기 BPSG막을 플로우시켜 평탄화한 후 화학적 기계연마방법으로 상기 BPSG막을 제거하여 평탄화시키고 노출된 질화막 및 제2산화막을 순차적으로 제거하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.In the method of forming a device isolation film of a semiconductor device, after forming a first oxide film and a photoresist film sequentially on a silicon substrate, the photoresist film is patterned by using a device isolation mask, and exposed through an etching process using the patterned photoresist film as a mask Sequentially etching the first oxide film and the silicon substrate of the formed portion to form a trench having a predetermined depth in the silicon substrate, and sequentially removing the patterned photoresist film and the first oxide film from the step, and forming a second surface on the entire surface. Forming an oxide film and a nitride film sequentially, and then depositing a BPSG film on the entire upper surface so as to completely buried the trench, and the planarized by flowing the BPSG film from the step and then planarized by removing the BPSG film by chemical mechanical polishing Sequentially removing the exposed nitride film and the second oxide film A device isolation film forming method of a semiconductor device, characterized in that made. 제1 또는 제2항에 있어서 상기 트랜치의 깊이는 1.0내지 2.0μm로 형성되는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.The method of claim 1, wherein the trench has a depth of about 1.0 μm to about 2.0 μm. 반도체 소자의 소자분리막 형성방법에 있어서, 실리콘기판상에 산화막, 질화막 및 감광막을 순차적으로 형성한 후 소자분리마스크를 이용하여 상기 감광막을 패터닝하고, 패터닝된 상기 감광막을 마스크로 이용한 식각공정을 통해 노출된 부분의 상기 질호막, 산화막 및 실리콘기판을 순차적으로 식각하여 상기 실리콘기판에 소정깊이의 트랜치를 형성시키는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 제거하고 채널스톱이온주입공정을 실시하여 상기 트랜치주위의 실리콘기판에 채널스토퍼를 형성한 다음 상기 트랜치내부가 완전히 매몰되도록 전체상부면에 TEOS막을 증착하는 단계와, 상기 단계로부터 전체상부면에 감광막을 도포하여 표면을 완전히 평탄화시킨 후 애치백공정으로 상기 감광막과 TEOS막을 제거하여 평탄화시키고 노출된 질화막 및 산화막을 순차적으로 제거하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.In the method of forming a device isolation film of a semiconductor device, an oxide film, a nitride film, and a photoresist film are sequentially formed on a silicon substrate, and then the photoresist film is patterned by using a device isolation mask and exposed through an etching process using the patterned photoresist film as a mask. Sequentially etching the trench film, the oxide film, and the silicon substrate of the formed portion to form a trench having a predetermined depth in the silicon substrate, removing the patterned photosensitive film from the step, and performing a channel stop ion implantation process to perform the trench. Forming a channel stopper on the surrounding silicon substrate and depositing a TEOS film on the entire upper surface so as to completely bury the trench, and from this step, the photoresist is applied on the entire upper surface to completely planarize the surface, and then The photoresist film and the TEOS film are removed and planarized to expose the vagina. Device isolation method for forming a semiconductor device, characterized in that the film and the oxide film is made of a step of sequentially removed. 반도체 소자의 소자분리막 형성방법에 있어서, 실리콘기판상에 산화막, 질화막 및 감광막을 순차적으로 형성한 후 소자분리마스크를 이용하여 상기 감광막을 패터닝하고, 패터닝된 상기 감광막을 마스크로 이용한 식각공정으로 통해 노출된 부분의 상기 질화막, 산화막 및 실리콘기판을 순차적으로 식각하여 상기 실리콘기판에 소정깊이의 트랜치를 형성시키는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 제거하고 채널스톱이온주입공정을 실시하여 상기 트랜치주위의 실리콘기판에 채널스토퍼를 형성한 다음 상기 트랜치 내부가 완전히 매몰되도록 전체상부면에 TEOS막을 증착하는 단계와, 상기 단계로부터 화학적기계연마방법으로 상기 TEOS막을 제거하여 평탄화시킨 후 노출된 질화막 및 산화막을 순차적으로 제거하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.In the method of forming a device isolation film of a semiconductor device, an oxide film, a nitride film, and a photoresist film are sequentially formed on a silicon substrate, and then the photoresist film is patterned using a device isolation mask and exposed through an etching process using the patterned photoresist film as a mask. Sequentially etching the nitride film, the oxide film, and the silicon substrate of the formed portion to form a trench having a predetermined depth in the silicon substrate, removing the patterned photoresist film from the step, and performing a channel stop ion implantation process to perform the periphery of the trench. Forming a channel stopper on the silicon substrate and depositing a TEOS film on the entire upper surface of the trench to completely bury the inside of the trench; and removing and planarizing the TEOS film by chemical mechanical polishing from the step to expose the nitride film and the oxide film. Consisting of steps of sequentially removing Device isolation method for forming a semiconductor device according to claim. 제4또는 제5항에 있어서, 상기 트랜치의 깊이는 0.3 내지 0.7μm인 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법The method of claim 4, wherein the trench has a depth of about 0.3 μm to about 0.7 μm. 제4 또는 제5항에 있어서, 상기 채널스토퍼는 활성영역의 크기축소를 방지하기 위하여 상기 트랜치의 외벽으로부터 0.2μm이하의 깊이에 형성되는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법The method of claim 4, wherein the channel stopper is formed at a depth of 0.2 μm or less from an outer wall of the trench to prevent size reduction of an active region. 제7항에 있어서, 상기 채널스토퍼를 형성하기 위한 채널스톱이온주입공정은 이온주입반응로내에서 실시되는 것을 특징으로 하는 반도체 소자의 소자분리막 형성방법.8. The method of claim 7, wherein the channel stop ion implantation process for forming the channel stopper is performed in an ion implantation reactor.
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KR100487513B1 (en) * 1998-07-10 2005-07-07 삼성전자주식회사 A method for fabricating trench isolation

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Publication number Priority date Publication date Assignee Title
KR100487513B1 (en) * 1998-07-10 2005-07-07 삼성전자주식회사 A method for fabricating trench isolation

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