KR100487513B1 - A method for fabricating trench isolation - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing trench isolation that prevents dent generation of trench isolation edges. After trenches are formed, SiN, a trench etch mask, is stripped. A thermal oxide film and a SiN liner for preventing oxidation of the trench inner wall are sequentially formed in the trench inner wall. After the trench isolation is deposited, the trench isolation is planarized and etched until the top surface of the SiN liner is exposed. After the SiN liners on both sides of the trench are stripped, the pad oxide film is removed. With this method of manufacturing a semiconductor device, when SiN, which is a trench etch mask, is stripped, the SiN liner may be overetched to prevent dents occurring at the edge portions of the trench isolation, and thus, poly dents may be formed at the dent portions during subsequent gate poly formation. This can prevent the gate bridge caused by remaining, and improve the electrical characteristics of the trench isolation.

Description

A METHOD FOR FABRICATING TRENCH ISOLATION

TECHNICAL FIELD The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing trench isolation.

The characteristics and reliability of transistors, which are the basis of device construction, are closely related to the isolation of cells and fields.

Isolation effectively isolates the cell from the field, thereby ensuring complete isolation between the device and the device during operation, preventing leakage currents. Therefore, if sufficient isolation between the cell and the field is not achieved, the reliability of the device is caused by leakage current.

Trench isolation method is currently used in high density devices such as 256M DRAM and 1G DRAM to overcome the isolation limit in the micro pattern due to the bird's beak of the local local oxidation of silicon (LOCOS) isolation. It is losing isolation technology.

Unlike the conventional LOCOS-based isolation method in which the active region is insulated from the active region by oxidizing the field region, the trench isolation method directly etches a silicon substrate and deposits a chemical vapor deposition (CVD) oxide layer to fill the trench, and then CMP. It is a technology to achieve device isolation by planarization through chemical mechanical polishing.

However, trench isolation has the advantage of being effective for isolation in fine patterns, but has a structure that is vulnerable to stress, resulting in leakage and shallow pit due to dislocation, etc. The problem that a characteristic falls is produced. The disposition may be performed by the thermal budget during the subsequent deposition and annealing of the CVD oxide layer after the trench etching and the diffusion of O ₂ gas during the deposition of the CVD oxide layer. It is known to be mainly caused by stress due to volume expansion generated during oxidation. In order to improve this problem, current trench isolation process uses a thin silicon nitride film (hereinafter referred to as 'SiN') liner after the trench etching to prevent the diffusion of O ₂ during the deposition of the CVD oxide film to stress the oxidation of the trench inner wall A method for preventing the introduction has been introduced and used.

1A and 1B are flow charts sequentially illustrating the processes of a conventional trench isolation manufacturing method.

Referring to FIG. 1A, in the conventional trench isolation manufacturing method, a pad oxide film 2 and a SiN 3 are sequentially formed on a semiconductor substrate 1. The SiN (3) is deposited to have a thickness of, for example, 1500 kPa. A trench etching mask 4 is formed by defining a trench formation region and patterning the SiN 3 and the pad oxide layer 2 using photolithography, which is well known in the art. The semiconductor substrate 1 is etched using the trench etch mask 4 to form the trench 6. Thermal oxides 8 are formed on the inner walls of the trenches, that is, on the lower and both side walls of the trenches, to remove the silicon damage layer generated during the etching process for forming the trenches 6.

Next, a SiN liner 10 is deposited on the thermal oxide film 8 and the trench etch mask 4 to prevent oxidation of the inner wall of the trench. Trench isolation layer 12 is deposited until the trench 6 is completely filled on the SiN liner 10. The trench isolation layer 12 is typically a USG (undoped silicate glass) film.

The trench isolation layer 12 is planarized by a CMP process or the like until the upper surface of the trench etch mask 4 is exposed. In this case, not only the trench etching mask 4 but also the SiN liner 10 of the trench edge portion is exposed.

Finally, when the trench etch mask 4 is removed by a phosphoric acid strip process, trench isolation 20 is completed, as shown in FIG. 1B.

However, during the phosphate strip process, the SiN liner 10 is simultaneously etched to generate dents at edge portions of the trench isolation 20, as indicated by reference numeral 13. The dent 13 is generated when the thickness of the SiN liner 10 is 53 kPa or more. On the other hand, when the thickness of the SiN liner 10 is 45Å or less, a problem arises in that the trench inner wall oxidation prevention property is lost.

Due to the occurrence of the dent 13, the refresh characteristics of the device are degraded, or the poly residue present in the dent 13 during the subsequent gate poly etching causes the gate bridge. Is generated.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a method of manufacturing trench isolation, which can prevent the occurrence of dents in the trench isolation edge portions, and thus can improve the electrical characteristics of the trench isolation. have.

(Configuration)

According to the present invention for achieving the above object, a method of manufacturing a trench isolation, comprising: forming a trench etching mask by patterning a first oxide film and a first nitride film sequentially formed on a semiconductor substrate; Etching the semiconductor substrate using the trench etching mask to form a trench; Stripping the first nitride film; Forming a second oxide layer on the bottom surface and both sidewalls of the trench; Forming a second nitride film on the second oxide film and the first oxide film to prevent oxidation of the trench lower surface and both sidewalls; Forming a trench isolation layer on the second nitride layer until the trench is completely filled; Planar etching the trench isolation layer until the upper surface of the second nitride layer is exposed; Stripping the second nitride film until the upper surface of the first oxide film is exposed; And removing the first oxide layer until the upper surface of the semiconductor substrate on both sides of the trench is exposed.

(Action)

Referring to FIG. 2D, in the novel method of manufacturing trench isolation according to an embodiment of the present invention, after the trench is formed, SiN, which is a trench etching mask, is stripped. As a result, when the SiN, which is a trench etching mask, is stripped, the SiN liner may be over-etched to prevent dents occurring at the edge portions of the trench isolation, thereby preventing the gate bridges generated by the residual poly in the dent portions during subsequent gate poly formation. You can prevent it. As a result, it is possible to improve the electrical properties of the trench isolation.

(Example)

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.

2A-2G are flow diagrams sequentially illustrating the processes of a trench isolation manufacturing method in accordance with an embodiment of the present invention.

Referring to FIG. 2A, in the trench isolation manufacturing method according to the exemplary embodiment of the present invention, a pad oxide film 102 and a SiN 103 are sequentially formed on a semiconductor substrate 100. The pad oxide film 102 is formed by, for example, a thermal oxidation method. The SiN 103 and the pad oxide layer 102 are patterned by a photolithography process well known in the art to form a trench etch mask 104.

The semiconductor substrate 100 is etched using the trench etch mask 104 to form the trench 106.

In FIG. 2B, after the SiN 103 is removed by the phosphate strip process, defects that act as a leakage source, such as silicon lattice damage generated during the trench etching process, as shown in FIG. 2C. In order to remove the thermal oxide film 108 is formed on the inner wall of the trench 106. At this time, during the formation of the thermal oxide film 108, the thickness of the pad oxide film 102 is also increased to some extent.

The SiN liner 110 is deposited on the pad oxide layer 102a including the thermal oxide layer 108 to prevent oxidation of the inner wall of the trench. The SiN liner 110 is formed of Si ₃ N ₄ , which is a conventional silicon nitride film, or Si _{(3 + α)} N ₄ , which is a silicon rich (Si-rich) nitride film containing a large amount of silicon in a composition ratio.

Referring to FIG. 2D, a trench isolation layer 112 is deposited on the SiN liner 110 until the trench 106 is completely filled. The trench isolation layer 112 is typically an undoped silicate glass (USG) film and a PECVD tetraethylorthosilicate (PE-TEOS) film.

After the trench isolation layer 112 is planarized by a CMP process or the like until the upper surface of the SiN liner 110 is exposed, as shown in FIG. 2F, until the upper surface of the pad oxide layer 102a is exposed. SiN liner 110 is etched by a phosphate strip process.

In the SiN liner 110 strip process, a dent portion is generated as shown by reference numeral 113, but since the thickness of the etched SiN liner 110 is thinner than that of the SiN 103, the etching time is relatively short, so the dent The incidence is relatively small. This makes it possible to form the thickness of the SiN liner 110 as thick as 85 kPa or more, for example, 100 kPa, thereby increasing the reliability of the device.

Finally, when the pad oxide layer 102a is stripped, trench isolation 120 according to the present invention without the SiN liner dent is completed, as shown in FIG. 2G.

By stripping the SiN mask after the trench formation, the present invention can prevent dents occurring at the edge portions of the trench isolation, thus preventing gate bridges caused by the residual poly in the dents during subsequent gate poly formation, There is an effect that can improve the electrical characteristics of the trench isolation.

1A and 1B are flow diagrams showing in sequence the processes of a conventional trench isolation manufacturing method;

2A-2G are flow diagrams showing in sequence the processes of a trench isolation manufacturing method in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

1, 100: semiconductor substrate 4, 104: trench etching mask

6, 106: trench 8, 108: thermal oxide film

10, 110: SiN liner 12, 112: trench isolation film

20, 120: trench isolation

Claims (4)

Patterning the first oxide film 102 and the first nitride film 103 sequentially formed on the semiconductor substrate 100 to form a trench etch mask 104; Etching the semiconductor substrate 100 using the trench etch mask 104 to form a trench 106; Stripping the first nitride film (103); Forming a second oxide film (108) on the trench lower surface and both sidewalls; Forming a second nitride film (110) on the second oxide film (108) and the first oxide film (102) to prevent oxidation of the trench lower surface and both sidewalls; Forming a trench isolation layer 112 on the second nitride layer 110 until the trench 106 is completely filled; Planar etching the trench isolation layer 112 until the upper surface of the second nitride layer 110 is exposed; Stripping the second nitride film 110 until the upper surface of the first oxide film 102 is exposed; And Removing the first oxide layer (102) until the top surface of the semiconductor substrate (100) on both sides of the trench (106) is exposed. The method of claim 1, And the first nitride film (103) and the second nitride film (110) are formed of a silicon nitride film (SiN (Si ₃ N ₄ )). The method of claim 1, And the first nitride film (103) and the second nitride film (110) are formed of SiN and silicon rich nitride film (Si _{(3 + α)} N ₄ ), respectively. The method of claim 1, And the second nitride film (110) is formed to have a thickness of about 85 GPa or more.