KR20000008301A - Method of fabricating trench isolation - Google Patents

Abstract

PURPOSE: The method can prevent the generation of a gate bridge due to the generation of a dent around the edge of a trench isolation(112). CONSTITUTION: A SiN liner(106) is formed on the inner wall of a trench(104) formed on a semiconductor substrate(100). The trench isolation is deposited on the SiN liner until the trench is fully filled. A trench etch mask(102) is removed after the trench isolation and the SiN liner are planarized by etching until the top surface of the trench etch mask is revealed. An insulating layer spacer(110a) is formed on both side walls of the trench isolation. The dent can be removed and the gate bridge generated by the poly residue around the dent can be prevented.

Description

A METHOD FOR FABRICATING TRENCH ISOLATION

TECHNICAL FIELD The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing trench isolation.

The characteristics and reliability of transistors, which are the basis of device construction, are closely related to the isolation of cells and fields.

Isolation effectively isolates the cell from the field, thereby ensuring complete isolation between the device and the device during operation, preventing leakage currents. Therefore, if sufficient isolation between the cell and the field is not achieved, the reliability of the device is caused by leakage current.

Trench isolation method is mainly used in high-density devices such as 256M DRAM and 1G DRAM to overcome the isolation limit in the micropattern due to the bird's beak of the existing local oxidation of silicon (LOCOS) isolation. It is losing isolation technology.

Unlike the conventional LOCOS-based isolation method in which the active region is insulated from the active region by oxidizing the field region, the trench isolation method directly etches a silicon substrate and deposits a chemical vapor deposition (CVD) oxide layer to fill the trench, and then CMP. It is a technology to achieve device isolation by planarization through chemical mechanical polishing.

However, trench isolation has the advantage of being effective for isolation in fine patterns, but has a structure that is vulnerable to stress, resulting in leakage and shallow pit due to dislocation, etc. The problem that a characteristic falls is produced. The disposition may be performed by thermal budgeting during the subsequent deposition and annealing of the CVD oxide layer after the trench etching, and by the diffusion of O 2 gas during deposition of the CVD oxide layer, that is, the silicon in the trench, that is, the inner wall of the trench is oxidized. It is known that it is mainly caused by the stress caused by volume expansion. In order to improve this problem, current trench isolation process uses a thin silicon nitride film (hereinafter referred to as 'SiN') liner after the trench etching to prevent the diffusion of O2 during CVD oxide deposition to prevent stress caused by trench sidewall oxidation This method is introduced and used.

1A-1C are flow diagrams illustrating in sequence the processes of a conventional trench isolation manufacturing method.

Referring to FIG. 1A, in the conventional trench isolation manufacturing method, a trench etch mask 2 is formed on a semiconductor substrate 1 with a pad oxide (not shown) interposed therebetween. The trench etch mask 2 is generally formed of SiN. The semiconductor substrate 1 is etched using the trench etch mask 2 to form the trench 4. A SiN liner 6 is deposited on the trench etch mask 2 to prevent oxidation of the inner wall of the trench, including the lower surface and both side walls of the trench 4, that is, the inner wall of the trench. Before the SiN liner 6 deposition process, an oxidation process may be further performed to remove the silicon damage layer generated during the trench etching.

Trench isolation layer 8 is deposited until the trench 4 is completely filled on the SiN liner 6. The trench isolation film 8 is typically a USG (undoped silicate glass) film.

In FIG. 1B, the trench isolation layer 8 is planarized etched by a CMP process or the like until the upper surface of the trench etch mask 2 is exposed. In this case, not only the trench etching mask 2 but also the SiN liner 6 of the trench edge portion is exposed.

Finally, when the trench etch mask 2 is removed by a phosphoric acid strip process, trench isolation 10 is completed, as shown in FIG. 1C.

However, during the phosphate strip process, a portion of the SiN liner 6 is simultaneously etched to generate dents at the edge portions of the trench isolation 10, as indicated by reference numeral 11. This dent 11 appears to be about 325 mm between the active and the field (reference numeral 'a'). The occurrence of this dent 11 degrades the refresh characteristics of the device or the subsequent gate poly etching. The poly residue between the dent sites in Si is a problem that causes the gate bridge.

The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a method of manufacturing trench isolation, which can prevent a gate bridge due to dent generation of trench isolation edge portions.

1A-1C are flow diagrams sequentially illustrating the processes of a conventional trench isolation manufacturing method.

2A-2C are flow diagrams showing in sequence the processes of a trench isolation manufacturing method in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

1, 100: semiconductor substrate 2, 102: trench etching mask

4, 104: trench 6, 106: SiN liner

8, 108: trench isolation 10, 112: trench isolation

110: peeling insulating film 110a: insulating film spacer

(Configuration)

According to the present invention for achieving the above object, a method of manufacturing a trench isolation, forming a trench etching mask for defining a trench isolation region on a semiconductor substrate; Etching the semiconductor substrate using the trench etching mask to form a trench; Forming a material layer to prevent oxidation of the inner wall of the trench; Forming a trench isolation layer over the material layer until the trench is completely filled; Planar etching the trench isolation layer and the material layer until the top surface of the trench etching mask is exposed; Removing the trench etch mask; And forming insulating layer spacers on both sidewalls of the trench isolation layer.

In a preferred embodiment of the method, the forming of the insulating layer spacer may include forming an insulating layer on the entire surface of the semiconductor substrate including the trench isolation layer; And etching the insulating layer by an etch back process until the upper surface of the semiconductor substrate on both sides of the trench is exposed.

(Action)

Referring to FIG. 2C, in the novel trench isolation method according to an embodiment of the present invention, after the trench etching mask is removed, spacers formed by high temperature oxide layers are formed on both sidewalls of the trench isolation layer. This makes it possible to eliminate the dents generated at the edge portions of the trench isolation and thus prevent gate bridges caused by the poly remaining in the dent portions during subsequent gate poly formation.

(Example)

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.

2A-2C are flow diagrams illustrating in sequence processes of a trench isolation manufacturing method in accordance with an embodiment of the present invention.

Referring to FIG. 2A, in the trench isolation manufacturing method according to the embodiment of the present invention, a trench etching mask 102 is formed on a semiconductor substrate 100 with a pad oxide film (not shown) interposed therebetween. The trench etch mask 102 is typically formed of SiN. The semiconductor substrate 100 is etched using the trench etch mask 102 to form the trench 104. A SiN liner 106 is deposited on the trench etch mask 102 to prevent oxidation of the trench inner wall, including the bottom surface and both side walls of the trench 104, that is, the trench inner wall. An oxidation process may be further performed to remove the silicon damage layer generated during the trench etching before the SiN liner 106 deposition process.

Trench isolation layer 108 is deposited until the trench 104 is completely filled on the SiN liner 106. The trench isolation 108 is typically a USG (undoped silicate glass) film.

After the trench isolation layer 108 is flattened by a CMP process or the like until the upper surface of the trench etch mask 102 is exposed, the trench etch mask 102 is removed by a phosphoric acid strip process. .

At this time, a portion of the SiN liner 106 is simultaneously etched during the phosphoric acid strip process, so that dents are generated at the boundary between the trench 104 and the trench isolation layer 108 as shown by reference numeral 109.

Therefore, as shown in FIG. 2B, a novel filling insulating layer 110 according to the present invention is deposited on the entire surface of the semiconductor substrate 100 to fill the dent 109. The peeling insulating layer 110 is deposited to a thickness sufficient to fill the dent 109, for example, when the gap between the active and the field is about 325 mm 3 to 300 mm to 400 mm.

The peeling insulating layer 110 is preferably a film having a small etching amount in the subsequent cleaning process while effectively filling the dent 109, for example, a high temperature oxide is used.

Finally, the peeling insulating layer 110 is dry-etched by an etch-back process until the upper surface of the semiconductor substrate 100 (active) on both sides of the trench is exposed. Then, as shown in FIG. 2C, insulating film spacers 110a are formed on both sides of the trench isolation film 108, thereby completing trench isolation 112 having no dent according to the present invention.

The present invention can eliminate the dents generated at the edge portion of the trench isolation, thus preventing the gate bridge caused by the residual poly in the dent portion during subsequent gate poly formation.

Claims (6)

Forming a trench etch mask 102 for defining a trench isolation region on the semiconductor substrate 100; Etching the semiconductor substrate 100 using the trench etch mask 102 to form a trench 104; Forming a material layer (106) to prevent oxidation of the trench inner wall; Forming a trench isolation layer 108 over the material layer 106 until the trench 104 is completely filled; Planar etching the trench isolation layer 108 and the material layer 106 until the upper surface of the trench etching mask 102 is exposed; Removing the trench etch mask (102); And Forming insulating layer spacers (110a) on both sidewalls of the trench isolation layer (108). The method of claim 1, And the material layer (106) is formed of SiN. The method of claim 1, The forming of the insulating layer spacer 110a may include forming the insulating layer 110 on the entire surface of the semiconductor substrate 100 including the trench isolation layer 108; And Etching the insulating (110) layer by an etch back process until the upper surface of the semiconductor substrate (100) on both sides of the trench (104) is exposed. The method of claim 3, wherein The insulating layer (110) is a high temperature oxide film. The method of claim 3, wherein The insulating layer (110) is a method of manufacturing trench isolation is deposited within a thickness range of 200 kPa to 400 kPa. The method of claim 1, The insulating layer spacer (110a) is formed to remove the dent of the trench edge portion generated when the trench etch mask (102) is removed.