KR100221626B1 - A device isolation film of semiconductor device and method for manufacturing the same - Google Patents
A device isolation film of semiconductor device and method for manufacturing the same Download PDFInfo
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- KR100221626B1 KR100221626B1 KR1019960054207A KR19960054207A KR100221626B1 KR 100221626 B1 KR100221626 B1 KR 100221626B1 KR 1019960054207 A KR1019960054207 A KR 1019960054207A KR 19960054207 A KR19960054207 A KR 19960054207A KR 100221626 B1 KR100221626 B1 KR 100221626B1
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- isolation film
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- 238000002955 isolation Methods 0.000 title claims abstract description 78
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 claims abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 239000005368 silicate glass Substances 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 5
- 230000008021 deposition Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- -1 nitrogen (N 2 ) ions Chemical class 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체장치의 소자분리막 및 그의 제조방법에 관한 것으로서 반도체 기판과, 상기 반도체기판의 소정 부분에 형성된 트렌치와, 상기 트렌치 하부에 주입된 이온이 활성화되어 상기 반도체기판과 반응하여 형성된 제1소자분리막과, 상기 트렌치 내부에 형성된 제2소자분리막을 포함한다. 따라서, 제1소자분리막이 완만한 타원형으로 형성되므로 소자분리막에 전계가 집중되는 것을 방지할 수 있으며, 트렌치 형성시 제1소자분리막이 식각정지층으로 사용되어 재현상을 향상시킬 수 있을 뿐만 아니라 종횡비를 감소시켜 보이드가 생성되는 것을 방지할 수 있고, 또한, 트렌치를 한 번의 증착으로 채워 제2 소자분리막을 형성하므로 공정을 감소시킬 수 있다.The present invention relates to a device isolation film of a semiconductor device and a method of manufacturing the same, and more particularly, to a device isolation film and a method of manufacturing the device isolation film of a semiconductor device, including a semiconductor substrate, a trench formed in a predetermined portion of the semiconductor substrate, And a second device isolation film formed in the trench. Accordingly, since the first isolation layer is formed in a gentle elliptical shape, it is possible to prevent the electric field from concentrating on the isolation layer, and the first isolation layer can be used as an etch stop layer during trench formation to improve re- It is possible to prevent voids from being generated, and the process can be reduced because the trench is filled with one deposition to form the second device isolation film.
Description
제1도는 본 발명에 따른 소자분리막의 단면도.FIG. 1 is a cross-sectional view of a device isolation film according to the present invention. FIG.
제2a도 내지 e도는 본 발명에 따른 소자분리막의 형성방법을 도시하는 공정도.Figures 2a through e are process drawings showing a method of forming an element isolation film according to the present invention.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
11 : 반도체기판 13 : 마스크막11: semiconductor substrate 13: mask film
15 : 불순물주입영역 17 : 제1소자분리막15: impurity implantation region 17: first element isolation film
19 : 트렌치 21 : 완충산화막19: trench 21: buffer oxide film
23 : 제2소자분리막23: Second element isolation film
본 발명은 반도체장치의 소자분리막 및 그의 형성방법에 관한 것으로서, 특히, 작은 면적을 갖는 반도체장치의 소자분리막 그의 형성방법에 관한 것이다.The present invention relates to a device isolation film of a semiconductor device and a method of forming the same, and more particularly, to a method of forming an element isolation film of a semiconductor device having a small area.
반도체장치의 집적화가 거듭되면서 반도체장치의 상당한 면적을 점유하는 소자분리영역을 줄이기 위한 기술 개발이 활발히 진행되고 있다.BACKGROUND ART [0002] As the integration of semiconductor devices continues, technology for reducing a device isolation region occupying a considerable area of a semiconductor device has been actively developed.
일반적으로 반도체장치는 LOCOS(Local Oxidation of Silicon) 방법으로 소자를 분리하였으나, 이 LOCOS 방법은 버즈 비크(bird's beak)에 의해 소자분리영역이 크게 된다.Generally, a semiconductor device has been separated by LOCOS (Local Oxidation of Silicon) method. However, this LOCOS method has a large device isolation region due to bird's beak.
그러므로, 작은 면적으로도 소자를 분리할 수 있는 트렌치를 이용한 소자분리방법이 개발되었다.Therefore, a device isolation method using a trench capable of separating a device with a small area has been developed.
종래의 트렌치를 이용한 소자분리방법이 미국 특허 제5,099,304호(발명의 명칭 : 'Semiconductor device with insulating isolation groove')에 게시되어있다. 상기 방법은 트렌치 내부에 산화막과 질화막을 증착하고 1차로 다결정실리콘을 증착한 후 보이드(void)가 제거되도록 에치 백하여 소정 높이 까지만 채운다. 그리고, 2차로 흐름 특성이 양호한 BPSG(Boro-Phospho Silicate Glass) 등으로 트렌치를 완전히 채운 후 평탄화하여 소자를 분리시킨다.A device isolation method using a conventional trench is disclosed in U.S. Patent No. 5,099,304 entitled " Semiconductor device with insulating isolation groove ". In this method, an oxide film and a nitride film are deposited in the trench, and polysilicon is first deposited thereon. Then, the trench is etched back to remove voids, and the film is filled up to a predetermined height. Then, the trench is completely filled with BPSG (Boro-Phospho Silicate Glass) having good secondary flow characteristics, and then the planarization is performed to separate the device.
그러나, 상술한 종래의 소자분리방법은 보이드를 제거하기 위해 2번의 증착을 하여야 하므로 공정이 복잡해는 문제점이 있었다. 또한, 소자분리영역의 면적이 더욱 작아지게 되면 트렌치의 종횡비(aspect ratio)가 증가되므로 트렌치를 일정한 크기로 형성하기 어려워 재현성이 저하될 뿐만 아니라 보이드를 제거하기 어려운 문제점이 있었다. 또한, 트렌치에 의해 소자분리막 하부의 모서리로 전계가 집중되는 문제점이 있었다.However, the above-described conventional device isolation method has a problem in that the process is complicated because two times of deposition must be performed to remove voids. Further, if the area of the device isolation region is further reduced, the aspect ratio of the trench is increased, so that it is difficult to form the trench with a certain size, and the reproducibility is lowered and voids are difficult to remove. Further, there is a problem that the electric field is concentrated at the edge of the lower part of the element isolation film by the trench.
따라서, 본 발명의 목적은 소자분리막 하부에 전계가 집중되는 것을 방지할 수 있는 반도체장치의 소자분리막을 제공함에 있다.Accordingly, it is an object of the present invention to provide an element isolation film of a semiconductor device which can prevent the electric field from being concentrated on the lower part of the element isolation film.
본 발명의 다른 목적은 트렌치를 한 번의 증착으로 채워 공정을 감소시킬 수 있는 반도체장치의 소자분리막의 형성방법을 제공함에 있다.It is another object of the present invention to provide a method of forming an element isolation film of a semiconductor device capable of reducing a process by filling a trench with a single deposition.
본 발명의 또 다른 목적은 소자분리막의 면적이 감소되어도 트렌치 형성시 재현성을 향상시킬 수 있을 뿐만 아니라 보이드가 생성되는 것을 방지할 수 있는 반도체장치의 소자분리막의 형성방법을 제공함에 있다.It is still another object of the present invention to provide a method of forming a device isolation layer of a semiconductor device which can improve reproducibility and voids during formation of a trench even if the area of the device isolation film is reduced.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 소자분리막은 반도체기판과, 상기 반도체기판의 소정 부분에 형성된 트렌치와, 상기 트렌치 하부에 주입된 이온이 활성화되어 상기 반도체기판과 반응하여 형성된 제1소자분리막과, 상기 트렌치 내부에 형성된 제2소자분리막을 포함한다.According to another aspect of the present invention, there is provided a device isolation film for a semiconductor device, including: a semiconductor substrate; a trench formed in a predetermined portion of the semiconductor substrate; And a second isolation layer formed in the trench.
상기 다른 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 소자분리막의 형성방법은 반도체기판의 표면에 소정 부분을 노출시키는 마스크충을 형성하는 공정과, 상기 반도체기판의 노출된 부분에 이온을 주입하여 활성화시켜 상기 반도체기판의 표면으로부터 소정 깊이에 제1소자분리막을 형성하는 공정과, 상기 마스크충을 식각 마스크로 사용하여 상기 제1소자분리막이 노출되도록 상기 반도체기판의 노출된 부분을 식각하여 트렌치를 형성하는 공정과, 상기 트렌치 내부에 제2소자분리막을 형성하는 공정과, 상기 마스크충을 제거하는 공정을 구비한다.According to another aspect of the present invention, there is provided a method for forming a device isolation layer in a semiconductor device, the method comprising: forming a mask layer on a surface of a semiconductor substrate to expose a predetermined portion; Forming a first device isolation film at a predetermined depth from a surface of the semiconductor substrate by activating the first device isolation film; etching the exposed portion of the semiconductor substrate to expose the first isolation film using the mask charge as an etch mask, A step of forming a second element isolation film in the trench, and a step of removing the mask charge.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.
제1도는 본 발명에 따른 반도체장치의 소자분리막의 단면도이다.FIG. 1 is a cross-sectional view of an element isolation film of a semiconductor device according to the present invention.
본 발명에 따른 반도체장치의 소자분리막은 반도체기판(11)의 소정 부분에 트렌치(19)이 형성되고, 이 트렌치(19)의 내부 표면에 완충산화막(21)이 형성된다. 그리고, 트렌치(19)의 하부에 제1소자분리막(17)이 형성되고 내부에 제2소자분리막(23)이 형성된다.In the device isolation film of the semiconductor device according to the present invention, a trench 19 is formed in a predetermined portion of the semiconductor substrate 11, and a buffer oxide film 21 is formed on the inner surface of the trench 19. A first isolation layer 17 is formed under the trench 19 and a second isolation layer 23 is formed in the trench 19.
상기에서 트렌치(19)는 2000~4000Å 정도의 깊이로 이방성식각되어 형성된다. 완충산화막(21)은 열산화방법에 의해 50~200Å 정도의 두께로 형성되는 것으로 트렌치(19) 형성시 내부 표면에 생성되는 손상을 완화시킨다.The trench 19 is anisotropically etched to a depth of about 2000 to 4000 angstroms. The buffer oxide film 21 is formed to a thickness of about 50 to 200 ANGSTROM by a thermal oxidation method, thereby alleviating the damage to the inner surface when the trench 19 is formed.
그리고, 제1소자분리막(17)은 산소(O2) 또는 질소(N2) 이온이 이온주입된 후 열처리하여 형성된 산화실리콘 또는 질화실리콘으로 형성된다. 상기에서 제1소자분리막(17)은 하부가 완만한 타원형으로 이루어져 전계가 집중되는 것을 방지한다.The first device isolation film 17 is formed of silicon oxide or silicon nitride formed by ion implantation of oxygen (O 2 ) or nitrogen (N 2 ) ions and heat treatment. In this case, the first device isolation layer 17 is formed in a gentle elliptical shape at the bottom to prevent the electric field from being concentrated.
제2소자분리막(23)은 제1소자분리막(17)상에 트렌치(19)내부를 채워 형성된다. 상기에서, 제2소자분리막(23)은 산화실리콘(SiO2), 질화실리콘(Si3N4), BPSG 또는 USG(Undoped Silicate Glass) 등의 절연물질로 형성된다.The second isolation film 23 is formed by filling the trench 19 on the first isolation film 17. The second isolation film 23 is formed of an insulating material such as silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), BPSG, or USG (Undoped Silicate Glass).
제2a도 내지 e도는 본 발명에 따른 소자분리막의 형성방법을 도시하는 공정도이다.Figs. 2a to 2e are process drawings showing a method of forming an element isolation film according to the present invention.
제2a도를 참조하면, 반도체기판(11)의 표면에 마스크층(13)을 형성한다. 상기 마스크층(13)은 산화막 또는 질화막을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 1000~3000Å 정도의 두께로 증착하여 형성한다.Referring to FIG. 2A, a mask layer 13 is formed on the surface of the semiconductor substrate 11. The mask layer 13 is formed by depositing an oxide film or a nitride film to a thickness of about 1000 Å to 3000 Å by a chemical vapor deposition (hereinafter referred to as CVD) method.
제2b도를 참조하면, 마스크층(13)의 소정 부분을 포토리쏘그래피(photolithography) 방법으로 제거하여 반도체기판(11)을 노출시킨다. 그리고, 마스크충(13)을 마스크로 사용하여 반도체기판(11)의 노출된 부분에 산소(O2) 또는 질소(N2)를 80~150KeV 정도의 에너지로 주입하여 불순물주입영역(15)을 형성한다. 이 때, 불순물주입영역(15)은 불순물 이온이 반도체기판(11)에 표면으로부터 2000~4000Å 정도의 깊이로 주입되어 형성된다.Referring to FIG. 2b, a predetermined portion of the mask layer 13 is removed by photolithography to expose the semiconductor substrate 11. Oxygen (O 2 ) or nitrogen (N 2 ) is implanted into the exposed portion of the semiconductor substrate 11 at an energy of about 80 to 150 KeV by using the mask burr 13 as a mask to form the impurity implanted region 15 . At this time, the impurity implantation region 15 is formed by implanting impurity ions into the semiconductor substrate 11 at a depth of about 2,000 to 4,000 ANGSTROM from the surface.
제2c도를 참조하면, 불순물주입영역(15)의 불순물 이온을 활성화시켜 제1소자분리막(17)을 형성한다. 상기에서 불순물주입영역(15) 내의 산소(O2) 또는 질소 (N2) 이온은 열에 의해 활성화되어 반도체기판(11)을 이루는 실리콘과 반응하여 산화막 또는 질화막으로 이루어진 제1소자분리막(17)을 형성한다. 이 때, 제1소자분리막(17)은 주입된 불순물이 활성화되어 형성되므로 완만한 타원형으로 이루게 된다. 그리고, 마스크층(13)을 마스크로 사용하여 반도체기판(11)의 노출된 부분을 반응성이온식각(RIE) 등의 방법으로 제1소자분리막(17)이 노출될 때까지 이방성식각하여 트렌치(19)를 형성한다. 이 때, 트렌치(19)는 제1소자분리막(17)으로 인해 종횡비가 크지 않아도 된다. 그리고, 제1소자분리막(17)은 반도체기판(11)과 식각 선택비가 크므로 식각정지층으로 사용된다. 따라서, 트렌치(19) 형성시 재현성을 향상시킬 수 있다.Referring to FIG. 2C, impurity ions in the impurity implantation region 15 are activated to form the first isolation film 17. The oxygen (O 2 ) or nitrogen (N 2 ) ions in the impurity implantation region 15 are activated by heat and react with silicon constituting the semiconductor substrate 11 to form a first isolation film 17 composed of an oxide film or a nitride film . At this time, since the impurity implanted is activated, the first isolation film 17 is formed into a gentle oval shape. The exposed portion of the semiconductor substrate 11 is subjected to anisotropic etching until the first isolation film 17 is exposed by reactive ion etching (RIE) or the like using the mask layer 13 as a mask, ). At this time, the aspect ratio of the trench 19 does not have to be large due to the first isolation film 17. The first isolation film 17 is used as an etch stop layer because the etching selectivity with the semiconductor substrate 11 is large. Therefore, the reproducibility can be improved when the trench 19 is formed.
제2d도를 참조하면, 트렌치(19) 내부 표면을 열산화하여 완충산화막(21)을 형성한다. 상기 완충산화막(21)은 트렌치(19) 형성시 내부 표면에 생성되는 손상을 완화시키는 것으로 50~200Å 정도의 두께로 형성된다. 상기에서, 완충산화막(21)을 형성하지 않고 열처리하여 트렌치(19) 내부 표면의 손상을 완화시킬 수도 있다.Referring to FIG. 2d, the inner surface of the trench 19 is thermally oxidized to form a buffer oxide film 21. The buffer oxide film 21 is formed to have a thickness of about 50 to 200 ANGSTROM for relieving damage to the inner surface at the time of forming the trench 19. In the above, the damage to the inner surface of the trench 19 may be alleviated by performing heat treatment without forming the buffer oxide film 21.
제2e도를 참조하면, 트렌치(19) 내에 제2소자분리막(23)을 형성한다. 제2소자분리막(23)은 마스크층(13) 및 완충산화막(21)상에 산화실리콘(SiO2), 질화 실리콘(Si3N4), BPSG 또는 USG(Undoped Silicate Glass) 등의 절연물질을 트렌치(19)가 채워지도록 증착한 후 RIE 또는 화학적-기계적 연마 방법으로 에치 백하므로써 형성된다. 그리고, 마스크막(13)을 제거한다.Referring to FIG. 2E, the second device isolation film 23 is formed in the trench 19. A second isolation film 23 has a trench with an insulating material such as a mask layer 13 and the buffer oxide film 21, a silicon oxide (SiO2), a silicon nitride (Si 3 N 4), BPSG or USG (Undoped Silicate Glass) (19), and then etched back by RIE or a chemical-mechanical polishing method. Then, the mask film 13 is removed.
상술한 바와 같이 본 발명에 따른 반도체장치의 소자분리막은 반도체기판의 마스크층이 제거되어 노출된 소정 부분에 산소(O2) 또는 질소(N2)를 이온 주입한 후 열처리하여 완만한 타원형의 제1소자분리막을 형성한다. 그리고, 반도체기판의 노출된 부분을 제1소자분리막이 노출되도록 이방성식각하여 트렌치를 형성하고 이 트렌치 내에 제2소자분리막을 형성한다.As described above, in the device isolation film of the semiconductor device according to the present invention, oxygen (O 2 ) or nitrogen (N 2 ) ions are implanted into a predetermined portion of the semiconductor substrate where the mask layer is removed and then heat treatment is performed to form a gentle elliptical 1 device isolation film is formed. Then, an exposed portion of the semiconductor substrate is anisotropically etched to expose the first isolation film, thereby forming a trench and forming a second isolation film in the trench.
따라서, 본 발명은 제1소자분리막이 완만한 타원형으로 형성되므로 소자분리막에 전계가 집중되는 것을 방지할 수 있으며, 트렌치 형성시 제1소자분리막이 식각정지층으로 사용되어 재현성을 향상시킬 수 있을 뿐만 아니라 종횡비를 감소시켜 보이드가 생성되는 것을 방지할 수 있는 잇점이 있다. 또한, 트렌치를 한 번의 증착으로 채워 제2소자분리막을 형성하므로 공정을 감소시킬 수 있는 잇점이 있다.Therefore, since the first device isolation film is formed in a gentle elliptical shape, the electric field can be prevented from concentrating on the device isolation film, and the first device isolation film can be used as an etch stop layer during trench formation to improve reproducibility However, there is an advantage that voids can be prevented from being generated by reducing the aspect ratio. Further, since the trench is filled with one deposition to form the second device isolation film, there is an advantage that the process can be reduced.
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