JPH08316487A - Manufacture of thin-film semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a method of manufacturing a thin-film semiconductor device, which makes a TFT exercise the control of a threshold voltage by channel doping without deteriorating the on-off characteristics of the TFT. CONSTITUTION: Channel doping impurities are ion-implanted in the surface of a substrate or an insulative thin-film and a doped substrate layer 13 is formed. After an a-Si film is formed on the layer 13, an excimer laser 17 irradiates, the a-Si film 14a is molten, is recrystallized and a polycrystalline Si film 14 is formed. Here, the impurities are thermodiffused from the interior of the layer 13 into the film 14 simultaneously with the formation of the film 14 and a doped channel region 16a is formed. After that, a gate electrode and source and drain regions are formed and a TFT is manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film semiconductor device, and more particularly to a method for manufacturing a thin film semiconductor device in which power consumption is reduced by channel doping.

[0002]

2. Description of the Related Art In recent years, there has been a demand for development of a peripheral drive circuit integration technology on a glass substrate for the purpose of realizing cost reduction and high definition of a liquid crystal display device (hereinafter referred to as LCD). This technique is a technique in which a peripheral drive circuit for driving a pixel region is integrally formed by a same process on a glass substrate on which a plurality of pixel regions are formed. When an LCD using a glass substrate is manufactured by a high temperature process, thermal distortion occurs in the glass substrate, which is not preferable. Therefore, LC
A low temperature process is used to manufacture D. Therefore, especially in a thin film transistor (hereinafter, referred to as a TFT) which is a driving device, high performance by a low temperature process is essential. For this reason, various approaches have been taken such as improving the quality of the constituent material of the TFT. For example, as a technique for improving the quality of an active layer material that influences device characteristics, it has been reported that the device characteristics are significantly improved by developing a thin film poly-Si material by an excimer laser annealing method using an a-Si film as a starting material. (199
Proceedings of the 3rd Autumn Meeting of Applied Physics 27p-ZW-1
1).

Further, as the quality of the active layer material has been improved, on the other hand, a technology for improving the quality of the gate insulating layer, which is deeply related to the device characteristics, by a low temperature process is also required. However, the gate insulating layer material is originally a material that obtains stable and good characteristics when formed at high temperature, and when formed using the current low temperature process, it is more likely to be present in the insulating layer than when formed at high temperature. There are many defects, which increase the threshold voltage that determines the switching characteristics of the TFT.

In the LCD drive circuit, a CMOS is used as a switching element in order to realize low power consumption.
Is being adopted. CMOS is an n-channel TFT and a p-channel TFT formed on the same substrate.
In the operation, it is necessary to match the threshold voltage of each TFT to perform the switching operation. When this CMOS is formed by a low temperature process, the threshold voltage becomes high especially on the p-channel TFT side due to the deterioration of the film quality of the gate insulating layer as described above, making it difficult to reduce the power consumption which is a characteristic of CMOS. The problem arises.

Therefore, conventionally, several methods have been devised to control the threshold voltage of the TFT to an optimum value. One method is to provide a sub-gate in the channel of the TFT and use this sub-gate to control the bias. However, according to this method, a step for separately providing a sub-gate is required in the step of manufacturing the element on the insulating substrate, which complicates the step. In addition, a structure for performing bias control on the sub-gate is also required, which complicates the device structure.

As another method, there is a channel doping method in which the channel of the TFT is slightly doped with impurities to control the threshold voltage. This method can be realized by adding a step of slightly doping the channel region with impurities, and thus the steps are simpler than those of the above method.

Here, a method of forming a TFT on an insulating substrate by using the conventional channel doping method will be described. FIG. 27 is a sectional structural view showing a device structure of a TFT manufactured by a manufacturing method to which a conventional channel doping method is applied, and FIGS. 28 to 32 are manufacturing process diagrams showing the manufacturing process for each step. is there. The TFT is formed on a substrate 1 such as non-alkali glass with an insulating thin film 2 interposed. The TFT is a device active layer 3 having a pair of impurity regions 8 and a channel region 16 formed therebetween.
And a gate electrode 6 formed on the element active layer 3 via a gate insulating layer 5. A pair of impurity regions 8 and 8
The contact hole 1 formed in the protective insulating layer 9
Extraction electrode 1 such as Al (aluminum) through 0
1, 11 are connected.

Next, the manufacturing process of the conventional p-channel TFT will be described in order. First, as shown in FIG. 28, an insulating thin film 2 made of SiO ₂ or the like is deposited and formed on a substrate 1 such as a non-alkali glass by a CVD (chemical vapor deposition) method or a sputtering method. The insulating thin film 2 is formed to prevent impurities contained in the substrate 1 from diffusing into the element active layer in a later step.

Next, as shown in FIG. 29, the insulating thin film 2
On top of this, a semiconductor thin film 3 such as polycrystalline Si, which becomes an element active layer, is formed.
A is deposited by CVD or sputtering. Further, B is added to the semiconductor thin film 3a by using an ion implantation method or the like.
Impurity 7 such as (boron) or P (phosphorus) is added (channel dope). In addition, at the time of this ion implantation,
Ion damage defects occur in the surface layer of the semiconductor thin film 3a.

Next, as shown in FIG. 30, the semiconductor thin film 3a doped with impurities is patterned by a normal photolithography process to form islands (element active layers) 3 of the semiconductor thin film.
To form. Further, a gate insulating film 5 made of SiO ₂ , SiN _x or the like is deposited on the entire surface.

Further, as shown in FIG. 31, polycrystalline Si
Alternatively, a gate electrode 6 made of a metal such as Ti, Mo, or Ta is formed, and using the gate electrode 6 as a mask, impurities 12 of B (P or the like in the case of an n-channel TFT) are used by an ion implantation method to form an element active layer. 3 to form a pair of impurity regions. Then, heat treatment or the like is applied to activate the implanted impurities to form the source / drain regions 8 and 8.

Further, as shown in FIG. 32, a protective insulating layer 9 made of SiO ₂ or SiN _{x is} deposited and formed, and the contact hole 1 is formed on the source / drain regions 8 and 8.
After opening 0 and 10, the extraction electrode 11 made of Al or the like,
11 is formed, and the p-channel TFT is completed.

Next, a device structure of a CMOS formed on an insulating substrate by applying the conventional channel doping method and a manufacturing method thereof will be described. FIG. 33 is a sectional structural view of a CMOS, and FIGS. 34 to 39 are manufacturing process diagrams showing the manufacturing process for each step. First, as shown in FIG. 33, the CMOS is composed of an n-channel TFT 20a and a p-channel TFT 20b formed on the same substrate 21. The n-channel TFT 20a includes an element active layer 23a having a pair of source / drain regions 28a, 28a formed therein.
And a gate electrode 26a formed on the element active layer 23a with the gate insulating layer 25 interposed therebetween. The p-channel TFT 20b has the same structure as the n-channel TFT and has a pair of source / drain regions 28b, 28b.
The device active layer 23b having b, the gate insulating layer 25, and the gate electrode 26b are provided. Extraction electrode 31
Are source / drain regions 28a, 28a, 28b, through the contact holes formed in the protective insulating layer 30.
28b.

The manufacturing process of this CMOS will be sequentially described below. First, as shown in FIG. 34, an insulating thin film 22 is deposited on a substrate 21 made of non-alkali glass or the like, and subsequently islands 23a and 23b of a semiconductor thin film made of polycrystalline Si or the like to be an element active layer are formed. .

Then, as shown in FIG. 35, a region having the island 23a on the n-channel side is masked with a resist 24a, and B (boron) or P () is formed on the island 23b on the p-channel side by an ion implantation method or the like. An impurity 27a such as phosphorus) is added. This enables the n-channel TFT
The side channel region is doped with an impurity for adjusting the threshold voltage.

Further, as shown in FIG. 36, the resist 2
After removing 4a, this time the island 2 on the p-channel side
A region having 3b is masked with a resist 24b, and an impurity 27b such as B or P is added to the island 23a on the n-channel side by an ion implantation method or the like. This gives n
Impurities for adjusting the threshold voltage are doped in the channel region of the channel TFT. Note that the steps shown in FIGS. 35 and 36 may be performed in a different order.

Further, as shown in FIG. 37, after the gate insulating film 25 is deposited on the entire surface, a material such as polycrystalline Si is deposited and patterned to form gate electrodes 26a and 26b.
To form.

Further, as shown in FIG. 38, ion implantation is performed in the same procedure as the channel doping procedure to implant P into a region having the island 23a on the n-channel side and the island 23b on the p-channel side. Inject B into the region. Thereafter, heat treatment or the like is performed to activate the implanted impurities to activate the n ⁺ source / drain regions 28a and 28a.
a and p ⁺ source / drain regions 28b and 28b are formed.

Further, as shown in FIG. 39, after the protective insulating layer 30 is deposited and formed, the contact hole 32 and the take-out electrode 31 are sequentially formed to complete the CMOS.

[0020]

As described above, in the conventional channel doping method, the impurity for adjusting the threshold voltage is directly ion-implanted into the surface of the device active layer, so that the surface of the device active layer has an ion damage defect. Occurs. In this case, in the case of a semiconductor device to which a high temperature process can be applied, this ion damage defect is recovered by a high temperature thermal process (impurity activation process) performed in a post process of channel doping. However, in the low-temperature process for the LCD as described above, even if the heat treatment process is performed in the post-step of channel doping, the temperature is low and the ion damage defect cannot be sufficiently recovered. As a result, the characteristics of the device may be deteriorated due to the ion damage defect in the channel region. For example, FIG. 8 shows drain current _ID -gate voltage V _G characteristics of a conventional TFT with channel doping (conventional example 2) and without channel doping (conventional example 1). Comparing the two, although the channel-doped TFT shows improvement such as lowering of the threshold voltage, on the other hand, the on-current decreases and the off-current increases, which causes characteristic deterioration. I understand.

An object of the present invention is to manufacture a thin film semiconductor device capable of adjusting a threshold voltage without causing deterioration of element characteristics due to ion damage defects caused by ion implantation for channel doping. Is to provide a method.

[0022]

A method of manufacturing a thin film semiconductor device according to a broad aspect of the present invention includes a step of forming an insulating layer containing impurities on a substrate and an amorphous layer of a semiconductor on the insulating layer. Steps and irradiating the amorphous layer with an energy beam to diffuse impurities from the insulating layer into the amorphous layer and crystallize the amorphous layer to form a semiconductor crystal layer into which the impurity is introduced. And the process. The term "substrate" as used herein refers to an element that serves as a base on which the element of the thin film semiconductor device is formed,
For example, not only an insulating substrate such as glass or quartz,
It includes a laminate having a protective film formed on the surface thereof.

Further, the energy beam for irradiating the amorphous layer is sufficient to crystallize the amorphous layer,
Further, it is possible to use a material capable of heating the entire substrate to such an extent that thermal distortion does not occur, such as a laser beam or an electron beam.

In the method of manufacturing a thin film semiconductor device according to the limited aspect of the present invention, the step of forming the insulating layer containing impurities includes the step of forming the insulating layer on the substrate and the step of doping the insulating layer with impurities. And a process. Here, as a method for doping the insulating layer with impurities, for example, an ion implantation method or an ion shower method can be used.

Furthermore, in the method of manufacturing a thin film semiconductor device according to another limited aspect of the present invention, the step of forming the insulating layer containing impurities includes the step of directly forming an insulating film doped with impurities on the substrate. It is characterized by including.

Furthermore, a method of manufacturing a thin film semiconductor device according to another broad aspect of the present invention includes a step of forming an impurity-containing region by doping an impurity in the vicinity of the surface of a substrate, and a semiconductor non-contact on the surface of the impurity-containing region. The step of forming a crystalline layer and irradiating the amorphous layer with an energy beam to diffuse the impurities from the impurity-containing region into the amorphous layer and crystallize the amorphous layer to introduce the impurities. And a step of forming a semiconductor crystal layer.

A method of manufacturing a thin film semiconductor device according to another aspect of the present invention is a method of manufacturing a device in which a plurality of regions are provided on the same substrate and a semiconductor element is formed in each region. The semiconductor devices in the two areas are
It is characterized by being manufactured by the following steps. That is, a step of forming an insulating layer containing impurities on a substrate, a step of forming an amorphous layer of a semiconductor on the insulating layer, and irradiating the amorphous layer with an energy beam to form an amorphous layer from the insulating layer. It is manufactured by a step of diffusing impurities in the layer and crystallizing the amorphous layer to form a semiconductor crystal layer having impurities introduced therein.

A method of manufacturing a thin film semiconductor device according to still another aspect of the present invention is a method of manufacturing a device in which a plurality of regions are provided on the same substrate and a semiconductor element is formed in each region. The semiconductor device in one region is manufactured by the following steps. That is, by doping an impurity near the surface of the substrate to form an impurity-containing region, forming an amorphous layer on the surface of the impurity-containing region, and irradiating the amorphous layer with an energy beam. It is manufactured by a step of diffusing impurities from the impurity-containing region into the amorphous layer and crystallizing the amorphous layer to form a semiconductor crystal layer into which the impurities are introduced.

Further, in a method of manufacturing a thin film semiconductor device according to another aspect of the present invention, a first surface region in which a first semiconductor element is formed and a second surface element in which a second semiconductor element is formed are formed.
A method of manufacturing a thin film semiconductor device in which a first semiconductor element and a second semiconductor element are formed on a surface of a substrate having a surface region of, and is characterized by including the following steps. That is, a step of forming an insulating layer in which impurities are added to the first surface region and the second surface region, or a step of doping impurities in the vicinity of the surface of the substrate to form an impurity-containing region; A step of forming an amorphous layer of a semiconductor on the containing region; and irradiating the amorphous layer with an energy beam to crystallize the amorphous layer, and at the same time, the amorphous layer from the insulating layer and the impurity containing region. And diffusing impurities therein to form different impurity-doped regions in the channel region of the first semiconductor element and the channel region of the second semiconductor element. Here, the different impurity-added regions mean channel-doped regions having different kinds or concentrations of impurities.

In the method of manufacturing a thin film semiconductor device according to the above-described limited aspect of the invention, the first semiconductor element is a first conductivity type thin film transistor element, and the second semiconductor element is a second conductivity type thin film transistor element. It is characterized by being.

[0031]

In a wide aspect of the method of manufacturing a thin film semiconductor device according to the present invention, a semiconductor crystal layer having impurities introduced therein can be formed. As the method, first, an insulating layer or an impurity-containing region containing an impurity serving as an impurity diffusion source is formed in advance, and an amorphous layer of a semiconductor is formed thereon. And
By heating these layers, crystallization of the amorphous layer and thermal diffusion of impurities from the impurity diffusion source are simultaneously performed. Then, energy beam irradiation is used as a heat source for the heat treatment. When the amorphous layer is heated using energy beam irradiation, compared to the case where heat treatment is performed using, for example, a high-temperature heating furnace, the entire substrate is kept amorphous in a low temperature atmosphere. Crystallization of layers and thermal diffusion of impurities can be performed. Therefore, it can be applied to a method of manufacturing a thin film semiconductor device by a low temperature process. Further, since the impurities are introduced into the semiconductor crystal layer by thermal diffusion from the impurity diffusion source, it is possible to prevent the generation of ion damage defects in the semiconductor crystal layer as compared with the case where the impurities are introduced by ion implantation. it can. This makes it possible to form a high-quality semiconductor crystal layer into which desired impurities are introduced.

When the present invention is applied to the formation of the channel region of a thin film transistor, the threshold voltage of the thin film transistor can be controlled by adjusting the impurity concentration of the semiconductor crystal layer forming the channel region. Table 1 shows the relationship between the impurity doped in the channel region of the thin film transistor and the threshold voltage.

[0033]

[Table 1]

For example, when the channel region of the p-channel TFT is lightly doped with B (boron), the threshold voltage can be lowered. Further, the impurity concentration of the channel region can be adjusted by adjusting the impurity concentration of the insulating layer serving as the impurity diffusion source or the impurity-containing region.

Furthermore, when the present invention is applied to a method of manufacturing a part of a plurality of semiconductor elements formed on the same substrate, a semiconductor element with channel doping and a semiconductor element without channel doping are used. It can be formed on the same substrate. Therefore, the threshold voltage can be adjusted according to the application of the semiconductor element.

When applied to a thin film semiconductor device having a first conductivity type thin film transistor element and a second conductivity type thin film transistor element on the same substrate, the kind or concentration of impurities contained in the impurity diffusion source of each thin film transistor element is appropriately set. By setting, the threshold voltage of each thin film transistor element can be set to a desired value.

[0037]

Embodiments of the present invention will now be described in detail with reference to the drawings. First Embodiment First, a first embodiment in which the method of manufacturing a thin film semiconductor device of the present invention is applied to a TFT will be described. Figure 1 shows a TFT
FIG. The TFT is formed on a substrate 1 such as non-alkali glass with an insulating thin film 2 interposed.
The TFT has a pair of impurity regions 8 and 8, an element active layer 14 having a channel region 16 formed between them, and a gate electrode 6 formed on the element active layer 14 via a gate insulating layer 5. ing. In the pair of impurity regions 8 and 8,
Extraction electrodes 11, 1 made of Al (aluminum) or the like through contact holes 10 formed in the protective insulating layer 9.
1 is connected.

In this TFT, a substrate dope layer 13 serving as a diffusion source of impurities for channel doping such as B, P or As is formed on the surface of the protective insulating layer 2 which is a base layer of the element active layer 14. ing. Then, the channel region 16 is channel-doped with impurities thermally diffused from the substrate-doped layer 13, whereby T
The threshold voltage of the FT is adjusted.

Here, the p-channel T having the above structure
The manufacturing method in the case where the FT is channel-doped with B as an impurity for adjusting the threshold voltage is mainly described, and an additional manufacturing method of the n-channel TFT will be described with reference to FIGS.

First, as shown in FIG. 2, an insulating thin film 2 made of SiO ₂ or the like is formed on a substrate 1 made of non-alkali glass by CVD or sputtering. As a specific example of this step, Corning 7059 is used for the substrate, and the surface of the substrate is formed at a temperature of 350 ° C. by the atmospheric pressure CVD method.
Then, a SiO ₂ film 2 having a film thickness of 3000 Å is deposited. The thickness of the SiO ₂ film 2 is preferably about 1000 to 6000Å, and the film thickness is such that impurities in the substrate 1 will not pass through the SiO ₂ film 2 and diffuse to the upper layer due to heat treatment or beam irradiation in a later step. Is set.

Subsequently, a resist is applied on the insulating thin film 2 and patterned to form a resist mask 15, and the resist mask 15 is used to ion-implant a region where an element active layer to be channel-doped is formed. By B
A substrate dope layer 13 is formed by implanting impurities 12 such as P, As or the like. As a specific example of this step, the film thickness of the resist 15 is formed to about 1 μm. The implantation of impurity ions was performed with B ⁺ at an accelerating voltage of 5 to 30 keV and a dose amount of 2 × 10 ^{11 to} 5 × 10 ¹² cm ⁻² .

Next, as shown in FIG. 3, a semiconductor thin film 14a to be an element active layer is deposited by CVD or sputtering. Further, the surface of the semiconductor thin film 14a is irradiated with the energy beam 17.

In a specific example of this step, the semiconductor thin film 14a
As a result, an a-Si film having a film thickness of 500 Å is formed at a forming temperature of 450 ° C. by a low pressure CVD method using Si ₂ H ₆ . Subsequently, XeCl having a wavelength λ = 308 nm was formed on the surface of the a-Si film.
An excimer laser beam is scanned to perform annealing, and the a-Si film is melted and recrystallized to form a polycrystalline Si thin film 14.
To form. The laser conditions at this time are shown in Table 2.

[0044]

[Table 2]

When the surface of the a-Si film is irradiated with an excimer laser, the amorphous silicon is melted and recrystallized to become polycrystalline Si. At the same time, the impurity B in the substrate dope layer 13 formed on the surface of the insulating thin film 2 is thermally diffused into the polycrystalline Si thin film which is melted and recrystallized by heating by irradiation of the excimer laser to form the channel dope region 16a. The B atom concentration of the channel dope region 16a is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ by appropriately setting the impurity ion implantation condition and the laser irradiation condition into the underlying substrate doped layer 13.
It could be changed in the range of cm ^-3 .

Further, as shown in FIG. 4, melt recrystallization
The polycrystalline Si film formed by
By further patterning, the channel dope region 16a is formed.
The formed element active layer 14 is formed. In addition, element activation
SiO on the surface of layer 14, etc. ₂And SiN_XInsulation film such as
A gate insulating film 5 made of is deposited.

As a concrete example of this step, the gate insulating film 5 is formed.
As a film thickness of 1 at a formation temperature of 450 ° C. by an atmospheric pressure CVD method
A 000Å SiO ₂ film was deposited. Further, as shown in FIG. 5, a gate electrode 6 made of polycrystalline Si or a metal such as Ti, Mo, or Ta is formed.
B (n channel T
In the case of FT, impurities 18 such as P or As are implanted into the element active layer 14. Then, the implanted impurities are subsequently activated by heat treatment or beam irradiation to form the source / drain regions 8, 8.

As a concrete example of this step, first, Si ₂ H ₆
By the low pressure CVD method using the above, an a-Si film having a film thickness of 1000 Å was formed at a formation temperature of 450 ° C., and further patterned by a photolithography process to form the gate electrode 6. Furthermore, ion implantation is used to accelerate B ⁺ to an acceleration voltage of 30 to 50 ke
V, dose amount 2 × 10 ¹⁵ to 2 × 10 ¹⁶ cm ⁻² , and
Then, a XeCl excimer laser was scanned at room temperature for ² shots at an irradiation energy density of 300 mJ / cm ² ,
The gate electrode 6 of a-Si was melted and recrystallized to be polycrystallized, and the implanted impurity B was activated.

Further, as shown in FIG. 6, SiO ₂ and S
A protective insulating layer 9 made of iN _X or the like is deposited, and contact holes 10 are formed on the source / drain regions 8 and 8.
After opening 10, the extraction electrodes 11, 11 made of Al (aluminum) or the like are formed.

As a specific example of this step, a protective insulating layer is formed by atmospheric pressure CVD at a forming temperature of 350 ° C. and a film thickness of 7000.
Å PSG (Phospho-Silicate Glass) is formed, a contact hole is opened by a photolithography process, an Al film having a film thickness of 0.8 to 1 μm is deposited by a vacuum deposition method, and further patterned by a photolithography process. An extraction electrode was formed.

Through the above steps, a p-channel TFT (or an n-channel TFT) is completed. In the TFT manufactured by the above process, the channel region 16 which is channel-doped by the impurities thermally diffused from the substrate dope layer 13 formed in the insulating thin film 2 which is the base layer of the element active layer 14 is provided. Has been formed. Moreover, for thermal diffusion of impurities, a laser irradiation step for melting and recrystallizing the a-Si layer to form the element active layer 14 of polycrystalline Si is used. Since the laser beam irradiation can locally heat by beam scanning, the melt recrystallization of the a-Si film and the substrate-doped layer 1 can be performed without exposing the entire substrate to high temperature.
The thermal diffusion of impurities from 3 can be performed. Moreover, unlike the conventional channel doping method, the ion implantation method is not used, so that ion damage defects do not occur near the surface of the channel region. Therefore, the threshold voltage of the TFT can be controlled and the T caused by the ion damage defect can be controlled.
It is possible to eliminate the characteristic deterioration of the FT. FIG. 7 shows the relationship between the B doping amount and the threshold voltage of each of the n-channel and p-channel TFTs when the channel region is doped with B by applying the manufacturing process of this embodiment. As is clear from FIG. 7, in the p-channel TFT, the threshold voltage tends to decrease substantially linearly as the concentration of B atoms doped in the channel region increases, and the n-channel TF
At T, conversely, the threshold voltage tends to increase linearly in proportion to the B atom concentration. It can be seen that in any of the TFTs, the threshold voltage changes almost linearly with changes in the B atom concentration with which the channel region is doped, so that the threshold voltage can be easily controlled by the B atom concentration.
Further, with respect to B, the change in the threshold voltage of the p-channel TFT is more sensitive than that of the n-channel TFT.

When the channel region is doped with an n-type impurity such as P or As, the changes in the concentration of the doped atoms and the threshold voltage show the opposite tendency.
That is, in the p-channel TFT, the threshold voltage increases as the n-type atomic concentration increases, and conversely, the n-channel T
In FT, the threshold voltage tends to decrease.

Further, FIG. 8 shows a comparison between the drain current _ID -gate voltage V _G characteristic of the TFT to which the manufacturing process of this embodiment is applied and the same characteristic of the TFT by the conventional process. T of Conventional Example 1 without channel doping
In the FT, the threshold voltage is particularly high in the p-channel TFT, and the absolute values of the threshold voltages of the n-channel TFT and the p-channel TFT are greatly different and they are not matched.
Further, in the TFT of Conventional Example 2 in which channel doping is performed by ion implantation, although the threshold voltage is improved, on / off characteristics, particularly off current and subthreshold characteristics are deteriorated.

On the other hand, in the TFT of this embodiment, the threshold voltage of the p-channel TFT is improved so that it is particularly low, and the p-channel TFT and the n-channel TFT are improved.
The absolute values of the threshold voltages of are matched almost equally.
Moreover, the deterioration of the on / off characteristics is significantly improved as compared with the conventional example 2 in which channel doping is performed by ion implantation.

In the manufacturing process shown in FIGS. 2 to 6, when a quartz substrate is used as the insulating substrate 1,
It is not necessary to form the insulating thin film 2 on the surface of the substrate. That is, the insulating thin film 2 is provided in order to prevent impurities such as sodium contained in the glass substrate from diffusing into the upper element active layer under a high temperature atmosphere of the manufacturing process and exerting an adverse effect. . However, quartz does not contain such impurities. Therefore,
In this case, the substrate dope layer 13 serving as an impurity diffusion source to the channel region is directly formed on the surface of the quartz substrate 1. Then, in the laser annealing process shown in FIG.
Impurities diffuse into the channel region from the substrate doped layer 13 formed directly on the surface.

Second Embodiment A second embodiment in which the thin film semiconductor device manufacturing method of the present invention is applied to a TFT will be described.

FIG. 9 is a sectional structural view of a TFT according to the second embodiment, and FIGS. 10 to 14 are manufacturing process diagrams showing the manufacturing process in the order of processes. The TFT according to the second embodiment has substantially the same structure as the TFT shown in FIG. 1 except for the structure near the channel. Therefore, in the cross-sectional structure diagram shown in FIG. 9, the elements denoted by the same reference numerals as those in FIG. 1 are the same as the configuration of the TFT according to the first embodiment, and therefore the repetitive description is omitted here.

In the TFT according to the second embodiment, an impurity-doped insulating layer 19 containing impurities for channel doping is formed below the channel region 16. And
The channel region 6 is channel-doped with the impurities diffused from the impurity-doped insulating layer 19.

Hereinafter, the p-channel TF having the above structure will be described.
T (B) as an impurity for adjusting the threshold voltage
A method of manufacturing an n-channel TFT will be mainly described with reference to a manufacturing method in the case of performing channel doping.

First, as shown in FIG. 10, an insulating thin film 2 made of SiO ₂ or the like is adhered and formed on a substrate 1 such as a non-alkali glass, and then an insulating film to which B, P or As is added in a small amount. Form the layer 19a.

In a concrete example of this step, Corning 7059 is used as a substrate, and a SiO ₂ film (N) having a film forming temperature of 350 ° C. and a film thickness of 3000 Å is first formed thereon by atmospheric pressure CVD.
SG) 2 is deposited. Successively, by a normal pressure CVD method, a forming temperature of 350 ° C. and a film thickness of 300 to 500 Å, B-doped SiO
_Two films (BSG) 19a are deposited. At this time, BS
The B atom concentration of G was set to 2 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 11, a photolithography process is used to pattern the insulating layer 19a to form an impurity-doped insulating layer 19 in a region where an element active layer to be channel-doped is to be formed. Subsequently, a semiconductor thin film 14a to be an element active layer is deposited on the insulating thin film 2 and the impurity-doped insulating layer 19. Then, the semiconductor thin film 14a
The surface of the semiconductor thin film 14 is irradiated with the energy beam 17.
a is melted and recrystallized, and impurities are diffused from the impurity-doped insulating layer 19 to form the channel-doped region 16a.
To form.

In a specific example of this process, first, the BSG film 19a is patterned by a normal photolithography process, and then a low pressure CVD method using Si ₂ H ₆ is carried out on the BSG film 19a at a formation temperature of 450 ° C. and a film thickness of 500Å. -Si film 14a is formed. Then, XeCl excimer laser (λ = 308n
By the scanning annealing of m), the a-Si film was melted and recrystallized to form the polycrystalline Si thin film 14. The laser irradiation conditions at this time were set to be the same as the conditions shown in Table 2 of the first embodiment. By this laser annealing, the impurities contained in the impurity-doped insulating layer 19 are thermally diffused in the upper polycrystalline Si thin film to form the channel-doped region 16a. For this reason, a channel-doped region having a good crystallinity and slightly doped with impurities was formed without causing an ion damage defect. The B atom concentration in the polycrystalline Si thin film in the impurity-doped channel region is
Depending on the doping conditions of the impurity-doped insulating layer 19 and the laser irradiation conditions, for example, it could be appropriately changed within the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ .

Further, as shown in FIG. 12, the semiconductor thin film 14a in which the channel dope region 16a is formed is patterned by a normal photolithography process to form the device active layer 14
To form. Further, a gate insulating film 5 made of SiO ₂ , SiN _x or the like is deposited thereon.

In a specific example of this step, the gate insulating film is formed by atmospheric pressure CVD at a formation temperature of 450 ° C. and a film thickness of 100.
A 0Å SiO ₂ film was deposited. Further, as shown in FIG. 13, a gate electrode 6 made of polycrystalline Si or a metal such as Ti, Mo, Ta is formed, and the gate electrode 6 is used as a mask to perform B (n-channel TF) by ion implantation or the like.
In the case of T, impurities 18 such as P, As) are implanted.
Then, the implanted impurities are activated by heat treatment or beam irradiation to form the source / drain regions 8, 8.

In a specific example of this step, first, a film thickness of 1 is formed at a forming temperature of 450 ° C. by a low pressure CVD method using Si ₂ H _6.
A 000 Å a-Si film was formed and patterned into a gate electrode shape by a photolithography process to form a gate electrode 6. Subsequently, B ⁺ is accelerated by an ion implantation method at an acceleration voltage of 30 to 50 keV and a dose amount of 2 × 10 ¹⁵ to 2 × 10 ¹⁶ c.
m ⁻² and then beam irradiation with XeCl excimer laser at room temperature at 350 mJ / cm ² and ² shots to melt and recrystallize the gate electrode 6 of a-Si and activate the injected impurity B. Was made.

Further, as shown in FIG. 14, a protective insulating layer 9 made of SiO ₂ or SiN _{x is} deposited and formed, and the contact hole 1 is formed on the source / drain regions 8 and 8.
Open 0 and 10. After that, extraction electrodes 11, 11 of aminium or the like are formed to complete the thin film semiconductor element.

In a specific example of this step, the protective insulating layer is formed by atmospheric pressure CVD at a forming temperature of 350 ° C. and a film thickness of 7,000 Å.
PSG is formed and a contact hole is opened by a photolithography process, and then a film thickness of about 0.8 to 1 μm is formed by a vacuum deposition method.
Then, the aluminum film was deposited and the extraction electrode was formed in the photolithography process.

TFT manufactured by the above manufacturing method
In the same manner as the TFT of the first embodiment, the threshold voltage is accurately controlled by performing channel doping with a desired impurity concentration without causing ion damage defects. Moreover, there is no increase in off-current or deterioration in subthreshold characteristics. Such characteristics are
It has been made clear under various conditions that the same characteristics as those of FIGS. 7 and 8 for the first embodiment are exhibited.

As in the first embodiment, when a quartz substrate is used as the insulating substrate 1, it is not necessary to form the insulating thin film 2 on the substrate. Then, in this case, the impurity-doped insulating layer 19 serving as an impurity diffusion source to the channel region is directly formed on the quartz substrate.

Third Embodiment Next, an example in which the manufacturing process of the thin film semiconductor device according to the first and second embodiments is applied to CMOS will be described.
FIG. 15 is a sectional view of the CMOS, and FIGS.
0 is a manufacturing process explanatory view showing the manufacturing process in order.

First, as shown in FIG.
n-channel TFT 100a and p-channel TFT 100b
And are connected in series. C according to the example shown
The MOS is an n-channel TFT 100a and a p-channel TF.
An example is shown in which both T100b are channel-doped. For example, the n-channel TFT 100a is manufactured by using the channel doping method according to the first embodiment, and the p-channel TFT 100b is manufactured by using the channel doping method according to the second embodiment.

Hereinafter, the manufacturing method of the CMOS will be described to explain the device structure of the CMOS at the same time. First, as shown in FIG. 16, an insulating thin film 102 is deposited on a substrate 101 such as non-alkali glass, and then an insulating layer 103 to which B, P, As or the like is added in a trace amount is deposited. Form. The insulating thin film 102 is formed for the purpose of preventing impurity diffusion from the substrate 101 to the element active layer in a later process.

In a specific example in this step, Corning 7059 is used as a substrate, and a SiO ₂ film (NS) having a film formation temperature of 350 ° C. and a film thickness of 3000 Å is first formed thereon by atmospheric pressure CVD.
G) is deposited. Subsequently, a B-doped SiO ₂ film (BSG) having a film formation temperature of 350 ° C. and a film thickness of 300 to 500 Å was deposited by the atmospheric pressure CVD method. At this time, the B atom concentration of BSG was set to 2 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 17, the resist 10 is used.
4 is formed in a pattern that remains on the region where the p-channel side element active layer is formed and has an opening on the region where the n-side element active region is formed. And
Using the resist 104 as a mask, the insulating layer 103 with a slight amount of impurities added is etched to remove the insulating layer 103 on the region where the element active layer on the n-channel side is formed. Further, using the resist 104 as a mask, ions of any of impurities such as B, P, and As are ion-implanted to form a substrate dope layer 106 in a region near the surface of the insulating thin film 102. By this step, the insulating layer 103 to which a small amount of B, P or As is added remains in the region where the element active layer on the p-channel side is formed, and the element active layer on the n-channel side is left. A substrate doped layer 106 is formed in the formed region. It should be noted that the insulating layer 103 and the substrate-doped layer 106 can appropriately set the type and concentration of impurities. That is, it is possible to change the kind of impurities to each other, and it is also possible to change the concentration of impurities to be doped in each layer.

In a specific example of this step, a resist is first applied to a film thickness of about 1 μm and patterned to form a resist mask, and then the BSG 103 is patterned by dry etching with CHF ₃ . Further, with the resist 104 left, B ⁺ is accelerated at an acceleration voltage of 5 to 30 ke.
Ion implantation was performed in a range of V and dose of 2 × 10 ^{11 to} 5 × 10 ¹² cm ⁻² to form the substrate-doped layer 106.

Further, as shown in FIG. 18, a semiconductor thin film 107 to be an element active layer is adhered and formed, and an energy beam 108 is irradiated. In a specific example of this process, Si ₂ H
An a-Si film having a film thickness of 500Å is formed at a forming temperature of 450 ° C. by a low pressure CVD method using ₆ . Subsequently, the a-Si film was melted and recrystallized by scanning annealing with a XeCl excimer laser (λ = 308 nm) to form a polycrystalline Si thin film. The laser conditions at this time were set in the same manner as the conditions of Table 2 in the first embodiment. As a result, in the process of melt recrystallization of the a-Si film, the impurities contained in the substrate dope layer 106 thermally diffuse into the upper layer during melt recrystallization. As a result, the channel regions 117a and 117b having good crystallinity and being slightly doped with impurities were formed without causing ion damage defects. This polycrystalline Si
In the n-channel TFT, the B atom concentration in the thin film depends on the implantation conditions of the underlying substrate dope layer 106 and the p-channel T
In the FT, 1 × 10 6 was obtained depending on the doping condition of the insulating layer 103 added with impurities and the laser irradiation condition.
It could be changed in the range of ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ . In the above example, the case was explained in which the BSG concentration and B implantation were combined as the channel doping conditions on the n-channel side and the p-channel side. However, depending on the control range of the threshold voltage, BSG and P may be used. Implantation, PSG and B implantation, or a combination of PSG and P implantation may be used.

Further, as shown in FIG. 19, after patterning the semiconductor thin film 107 by a photolithography process to form element active layers 107a and 107b, the gate insulating film 1 is formed.
09 is deposited, and the gate electrode 110 is formed thereon. Further, first, by ion implantation, P ⁺ is implanted into the region of the element active layer 107a on the n-channel side to form the source / drain regions 112 and 112 of the n-channel TFT, and thereafter, the element active layer 107b on the p-channel side. B ⁺ ions are implanted into the regions to form the source / drain electrodes 113, 113 of the p-channel TFT. Incidentally, at the time of ion implantation on either the n-channel side or the p-channel side,
The surface on the other channel side is masked with a resist.
After the ion implantation is performed, heat treatment or beam irradiation is performed to activate the implanted impurities.

In a specific example of this step, first, the semiconductor thin film 107 is formed into an island by a photolithography step, and then a gate insulating film is formed at a formation temperature of 450 by atmospheric pressure CVD.
A SiO ₂ film having a film thickness of 1000 Å was formed by deposition. Further, a low pressure CVD method using Si ₂ H ₆ was used to form an a-Si film having a film thickness of 1000 Å at a forming temperature of 450 ° C., and a gate electrode was formed by using a photolithography process. Next, P ⁺ is added to the element active layer 107a on the n-channel side with an acceleration voltage of 90 to 120 keV and a dose of 2 × 10 ¹⁵ to 2 × 1.
0 ¹⁶ cm ^-2 , and the element active layer 107b on the p-channel side
Is B ⁺ for acceleration voltage 30 to 50 keV, dose 2 × 1
Ion implantation was performed at 0 ^{15 to} 2 × 10 ¹⁶ cm ^-2 . Then, it was annealed by a XeCl excimer laser at room temperature under the conditions of 300 mJ / cm ² and ² shots to melt and recrystallize the a-Si gate electrode and activate the implanted impurities.

Further, as shown in FIG. 20, after depositing a protective insulating layer 114, contact holes 115, 1 are formed.
15 and the take-out electrodes 116, 116 are sequentially formed to complete a channel-doped CMOS. In a specific example of this step, PSG having a film thickness of 7,000 Å is formed as a protective insulating layer by an atmospheric pressure CVD method at a forming temperature of 350 ° C.
After opening the contact hole by photolithography process,
An aluminum film having a film thickness of 0.8 to 1 μm was formed by vacuum deposition, and a take-out electrode was patterned by using a photolithography process.

Fourth Embodiment Further, another example in which the manufacturing process of the thin film semiconductor device according to the first and second embodiments is applied to CMOS will be described. FIG. 21 is a sectional structural view of the CMOS.
26A to 26C are manufacturing process explanatory views showing the manufacturing process in order.

In the CMOS according to this example, unlike the third embodiment, the n-channel TFT 100a is manufactured by using the channel doping method according to the second embodiment, and the p-channel T100a is manufactured.
The FT 100b is manufactured using the channel doping method according to the first embodiment.

Hereinafter, the manufacturing method will be described in accordance with the CMOS manufacturing process, and at the same time, the CMOS device structure will be described. First, as shown in FIG. 22, after depositing an insulating thin film 102 on a substrate 101 such as non-alkali glass, a small amount of B, P, As or the like for adjusting a threshold voltage is added. Insulating layer 122
a is deposited. The insulating thin film 102 is formed for the purpose of preventing impurity diffusion from the substrate 101 to the element active layer in a later process.

In a specific example in this step, Corning 7059 is used as a substrate, and a SiO ₂ film (NS) having a film forming temperature of 350 ° C. and a film thickness of 3000 Å is first formed on the substrate by atmospheric pressure CVD.
G) is deposited. Subsequently, a B-doped SiO ₂ film (BSG) having a film formation temperature of 350 ° C. and a film thickness of 300 to 500 Å was deposited by the atmospheric pressure CVD method. At this time, the B atom concentration of BSG was set to 2 × 10 ^{16 to} 5 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 23, the resist 10 is formed only on the region where the element active region on the n-channel side is formed.
4 is formed. Then, using the resist 104 as a mask, the insulating layer 122a added with a slight amount of impurities is etched to form the impurity-doped insulating layer 122 on the region where the element active layer on the n-channel side is formed. Further, using the resist 104 as a mask, an impurity such as B, P, or As is ion-implanted to form a substrate dope layer 123 in the region near the surface of the insulating thin film 102. By this step, the substrate dope layer 123 to which a small amount of B, P or As is added is formed in the region where the element active layer on the p-channel side is formed, and the element active layer on the n-channel side is formed. The impurity-doped insulating layer 122
Is formed.

In the specific example of this step, first, a resist film is formed.
Apply 1 μm thick and pattern to form resist mass
CHF after forming₃For dry etching
Then, the BSG 122a is patterned. In addition, the cash register
B with the strike 104 left ⁺Acceleration voltage 5 to 30 ke
V, dose amount 2 × 10¹¹~ 5 × 10¹²cm^-2In the range
On implantation was performed to form a substrate doped layer 123.

Further, as shown in FIG. 24, a semiconductor thin film 120 to be an element active layer is deposited and formed, and the energy beam 108 is irradiated. In a specific example of this process, Si ₂ H
An a-Si film having a film thickness of 500Å is formed at a forming temperature of 450 ° C. by a low pressure CVD method using ₆ . Subsequently, the a-Si film was melted and recrystallized by scanning annealing with a XeCl excimer laser (λ = 308 nm) to form a polycrystalline Si thin film. The laser conditions at this time were set to the same conditions as those in Table 2 in the first embodiment. As a result, a-S
In the process of melt recrystallization of the i film, the substrate doped layer 12
2 and the impurities contained in the impurity-doped insulating layer 123 are thermally diffused into the upper layer during melt recrystallization. This allows
The channel regions 121a, 1a having good crystallinity and being lightly doped with impurities without causing ion damage defects
21b could be formed. The B atomic concentration in this polycrystalline Si thin film is 1 × depending on the implantation conditions of the underlying substrate doped layer 122 in the n-channel TFT, the doping conditions of the impurity-doped insulating layer 123 in the p-channel TFT, and the laser irradiation conditions. It could be changed in the range of 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ . In this specific example, B is set as the channel doping condition on the n-channel side and the p-channel side.
The case of performing the combination of SG concentration and B implantation has been described, but depending on the control range of the threshold voltage, BSG may be used.
And P implantation, PSG and B implantation, or PSG and P implantation in combination.

Further, as shown in FIG. 25, the semiconductor thin film 120 is patterned to form the element active layers 120a and 120a.
After forming b, a gate insulating film 109 is deposited and a gate electrode 110 is formed thereon. Further, first, the element active layer 120a on the n-channel side is formed by ion implantation.
P ⁺ ions are implanted into the regions to form the source / drain regions 112 and 112 of the n-channel TFT, and then B ⁺ ions are implanted into the element active layer 120b on the p-channel side to source / drain electrodes of the p-channel TFT. 113,11
3 is formed. During ion implantation on either the n-channel side or the p-channel side, the surface on the other channel side is masked with a resist. Then, after the ion implantation is performed, the implanted impurities subjected to the heat treatment or the beam irradiation are activated.

In a specific example of this step, first, the semiconductor thin film 120 is formed into an island by a photolithography step, and then a gate insulating film is formed at a forming temperature of 450 by an atmospheric pressure CVD method.
A SiO ₂ film having a film thickness of 1000 Å was deposited at ℃. Further, a low pressure CVD method using Si ₂ H ₆ was used to form an a-Si film having a film thickness of 1000 Å at a forming temperature of 450 ° C., and a gate electrode was formed by using a photolithography process. Next, P ⁺ is added to the element active layer 120a on the n-channel side with an acceleration voltage of 90 to 120 keV and a dose amount of 2 × 10 ¹⁵ to 2 × 1.
0 ¹⁶ cm ^-2 , and the element active layer 120b on the p-channel side
Is B ⁺ for acceleration voltage 30 to 50 keV, dose 2 × 1
Ion implantation was performed at 0 ^{15 to} 2 × 10 ¹⁶ cm ^-2 . Then, it was annealed by a XeCl excimer laser at room temperature under the conditions of 300 mJ / cm ² and ² shots to melt and recrystallize the gate electrode of a-Si and activate the implanted impurities.

Further, as shown in FIG. 26, after depositing a protective insulating layer 114, contact holes 115, 1 are formed.
15 and the take-out electrodes 116, 116 are sequentially formed to complete a channel-doped CMOS. In a specific example of this step, PSG having a film thickness of 7,000 Å is formed as a protective insulating layer by an atmospheric pressure CVD method at a forming temperature of 350 ° C.
After opening the contact hole by photolithography process,
An aluminum film having a film thickness of 0.8 to 1 μm was formed by vacuum deposition, and a take-out electrode was patterned by using a photolithography process.

In the above third and fourth embodiments,
The mask pattern used for channel doping can be reduced as compared with the conventional CMOS manufacturing process. That is, in the conventional CMOS manufacturing process, as shown in FIG.
Although the photolithography process for forming the resist 24a shown in FIG. 5 and the photolithography process for forming the resist 24b shown in FIG. 36 are required twice, in the above-described embodiment, the photolithography process shown in FIGS. As shown in FIG. 23, the same process is performed by one photolithography process. Therefore, simplification of the CMOS manufacturing process can be realized.

In the third and fourth embodiments, a quartz substrate can be used as the insulating substrate 1. In this case, it is not necessary to form the insulating thin film 102, and the substrate dope layers 106 and 123 are formed on the surface of the quartz substrate.

[0093]

As described above, in the method of manufacturing a thin film semiconductor device according to the present invention, an amorphous layer of a semiconductor is irradiated with an energy beam so that an impurity diffusion source formed below the amorphous layer is removed. High quality semiconductor crystal that does not cause ion damage defects due to low temperature process because it is configured to thermally diffuse impurities and recrystallize the amorphous layer to form a semiconductor crystal layer into which desired impurities are introduced. Layers can be obtained.

Furthermore, when this semiconductor crystal layer is used for a thin film semiconductor device having a channel region, the on / off characteristics of the thin film semiconductor element are not deteriorated due to ion damage defects, and a desired threshold voltage is obtained. An adjusted thin film semiconductor device can be obtained.

Further, for example, when the method of the present invention is applied to CMOS, a p-channel TFT and an n-channel TF are used.
A CMOS with low power consumption can be obtained by matching the threshold voltage of each T.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process explanatory view showing one process of manufacturing the thin film transistor shown in FIG.

FIG. 3 is a manufacturing process explanatory view showing one process of manufacturing the thin film transistor shown in FIG.

FIG. 4 is a manufacturing process explanatory view showing one process of manufacturing the thin film transistor shown in FIG.

FIG. 5 is a manufacturing process explanatory view showing one process of manufacturing the thin film transistor shown in FIG.

FIG. 6 is a manufacturing process explanatory view showing one process of manufacturing the thin film transistor shown in FIG.

FIG. 7 is a characteristic diagram of B atom concentration versus threshold voltage of a thin film transistor.

FIG. 8 is a characteristic diagram showing a relationship between gate voltage and drain current of a thin film transistor.

FIG. 9 is a sectional structural view of a thin film transistor according to a second embodiment of the present invention.

FIG. 10 is a manufacturing process explanatory view showing a step of the manufacturing process of the thin film transistor shown in FIG. 9;

11 is a manufacturing process explanatory view showing one process of manufacturing the thin film transistor shown in FIG. 9. FIG.

12 is a manufacturing process explanatory view showing one process of manufacturing the thin film transistor shown in FIG. 9. FIG.

13 is a manufacturing process explanatory view showing one process of manufacturing the thin film transistor shown in FIG. 9. FIG.

14 is a manufacturing process explanatory view showing one process of manufacturing the thin film transistor shown in FIG. 9. FIG.

FIG. 15 is a sectional structural view of a CMOS according to a third embodiment of the present invention.

16 is a manufacturing process explanatory view showing one process of the manufacturing process of the CMOS shown in FIG. 15; FIG.

17 is a manufacturing process explanatory view showing one process of the manufacturing process of the CMOS shown in FIG. 15; FIG.

FIG. 18 is a manufacturing process explanatory view showing one process of the manufacturing process of the CMOS shown in FIG. 15;

FIG. 19 is a manufacturing process explanatory view showing one process of the manufacturing process of the CMOS shown in FIG. 15;

20 is a manufacturing process explanatory view showing one process of the manufacturing process of the CMOS shown in FIG. 15; FIG.

FIG. 21 is a sectional structural view of a CMOS according to the fourth embodiment of the present invention.

22 is a manufacturing process explanatory view showing one process of the manufacturing process of the CMOS shown in FIG. 21; FIG.

23 is a manufacturing process explanatory view showing one process of the manufacturing process of the CMOS shown in FIG. 21; FIG.

24 is a manufacturing process explanatory view showing one process of the manufacturing process of the CMOS shown in FIG. 21; FIG.

25 is a manufacturing process explanatory view showing one process of the manufacturing process of the CMOS shown in FIG. 21; FIG.

FIG. 26 is a manufacturing process explanatory view showing one process of the manufacturing process of the CMOS shown in FIG. 21;

FIG. 27 is a cross-sectional structural diagram of a conventional thin film transistor.

FIG. 28 is a manufacturing process explanatory view showing one process of a conventional manufacturing process of a thin film transistor.

FIG. 29 is a manufacturing process explanatory view showing one process of manufacturing a conventional thin film transistor.

FIG. 30 is a manufacturing process explanatory view showing one process of a conventional manufacturing process of a thin film transistor.

FIG. 31 is a manufacturing process explanatory view showing one process of manufacturing a conventional thin film transistor.

FIG. 32 is a manufacturing process explanatory view showing one process of manufacturing a conventional thin film transistor.

FIG. 33 is a sectional structural view of a conventional CMOS.

FIG. 34 is a manufacturing process explanatory view showing one process of the conventional CMOS manufacturing process.

FIG. 35 is a manufacturing process explanatory view showing one process of the conventional CMOS manufacturing process.

FIG. 36 is a manufacturing process explanatory view showing one process of the conventional CMOS manufacturing process.

FIG. 37 is a manufacturing process explanatory view showing one process of the conventional CMOS manufacturing process.

FIG. 38 is a manufacturing process explanatory view showing one process of the conventional CMOS manufacturing process.

FIG. 39 is a manufacturing process explanatory view showing one process of the conventional CMOS manufacturing process.

[Explanation of symbols]

1, 101 ... Substrate 2, 102 ... Insulating thin film 5, 109 ... Gate insulating layer 6, 110 ... Gate electrode 17, 108 ... Excimer laser beam 14, 107a, 107b ... Element active layer 13, 106, 123 ... Substrate dope layer 19, 103, 122 ... Impurity-doped insulating layer 16, 117a, 117b, 121a, 121b ... Channel region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/8238 H01L 27/08 321B 27/092 29/78 618F 27/08 331

Claims (9)

[Claims] 1. A step of forming an insulating layer containing impurities on a substrate, a step of forming an amorphous layer of a semiconductor on the insulating layer, and irradiating the amorphous layer with an energy beam Diffusing the impurities from the insulating layer into the amorphous layer and crystallizing the amorphous layer to form a semiconductor crystal layer into which the impurities are introduced. Device manufacturing method. 2. The step of forming the insulating layer containing impurities includes a step of forming an insulating layer on the substrate, and a step of doping the insulating layer with impurities. A method of manufacturing a thin film semiconductor device according to. 3. The thin film semiconductor according to claim 1, wherein the step of forming the insulating layer containing impurities includes the step of directly forming an insulating film doped with impurities on the substrate. Device manufacturing method. 4. A step of forming an impurity-containing region by doping an impurity near a surface of a substrate; a step of forming an amorphous layer of a semiconductor on the surface of the impurity-containing region; Diffusing the impurities from the impurity-containing region into the amorphous layer by irradiating with an energy beam, and crystallizing the amorphous layer to form a semiconductor crystal layer into which the impurities are introduced. A method of manufacturing a thin film semiconductor device, comprising: 5. The manufacturing of a thin film semiconductor device according to claim 1, wherein at least a part of the semiconductor crystal layer having impurities introduced therein constitutes a channel region of a thin film transistor. Method. 6. A method of manufacturing a thin film semiconductor device, wherein a plurality of regions are provided on the same substrate, and a semiconductor element is formed in each region, wherein at least one semiconductor element in the region is an impurity on the substrate. A step of forming an insulating layer including a step of forming an amorphous layer of a semiconductor on the insulating layer, and irradiating the amorphous layer with an energy beam so that the inside of the amorphous layer And a step of crystallizing the amorphous layer to form a semiconductor crystal layer into which impurities are introduced, while manufacturing the thin film semiconductor device. 7. A method of manufacturing a thin film semiconductor device, wherein a plurality of regions are provided on the same substrate, and a semiconductor element is formed in each region, wherein at least one semiconductor element in the region is near a surface of a substrate. Forming an impurity-containing region by doping impurities into the impurity-containing region, forming an amorphous layer on the surface of the impurity-containing region, and irradiating the amorphous layer with an energy beam to form the impurity-containing region. A thin film semiconductor device manufactured by a process of diffusing the impurities into the amorphous layer and crystallizing the amorphous layer to form a semiconductor crystal layer into which the impurities are introduced. Manufacturing method. 8. A first semiconductor element and a second semiconductor on a surface of a substrate having a first surface area on which a first semiconductor element is formed and a second surface area on which a second semiconductor element is formed. A method of manufacturing a thin film semiconductor device having an element formed, wherein an insulating layer doped with impurities is formed in the first surface region and the second surface region, or impurities are added in the vicinity of the substrate surface. Forming an impurity-containing region by doping, forming a semiconductor amorphous layer on the insulating layer and the impurity-containing region, and irradiating the amorphous layer with an energy beam, The amorphous layer is crystallized, and the impurities are diffused from the insulating layer and the impurity-containing region into the amorphous layer to form a channel region of the first semiconductor element and a channel region of the second semiconductor element. At each other And a step of forming different impurity-added regions on the substrate. 9. The thin film semiconductor according to claim 8, wherein the first semiconductor element is a first conductivity type thin film transistor element, and the second semiconductor element is a second conductivity type thin film transistor element. Device manufacturing method.