JPH04315441A - Manufacture of thin-film transistor - Google Patents

Abstract

PURPOSE:To provide good transistor characteristics even if active layers are formed as thin as tens of nanometers in a thin-film polysilicon planar transistor for switching devices or peripheral devices of a liquid crystal display. CONSTITUTION:Sources (4a and 4b) of impurity diffusion are selectively formed on a glass substrate, and a semiconductor layer on the substrate is annealed for crystallization. The impurity is diffused from the sources into the semiconductor layer on the substrate to form source and drain regions 8a and 8b (lightly doped source/drain region in the case of LDD TFT). On the other hand, that region of the semiconductor layer, above which no diffusion source exists, is crystallized to form an undoped active layer 7. According to this method, source and drain regions with uniform impurity concentration even in a semiconductor layer that is as thin as tens of nanometers. As a result, it is possible to provide a polysilicon thin-film transistor (or LDD TFT) having uniform characteristics.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing thin film transistors used in liquid crystal display devices and the like.

0002

2. Description of the Related Art Polycrystalline silicon thin film transistors have higher mobility than amorphous silicon thin film transistors and are therefore being researched and developed as peripheral circuit devices for liquid crystal display elements.

As a method for improving the performance of this polycrystalline silicon thin film transistor, a method has been proposed in which the thickness of the semiconductor layer is reduced to several tens of nanometers.

A method for manufacturing a planar thin film transistor will be described with reference to FIG. First, as shown in FIG. 3A, a silicon thin film with a thickness of several tens of nanometers is formed on a glass substrate 1, and then crystallized by a laser annealing method to form a semiconductor layer 5b having an island-like structure. Next, as shown in FIG. 3(b), by forming and patterning a silicon dioxide thin film and an aluminum thin film,
A gate oxide film 9 and a gate electrode 10 are formed. Then, as shown in FIG. 3(c), after implanting phosphorus ions 3 into the entire surface of the substrate, annealing is performed, and the source/drain regions 8a,
Form 8b. Here, the term source/drain region is used as a general term for the source region and the drain region. Furthermore, a protective film and electrodes (not shown) are formed. Furthermore, polycrystalline silicon thin film transistors have the disadvantage of large leakage current, which poses a problem when used as switching elements of liquid crystal display elements or peripheral circuit elements.

As a means of reducing leakage current of this polycrystalline silicon thin film transistor, a semiconductor layer is formed between the active layer and the source/drain electrodes, and the conductivity type of the semiconductor is the same as that of the source/drain region, and the impurity concentration is lower than that of the source/drain region. A lightly doped drain (LDD) structure has been proposed.

A method for manufacturing an LDD structure thin film transistor will be described with reference to FIG. First, as shown in FIG. 4A, high impurity concentration source/drain electrodes 11a and 11b made of polycrystalline silicon films are formed on a glass substrate 1. Next, as shown in FIG. 4(b), after forming a silicon thin film 15 with a thickness of several tens of nanometers, excimer laser light 1
3 to perform crystallization and pattern it into an island-like structure. Next, as shown in FIG. 4(c), a silicon dioxide thin film and an aluminum thin film are formed and patterned.
A gate oxide film 9 and a gate electrode 10 are formed. Then, as shown in FIG. 4D, phosphorus ions 3 are implanted into the entire surface of the substrate at a low concentration, and then annealing is performed to form low impurity concentration source/drain regions 14a and 14b. Furthermore, a protective film and electrodes (not shown) are formed.

[0007]

[Problems to be Solved by the Invention] As mentioned above, in order to improve transistor characteristics, it is desirable to thin the semiconductor layer to about several tens of nanometers, but it is necessary to implant impurity ions into a silicon thin film of about several tens of nanometers. In order to achieve this, the implantation must be performed at low energy. However, low-energy, high-dose implantation is difficult because of problems such as charge-up. These problems become more noticeable on an insulating substrate, resulting in non-uniform transistor characteristics. In particular, in LDD transistors, these problems become more noticeable because the source and drain regions with low impurity concentration are formed by ion implantation, resulting in the problem that the transistor characteristics become even more non-uniform.

Furthermore, when forming source/drain regions (low impurity concentration source/drain regions in LDD transistors) by ion implantation, impurity ions are also implanted into the gate electrode, causing damage to the MOS structure below the gate electrode. It happens. High-temperature annealing is required to recover the defects that occur at this time, but if a low-melting glass substrate is used, high-temperature annealing cannot be performed, making it difficult to recover the defects and risking deterioration of transistor characteristics.

An object of the present invention is to eliminate problems in the conventional manufacturing method of planar thin film transistors, to make the impurity concentration in the source and drain regions uniform even when the semiconductor layer is thinned to several tens of nanometers, and to maintain the MOS structure. It is an object of the present invention to provide a method for manufacturing a thin film transistor that can form a polycrystalline silicon thin film transistor having good characteristics without causing damage to the thin film transistor.

Another object of the present invention is to eliminate problems in the conventional manufacturing method of LDD structure thin film transistors, and to reduce the impurity concentration of low impurity concentration source/drain regions even when the semiconductor layer is thinned to several tens of nanometers. Make it uniform,
It is an object of the present invention to provide a method for manufacturing a thin film transistor that can form a polycrystalline silicon thin film transistor having low leakage current and good characteristics without damaging a MOS structure.

[0011]

[Means for Solving the Problems] A method for manufacturing a thin film transistor according to the first invention of the present application includes the steps of selectively forming a pair of impurity-containing regions facing each other at a predetermined distance on the surface of an insulating substrate; A step of forming a semiconductor layer spanning a pair of impurity-containing regions, and a step of annealing the semiconductor layer to diffuse impurities into portions in contact with the pair of impurity-containing regions to form a source region and a drain region. It is said that it has.

[0012] The method for manufacturing a thin film transistor according to the second aspect of the present invention also includes the step of selectively forming a pair of impurity-containing regions facing each other at a predetermined distance on the surface of an insulating substrate; forming a high impurity concentration source region and a high impurity concentration drain region made of polycrystalline silicon films doped with impurities in advance on the regions; and forming a semiconductor layer over the high impurity concentration source region and the high impurity concentration drain region. a step of forming a layer;
The method includes the step of annealing the semiconductor layer to diffuse impurities into portions in contact with the pair of impurity-containing regions to form a low impurity concentration source region and a low impurity concentration drain region.

[0013]

[Operation] In the first invention, by annealing the semiconductor layer by a laser annealing method or the like, when crystallizing the semiconductor layer, the impurities introduced into the insulating substrate diffuse into the semiconductor layer, so that the source/drain regions are Formation takes place simultaneously. In addition, since impurities are introduced into the semiconductor layer by diffusing the impurities in the insulating substrate through annealing such as laser annealing, the uniformity of the impurity concentration in the source and drain regions can be improved by direct ion implantation into the semiconductor layer. This can be improved compared to the conventional case, and the electrical characteristics of the transistor can be made uniform. Furthermore, since the gate oxide film and gate electrode are formed after forming the source/drain regions by annealing such as laser annealing, the formation of the source/drain regions does not damage the MOS structure, resulting in good transistor characteristics. is obtained.

Similarly, in the second invention, the impurity introduced into the insulating substrate is diffused into the semiconductor layer when crystallizing the semiconductor layer by annealing the semiconductor layer using a laser annealing method or the like. Formation of impurity-concentrated source and drain regions is performed at the same time. In addition, since impurities are introduced into the semiconductor layer by diffusing the impurities in the insulating substrate through annealing such as laser annealing, the uniformity of the impurity concentration in the low impurity concentration source/drain regions can be directly transferred to the semiconductor layer. This can be improved compared to the case of ion implantation, and the electrical characteristics of the transistor can be made uniform. Furthermore, since the gate oxide film and gate electrode are formed after the low impurity concentration source/drain regions are formed by annealing such as laser annealing, the formation of the low impurity concentration source/drain regions does not damage the MOS structure. Therefore, good transistor characteristics can be obtained.

[0015]

[Embodiment] An embodiment of the first invention of the present application will be described with reference to FIG. FIG. 1(e) is a cross-sectional view of a planar polycrystalline silicon thin film transistor manufactured according to the first invention of the present application. is implanted, an active layer 7 and source/drain regions 8a, 8b are formed on the glass substrate 1, and a gate oxide film 9 and a gate electrode 10 are formed on the active layer 7.

First, as shown in FIG. 1A, a resist is applied onto a glass substrate 1 such as quartz glass, and then patterned by photolithography to form a mask 2 for ion implantation. Next, as shown in FIG. 1(b), phosphorus ions 3 are implanted using an ion implanter (the implantation amount is 10 to the 16th power (1E1) per 1 square centimeter.
It is written as 6. (hereinafter, the same applies) and an acceleration voltage of 40 kV) impurity-containing regions 4a and 4b are formed. Furthermore, Figure 1(c)
As shown in FIG. 2, an amorphous silicon thin film is formed to a thickness of 50 nm by LPCVD, and then patterned by photolithography to form a semiconductor layer 5a having an island-like structure.
form. Next, as shown in FIG. 1D, the entire surface of the substrate is irradiated with laser light (XeCl excimer laser) to melt and crystallize the amorphous silicon layer to form a polycrystalline silicon film. At this time, the amorphous silicon film on the impurity-containing regions 4a, 4b is crystallized and at the same time becomes an n-type high impurity concentration (source/drain regions 8a, 8b) due to the diffusion of phosphorus from the impurity-containing regions 4a, 4b. Further, the amorphous silicon layer not located on the impurity-containing regions 4a and 4b is crystallized and becomes a non-doped active layer 7. Furthermore, after forming a silicon dioxide thin film of 200 nm on the substrate surface by the LPCVD method, a 100 nm thick polycrystalline silicon thin film doped with phosphorus was successively formed by the LPCVD method, and patterned by the photolithography method.
A gate oxide film 9 and a gate electrode 10 are formed on the active layer 7. Furthermore, a protective film and electrodes (not shown) are formed.

In this way, after forming an impurity diffusion source (impurity-containing region) on the glass substrate, laser annealing is performed on the amorphous silicon layer to perform impurity diffusion at the same time as crystallization, thereby forming the active layer and source/drain regions. By using the simultaneous formation method, source and drain regions can be easily formed in a silicon thin film of approximately several tens of nanometers. Further, since the gate oxide film and the gate electrode are formed after forming the active layer and the source/drain electrodes, the MOS structure is not deteriorated by ion implantation or the like, and good transistor characteristics can be manufactured.

Next, an embodiment of the second invention of the present application will be described.

FIG. 2(e) shows an LDD manufactured according to the present invention.
1 is a cross-sectional view of a structured polycrystalline silicon thin film transistor,
As shown in the figure, a pair of impurity-containing regions 4a and 4b are formed on the surface of the glass substrate 1, and on top of these, high impurity concentration source/drain regions 11a and 11b and low impurity concentration source/drain regions 11a are formed. , 11b and an active layer 7 are formed, and a gate oxide film 9 and a gate electrode 10 are formed on the active layer 7.

First, as shown in FIG. 2A, a resist is applied onto a glass substrate 1 made of quartz glass or the like, and then patterned by photolithography to form a mask 2 for ion implantation. Next, phosphorus ions 3 are implanted using an ion implantation device (implantation amount: 1E16 per square centimeter, acceleration voltage: 40 kV) to form impurity-containing regions 4a and 4b. Next, as shown in FIG. 2(b), a polycrystalline silicon thin film doped with phosphorus is formed on the glass substrate 1 by LPCVD, and then patterned by photolithography to form highly impurity-concentrated source/drain regions 11a. , 11b are formed. Furthermore, Figure 2
As shown in (c), an amorphous silicon thin film is formed to a thickness of 50 nm by LPCVD, and then patterned by photolithography to form a semiconductor layer (amorphous silicon layer 12) having an island-like structure. next,
As shown in FIG. 2(d), the laser beam 13 (X
The amorphous silicon layer 12 is melted and crystallized by irradiation with eCl excimer laser to form a polycrystalline silicon film. At this time, impurity-containing regions 4a, 4 which serve as phosphorus diffusion sources
At the same time as the amorphous silicon layer on b crystallizes,
The diffusion of phosphorus results in n-type low impurity concentration source/drain regions 14a and 14b. In addition, the amorphous silicon layer that is not on the diffusion source is crystallized and becomes a non-doped active layer 7.
becomes. Furthermore, as shown in FIG. 2(e), L
After forming a silicon dioxide thin film to a thickness of 200 nm using the PCVD method, a 100 nm thick polycrystalline silicon film doped with phosphorus was successively formed using the LPCVD method, and patterning was performed using a photolithography method to form a gate oxide film 9 on the active layer 7. and gate electrode 10 is formed. Furthermore, a protective film and electrodes (not shown) are formed.

After forming an impurity diffusion source on the glass substrate in this way, laser annealing is performed on the amorphous silicon layer to perform impurity diffusion at the same time as crystallization, thereby forming an active layer and low impurity concentration source/drain regions at the same time. By using this method, it was possible to easily form low impurity concentration source/drain regions in a silicon thin film of approximately several tens of nanometers. In addition, the active layer and source
Since the gate oxide film and the gate electrode were formed after forming the drain electrode, the MOS structure was not deteriorated by ion implantation or the like, and good transistor characteristics could be manufactured.

In the above explanation, phosphorus ion implantation is used to form the diffusion source, but similar effects can be obtained by forming the diffusion source by other methods such as vapor deposition or by using other dopants. can get.

Furthermore, when forming the active layer and source/drain electrodes, laser annealing is performed after forming an amorphous silicon thin film, but the same effect can be obtained by using a polycrystalline silicon thin film instead of the amorphous silicon thin film. Similar effects can also be obtained by using a method such as a solid phase growth method instead of the laser annealing method.

[0024]

As explained above, according to the first invention of the present application, after forming an impurity diffusion source on an insulating substrate such as a glass substrate, a semiconductor layer with a thickness of several tens of nanometers is provided, and annealing is performed. By simultaneously forming the active layer and the source/drain regions by applying this process, it is possible to form a polycrystalline silicon thin film transistor with good transistor characteristics and uniformity.

According to the second invention of the present application, after forming an impurity diffusion source on an insulating substrate, a semiconductor layer with a thickness of several tens of nanometers is provided, and annealing is performed to form an active layer and a low impurity layer. By simultaneously forming the doped source and drain regions, it is possible to form a polycrystalline silicon thin film transistor with low leakage current, good transistor characteristics, and uniformity.

[Brief explanation of the drawing]

[Fig. 1] To explain one embodiment of the first invention of the present application (a
) to (e) are step-by-step sectional views shown separately.

[Fig. 2] To explain one embodiment of the second invention of the present application (a
) to (e) are step-by-step sectional views shown separately.

3A to 3C are cross-sectional views in the order of steps for explaining a conventional method for manufacturing a planar thin film transistor; FIGS.

4A to 4D are cross-sectional views in the order of steps shown in sections (a) to (d) for explaining a method of manufacturing a conventional LDD structure thin film transistor.

[Explanation of symbols]

1 Glass substrate 2 Mask 3 Phosphorus ions 4a, 4b Impurity-containing regions 5a, 5b Semiconductor layer 6 Laser light 7 Active layers 8a, 8b Source/drain regions 9 Gate oxide film 10 Gate electrodes 11a, 11b High impurity concentration source/drain regions 12 Amorphous Silicon layer 13 Laser beams 14a, 14b Low impurity concentration source/drain regions 15 Polycrystalline silicon thin film

Claims (2)

[Claims] 1. A step of selectively forming a pair of impurity-containing regions facing each other at a predetermined distance on a surface portion of an insulating substrate, and a step of forming a semiconductor layer spanning the pair of impurity-containing regions. and a step of annealing the semiconductor layer to diffuse impurities into portions in contact with the pair of impurity-containing regions to form a source region and a drain region. 2. A step of selectively forming a pair of impurity-containing regions facing each other at a predetermined distance on a surface portion of an insulating substrate, and polycrystalline silicon doped with an impurity in advance on each of the pair of impurity-containing regions. a step of forming a high impurity concentration source region and a high impurity concentration drain region made of a film, a step of forming a semiconductor layer spanning the high impurity concentration source region and the high impurity concentration drain region, and annealing the semiconductor layer. A method for manufacturing a thin film transistor, comprising the step of: diffusing impurities into portions in contact with the pair of impurity-containing regions to form a low impurity concentration source region and a low impurity concentration drain region.