JP3190841B2 - Forward staggered thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a forward staggered thin film transistor and a method of manufacturing the same, and more particularly, to a thin film transistor formed on a general-purpose glass substrate for application to a liquid crystal display, a contact type image sensor, a fluorescent display tube, and the like. The present invention relates to a forward staggered thin film transistor including a thin film transistor array formed using a thin film transistor, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, with the cost reduction and high definition of the liquid crystal display and the like, an active element having a faster switching operation than a hydrogenated amorphous silicon thin film transistor conventionally used for driving a liquid crystal. Is required, and its realization is required. As one of them, development of a polycrystalline silicon thin film transistor in which a polycrystalline silicon thin film formed by an excimer laser annealing method is formed as an active layer thereof has been advanced. Excimer laser annealing is a method in which a silicon thin film formed on a glass substrate is irradiated with an excimer laser, which is an ultraviolet / short pulse laser, to melt and recrystallize only the silicon thin film or anneal defects. And a method of obtaining a high quality polycrystalline silicon thin film. In this method, since ultraviolet / short-pulse laser is used, laser absorption is performed only on the silicon surface and does not cause thermal damage to the substrate, so that high-temperature processing of silicon is possible. Therefore, the substrate material includes
It is also possible to use general-purpose glass having a low softening point.

The structure of a thin film transistor using such a polycrystalline silicon thin film includes a planar type, a forward stagger type, and a reverse stagger type, but a forward stagger type transistor (for example, K. Sera, et al. Extende).
d Abstracts of 1991 Inter
national Conference on So
lid State Device and Mate
reals, Yokohama, 1991, pp590
-592) is characterized in that a leakage current can be reduced as compared with a planar transistor or the like. FIG. 4 is a cross-sectional view of an example of a conventional thin film transistor using a polycrystalline silicon thin film.
A gate electrode 5, a gate insulating film 4, an active layer Poly-Si6, and n in which phosphorus is implanted into a glass substrate 1.
^{+ A} silicon layer 9 and a WSi (tungsten silicide: hereinafter abbreviated as WSi using an atomic symbol) 7 are formed by lamination.

[0004]

The above-mentioned conventional thin film transistor using a polycrystalline silicon thin film has the following drawbacks in terms of its structure and production.

First, in terms of the structure, there is a structural step in the active layer / drain (or source) coupling region C in the cross-sectional view of the conventional thin film transistor of FIG. Due to this step, an uneven electric field distribution is induced in the source / drain direction and the gate / drain direction during the operation of the thin film transistor. Such an excessive concentration of the electric field on the drain end lowers the resistance of the thin film transistor, and has a drawback that the driving voltage and the reliability may deteriorate the performance. Due to its structure, even in the manufacturing process, during the patterning of the source / drain regions, non-uniformity of the taper angle at the end and variation of the deposited thickness of the active layer due to the step occur, and the non-uniformity of the breakdown voltage and There is a disadvantage that it leads to variation in transistor characteristics.

A second point is that, in the case of a thin film transistor formed through a laser annealing step, after forming and patterning an n ⁺ layer or a p ⁺ layer as a source / drain electrode layer, a silicon layer for forming a channel layer is formed. Through a process of depositing a layer and irradiating a laser. In this case, in the conventional example, since the thicknesses of the Si layers in the regions A and B in FIG. 4 are different, a difference occurs in the temperature process in the laser annealing process, and the crystal structure of Si in the regions A and B is different. There is a problem that is different. This is also confirmed by the fact that the optimum irradiation intensity that gives the highest mobility changes when a thin film transistor having a different channel layer thickness is manufactured in a planar thin film transistor. That is, the optimum irradiation intensity increases as the thickness of the channel layer increases. Therefore, the laser annealing conditions at that time were changed to the region A
If the conditions for setting the channel region are set to the optimum conditions, the thickness of the silicon layer in the region B becomes larger than the thickness of the silicon layer in the region A, so that the heat capacity becomes larger. As a result, polycrystalline silicon having low crystallinity is formed. As a result, the carrier conduction characteristics of the region B are lower than the carrier conductivity of the region A, which has the disadvantage that the performance of the thin film transistor to be formed is reduced and the variation in characteristics is promoted.

[0007]

Means for Solving the Problems At least a source / drain region, a semiconductor film, and a semiconductor film are sequentially formed on an insulating substrate.
In a thin film transistor including a gate insulating film and a gate electrode, the semiconductor film is disposed above a low-resistance silicon layer serving as the source / drain region,
Configure the channel region. Further, the thickness t1 of the semiconductor film in the channel region, and the thickness t2 of the semiconductor film disposed above the source / drain region and the thickness t3 of the source / drain region have a relationship of t1 = t2 + t3. Features.

[0008]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a cross-sectional structure of a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, a gate electrode 5, a gate insulating film 4, a semiconductor film 3, and a source / drain layer 2 are stacked on a glass substrate 1. As shown in FIG. 1, the feature of the present invention is that the semiconductor film 3 and the gate insulating film 4
Is that there is no step at the interface between them.

Generally, the source / drain breakdown voltage decreases due to impact ionization of carriers caused by excessive electric field concentration at the drain end. Therefore, by alleviating the electric field concentration near the drain end, it is possible to prevent a decrease in breakdown voltage. In the conventional forward staggered thin film transistor, as described in the above-mentioned subject, since there is a step as shown in a region C of FIG. 4, an electric field in the gate-drain direction and an electric field in the source-drain direction are present. Are in a state of being easily concentrated in a complex manner.
However, in the present invention, since the steps are eliminated as shown in FIG. 1, it is possible to prevent the electric field concentration caused by the steps. Also, in the manufacturing process, in the conventional example, a change in the taper angle at the pattern edge of the source / drain film also causes a change in the step shape, which causes instability in the manufacturing. In this embodiment, since no step is formed as shown in FIG. 1, it is possible to prevent the variation in the electric field concentration due to the above-mentioned step shape. Therefore, according to the present invention, a high electric field region associated with a step is reduced, and a decrease in withstand voltage is prevented.

Next, the procedure for forming the staggered thin film transistor of the first embodiment shown in FIG. 1 will be described. First, an amorphous silicon film is deposited on a non-alkali glass substrate 1, and phosphorus (P) is implanted into a source / drain region by an ion implantation method. In the case of the conventional example, patterning of the source / drain layers is performed at this stage. In this embodiment, an amorphous silicon film serving as a channel layer is stacked without performing patterning. Next, the amorphous silicon film is polycrystallized by a solid phase growth method to form a channel layer and activate the source / drain layer 2. After that, silicon dioxide is laminated as the gate insulating film 4,
Aluminum is laminated as the gate electrode 5 to manufacture a thin film transistor. This allows mobility:
61 (cm ² / Vsec) and a threshold value of 2.6 (V). As is clear from the drain current-drain voltage characteristics shown in FIG.
As described above, a thin film transistor having a source / drain withstand voltage extremely higher than that of a conventional thin film transistor having a step is realized.

FIG. 2 is a view showing a lamination cross section of a second embodiment of the present invention. As shown in FIG.
On a glass substrate 1, a gate electrode 5, a gate insulating film 4, an active layer Poly-Si6, an n ⁺ silicon layer 9 into which phosphorus (P) is implanted, a silicon layer 9 and a WSi layer laser-annealed as formed. 7 are laminated. The processing procedure in this embodiment is as follows. A WSi layer 7 is formed as a source / drain electrode layer on a glass substrate 1 of an OA-2 substrate manufactured by Nippon Electric Glass Co., Ltd. Patterning is performed by lithography and dry etching. Next, the amorphous silicon layer is formed by a low pressure chemical vapor deposition (hereinafter referred to as LP).
After depositing 75 (nm) at 550 ° C. by a CVD method, phosphorus (P) is ion-implanted into a portion below the channel region using a photoresist as a mask, and n ⁺
A silicon layer 9 is formed. After the source / drain regions are formed as described above, a semiconductor film made of an a-Si thin film to be an active layer is formed by LPCVD at 550 ° C.
5 (nm) is deposited and irradiated with an excimer laser to form an active layer P.
Poly-Si6 is formed. Laser irradiation conditions were as follows: intensity: 450 mJ / cm ² , laser irradiation frequency per location: 5 shots. By excimer laser irradiation, the semiconductor film becomes polycrystalline silicon, and electric conductivity is improved.

Conventionally, the remaining silicon layer 8 was removed by etching without performing the above ion implantation. However, according to the present invention, the silicon layer 8 exists below the active layer together with the source / drain regions. Therefore, it exhibits the same thermal characteristics as the source / drain regions. Therefore, at the time of laser annealing, the thermal energy absorbed by the semiconductor film 3 composed of the a-Si thin film deposited as an active layer is uniformly diffused and heated in the silicon layer 8 and the source / drain regions. Thereby, in the active layer region between the source and the drain, a uniform polycrystalline silicon layer is formed in the horizontal direction. After that, the silicon dioxide layer for forming the gate insulating film 4 is formed to a thickness of 120 (nm) by LPCVD.
An aluminum layer for forming the gate electrode 5 is formed to a thickness of 3000 (nm) by a sputtering method. By forming the thin film transistor group over 150 (mm) square in this manner, the mobility: 3.6
(Cm ² / Vsec), threshold value: 2.6 (V) ± 0.08
A thin film transistor having high mobility and high uniformity was manufactured in the range of (V) and a variation of approximately ± 3%. According to the conventional method, although the mobility of about 140 (cm ² / Vsec) has been obtained, the distribution of the characteristics has spread to about ± 10%, and the uniformity of the characteristics is poor. In contrast to this, in this embodiment, a highly uniform laser-annealed staggered thin film transistor can be manufactured.

Although the embodiments of the present invention have been described above, the film forming method is not limited to the LPCVD method and the sputtering method as described above, but may be a deposition method, a plasma CVD method, or a normal pressure CVD method. It goes without saying that the present invention can be effectively applied even if other means are used. Also, the present invention can be effectively applied to a case where other means such as an ion doping method and a laser doping method are used as the ion implantation means.

[0015]

As described above, the present invention provides at least a source / drain layer, a semiconductor film,
A gate insulating film and a gate electrode are sequentially laminated, and a boundary surface between the semiconductor film and the gate insulating film is flattened from the source / drain region to a predetermined channel region. Laser annealing of the source / drain region and the channel region.
The process can be performed uniformly,
There is an effect that a forward staggered thin film transistor having uniform characteristics and higher carrier traveling characteristics can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a laminate according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a laminate according to a second embodiment of the present invention.

FIG. 3 is a diagram showing drain current / drain voltage characteristics.

FIG. 4 is a cross-sectional view of a conventional example.

[Explanation of symbols]

Reference Signs List 1 glass substrate 2 source / drain layer 3 semiconductor film 4 gate insulating film 5 gate electrode 6 active layer Poly-Si 7 WSi layer 8 silicon layer 9 n ⁺ silicon layer

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-83939 (JP, A) JP-A-1-105577 (JP, A) JP-A-4-324683 (JP, A) JP-A-4- 334065 (JP, A) JP-A-5-41519 (JP, A) JP-A-58-206163 (JP, A) JP-A-60-202931 (JP, A) JP-A-60-245124 (JP, A)

Claims (2)

(57) [Claims] (1)The semiconductor film formed on the insulating substrate is
After forming the first semiconductor film that forms the lower layer of the semiconductor film,
The upper layer of the semiconductor film formed on the first semiconductor film is
A second semiconductor film to be formed, The first semiconductor thin films are opposed to each other via a gap.
Drain layer comprising a first conductivity type impurity region and a saw
Layer is formed, A gate insulating film formed on the second semiconductor film; The gap and at least the drain on the gate insulating film;
Gate electrode formed to cover part of the source and source layers.
With poles, At least the channel layer, the drain end and the source end
The thickness of the semiconductor film to be formed is the first semiconductor film.
Equal to the sum of the thickness and the thickness of the second semiconductor, And before
The second semiconductor film was formed through a laser irradiation step.
A staggered thin film transistor characterized by the above-mentioned. 2. The staggered thin film transistor according to claim 1, wherein said semiconductor thin film is a crystalline silicon thin film formed through a laser irradiation step.