JPH04370937A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To allow a source-drain region to have a sufficiently low resistance and to make it possible to use an inexpensive glass substrate by conducting an activation annealing at 600 deg.C or lower for a few hours. CONSTITUTION:As to a self-alignedly fabricated thin-film transistor, the thickness of polycrystalline into which ions are to be implanted is 300Angstrom or less and an impurity is doped into a substrate with the substrate being kept at 300 deg.C or above in the ion implantation process.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor.

0002

2. Description of the Related Art One method for improving the characteristics of thin film transistors is to form self-aligned source/drain regions using ion implantation for the purpose of reducing parasitic capacitance. On the other hand, it has been found that it is advantageous to make the polycrystalline silicon film thinner in order to improve the characteristics of thin film transistors. However, if the normal ion implantation method is used when the thickness of the polycrystalline silicon film is 300 Å or less, it will take several tens of hours of heat at 600°C or more to form the source/drain regions, except under certain conditions. Annealing or laser annealing was required. Such thermal annealing does not allow the use of low-cost glass substrates and has poor productivity.

0003

[Problems to be Solved by the Invention] In thin film transistors manufactured using ion implantation technology, it is desirable to provide a thin film transistor that has sufficiently low resistance even after thermal annealing at temperatures below 600°C for several hours.
We devised an ion implantation method that can form the drain and drain regions, making it possible to use inexpensive glass substrates.

0004

[Means for Solving the Problems] The method of manufacturing a semiconductor device of the present invention is intended to solve the above-mentioned problems, and uses an ion implantation device in a self-aligned thin film transistor formed on an insulating substrate. In the implantation step, the temperature of the insulating substrate is lowered to 30°C.
It is characterized by implanting impurities while maintaining the temperature at 0°C or higher.

[0005]

[Example] Figure 1(a) shows 250 yen immediately after impurity implantation.
FIG. 3 is a diagram showing the relationship between the crystallization rate of a source/drain region having a film thickness of Å and the substrate temperature at the time of implantation. When the substrate temperature is below 300 DEG C., the implanted source/drain regions become amorphous. FIG. 1(b) is a diagram showing the relationship between the sheet resistance of a source/drain region having a film thickness of 250 Å and the activation heat treatment temperature. A line 101 is a sheet resistance curve when a conventional semiconductor device manufacturing method is used. Line 102 shows the case where an ion implantation device is used in the method of manufacturing a semiconductor device according to the present invention, and the substrate temperature is increased by 3.
Line 103, the sheet resistance curve when implanting is performed while maintaining the temperature at 00°C or above, is generated from a gas containing 5% phosphine and the balance consisting of hydrogen gas using an ion implanter that does not use mass spectrometry. This is the case when all ions are implanted while maintaining the substrate temperature at 300°C or higher.
shows the resistance curve. The activation heat treatment time is several hours. FIG. 2 is a cross-sectional view of one embodiment of a thin film transistor manufactured using the method of manufacturing a semiconductor device according to the present invention. A gate made by patterning a substrate 201 such as a glass substrate or a quartz substrate, a silicon oxide film 202, a non-doped polycrystalline silicon 203, a silicon oxide film 204, and an impurity-doped polycrystalline silicon film. Electrode 205, source/drain region 2 formed by impurity implantation
06 shows a silicon oxide film 207 and an electrode wiring 208. The method for manufacturing a semiconductor device of the present invention will be explained below using the process diagram of FIG. First, as shown in FIG. 3A, a silicon oxide film 302 is deposited as an insulating film to a thickness of 2000 Å on a substrate 301 such as a glass substrate or a quartz substrate. The purpose of the insulating film is to prevent heavy metals contained in the substrate from diffusing into the element portion during heat treatment, and it is not necessary as long as the purity of the substrate is sufficiently high. Next, polycrystalline silicon 303 containing no impurities is deposited to a thickness of 250 Å and patterned. A film having a crystallization rate of the polycrystalline silicon of 75% or more, preferably 90% or more is used. Next, a silicon oxide film is deposited to a thickness of 1500 Å to form a gate insulating film 304. Next, polycrystalline silicon containing phosphorus was deposited to a thickness of 3000 Å.
A gate electrode 305 is formed by depositing and patterning to a thickness of . Next, as shown in FIG. 3(b), using the gate electrode as a mask, a phosphorus ion beam 306 is implanted at 110 keV with an arbitrary concentration in the range of 1 x 1015 ions/cm2 to 1 x 1016 ions/cm2. Area 3
07 is formed. During the implantation, the substrate temperature was set at 30°C.
The substrate is heated from the back side so as to be maintained at 0° C. or higher, preferably 400° C. or higher and 500° C. or lower. It is clear that the implantation energy may be adjusted depending on the type of impurity ions and the thickness of the gate insulating film, and is not limited to this embodiment. For example, in the case of boron ions, 40 keV
Just do it. Next, impurities are activated by heat treatment at 600° C. for 1 hour. In the impurity implantation process, all ions generated from a gas containing 5% phosphine and the remainder hydrogen gas are implanted using an ion implantation device that does not use mass spectrometry to form the source/drain region. In order to fill in the asymmetric bonding, it is possible to form source/drain regions at even lower temperatures. Next, as shown in FIG. 3(c), a silicon oxide film with a thickness of 5,000 Å is
The interlayer insulating film 308 is deposited to a thickness of
After opening a contact hole in the drain region, Al
Electrode wiring 309 is performed using ITO or ITO. FIG. 4 is an enlarged cross-sectional view of a source/drain region having a film thickness of 250 Å immediately after impurity implantation using a conventional semiconductor device manufacturing method. Due to the implantation, the polycrystalline silicon film has become amorphous. FIG. 5 is an enlarged cross-sectional view of a source/drain region having a film thickness of 250 Å immediately after impurity implantation using the method of manufacturing a semiconductor device of the present invention. Crystals remain in the film even after implantation. In this way, since the remaining crystals are used as seeds, it is possible to recrystallize at a low temperature and in a short time to lower the resistance.

[0006]

[Effects of the Invention] The present invention has the following effects.

(1). Productivity is improved by achieving low resistance of a thin film of 250 Å or less at a temperature of 600° C. or less and by short-time annealing.

(2). It becomes possible to use an inexpensive glass substrate.

[0009] Furthermore, if an ion implantation device that does not use mass spectrometry is used to implant all ions generated from a gas that is 0% or more and less than 10% impurity, and the remainder is hydrogen gas, Since the hydrogen ions effectively fill the asymmetric bonds, it becomes possible to activate at a lower temperature, and at the same time, it is possible to hydrogenate the channel portion of the thin film transistor, improving the characteristics of the thin film transistor.

[Brief explanation of the drawing]

FIG. 1(a) is a diagram showing the relationship between the crystallization rate of the source/drain region of a thin film transistor immediately after impurity implantation and the substrate heating temperature during implantation. (b) is
FIG. 3 is a diagram showing the relationship between the sheet resistance of the source/drain region and the activation heat treatment temperature.

FIG. 2 is a cross-sectional view of an embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a process diagram of one embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 4 is an enlarged cross-sectional view of a source/drain region immediately after impurity implantation using a conventional semiconductor device manufacturing method.

FIG. 5 is an enlarged cross-sectional view of the source/drain region immediately after impurity implantation when using the method of manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

101 Sheet resistance curve of the source/drain region when a conventional semiconductor device manufacturing method is used 102 Source/drain region when an ion implantation device is used in the semiconductor device manufacturing method of the present invention Sheet resistance curve 103 of the source/drain region when an ion implantation device that does not use mass spectrometry is used in the semiconductor device manufacturing method of the present invention 201 Substrate 202 Silicon oxide film 203 Non-doped - polycrystalline silicon 204 silicon oxide film 205 gate electrode 206 source/drain region 207 silicon oxide film 208 electrode wiring 301 substrate 302 silicon oxide film 303 impurity-free polycrystalline silicon 304
Gate insulating film 305 Gate electrode 306 Phosphorous ion beam 307 Source/drain region 308 Interlayer insulating film 309 Electrode wiring

Claims (2)

[Claims] 1. A self-aligned thin film transistor formed on an insulating substrate, comprising a step of forming source/drain regions by implanting impurity ions using an ion implantation device, the implanting step comprising:
A method for manufacturing a semiconductor device, comprising implanting impurities while maintaining the temperature of an insulating substrate at 300° C. or higher. 2. In the method for manufacturing a semiconductor device according to claim 1, all ions generated from a gas consisting of 0% or more and less than 10% impurity gas and the remainder hydrogen gas, A method for manufacturing a semiconductor device, characterized in that implantation is performed using an ion implanter that does not use mass spectrometry.