JP3173126B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a thin film transistor.

[0002]

2. Description of the Related Art One of the methods for improving the characteristics of a thin film transistor is to form a self-aligned source / drain region using an ion implantation method for reducing a parasitic capacitance. On the other hand, it has been found that thinning the polycrystalline silicon film is advantageous for improving the characteristics of the thin film transistor. However, when the thickness of the polycrystalline silicon film becomes 500 ° or less, using an ordinary ion implantation method, except for specific conditions, the activation of the impurities in the source / drain regions takes more than tens of hours at 600 ° C. or more. Thermal annealing or laser
Annealing was required. In such thermal annealing, a low-cost glass substrate cannot be used, and productivity is poor.

[0003]

SUMMARY OF THE INVENTION In a thin film transistor manufactured by using the ion implantation technique, an ion implantation method has been devised in which a source / drain region having sufficiently low resistance can be formed even by thermal annealing at 600 ° C. or less for several hours. In addition, it is possible to use an inexpensive glass substrate.

[0004]

According to a method of manufacturing a thin film transistor of the present invention, a gate electrode is formed on a silicon film serving as a source / drain region via an insulating film in a method of manufacturing a thin film transistor formed on a substrate. And a step of implanting all ions generated from a mixed gas composed of a gas serving as an impurity and a helium gas into the silicon film using an ion implantation apparatus that does not use mass spectrometry. And implanting the impurity ions while maintaining the temperature of the substrate at 200 ° C. or more and 500 ° C. or less. Further, in the method of manufacturing a thin film transistor according to the present invention, the silicon film may have a thickness of 25%.
It is characterized in that the film thickness is not less than 0 Å and not more than 500 Å. Further, the method for manufacturing a thin film transistor according to the present invention is characterized in that, in the method for manufacturing a thin film transistor, a mixed gas in which the gas serving as the impurity is less than 10%. Further, in the method of manufacturing a thin film transistor according to the present invention, the temperature of the substrate is set to 300 ° C. or more and 50 ° C.
The temperature is set to 0 ° C. or lower. Further, in the method for manufacturing a thin film transistor according to the present invention, in the method for manufacturing a thin film transistor, after implanting the impurity ions,
Annealing is performed at a temperature of not less than 00 ° C. and not more than 600 ° C.

[0005]

FIG. 1 is a diagram showing the relationship between the sheet resistance of a source / drain region having a thickness of 250 ° and the activation heat treatment temperature. A line 101 is a sheet resistance curve of the source / drain region of the thin film transistor when the impurity is implanted by using the conventional ion implantation method. Line 102
In a method for manufacturing a thin film transistor according to the present invention, a thin film transistor containing 5% of phosphine and implanting all ions generated from a gas consisting of helium gas is implanted using an ion implantation apparatus without mass spectrometry. 4 shows an example of a sheet resistance curve of a source / drain region. FIG. 2 is an enlarged cross-sectional view of a source / drain region having a thickness of 250 ° immediately after impurity implantation when a conventional ion implantation method is used. The polycrystalline silicon film is made amorphous by the ion implantation. FIG. 3 is an enlarged sectional view of a source / drain region having a thickness of 250 ° immediately after impurity implantation when the method of manufacturing a thin film transistor according to the present invention is used. Even after impurity implantation, the source / drain regions are not amorphized,
The resistance can be reduced at a low temperature in a short time. FIG.
1 is a cross-sectional view of one embodiment of a thin film transistor manufactured by using the method of manufacturing a thin film transistor according to the present invention. Substrate 401 such as glass substrate or quartz substrate, insulating film 4
02, non-doped polycrystalline silicon 403, a gate insulating film 404, a gate electrode 405 formed by patterning a metal such as a polycrystalline silicon film doped with impurities or Cr, and source / drain regions 406 formed by implanting impurities. , An interlayer insulating film 407, and an electrode wiring 408 from a source / drain region.

(Embodiment 1) An embodiment of a method of manufacturing a thin film transistor according to the present invention will be described below with reference to the process chart of FIG. First, as shown in FIG. 5A, a silicon oxide film 502 is deposited on a substrate 501 such as a glass substrate or a quartz substrate as an insulating film to a thickness of 2000 °. The purpose of the insulating film is to prevent heavy metals and the like contained in the substrate from diffusing into the element portion at the time of heat treatment, and the substrate need not have sufficiently high purity. Next, polycrystalline silicon 503 containing no impurity is deposited to a thickness of 250 ° to 500 ° and patterned. As the polycrystalline silicon, a film having a crystallization ratio of 75% or more, preferably 90% or more is used.
Next, a silicon oxide film is deposited to a thickness of 1500 ° to form a gate insulating film 504. Next, polycrystalline silicon containing phosphorus is deposited to a thickness of 3000 ° and patterned to form a gate electrode 505. Next, as shown in FIG.
Using an ion implantation apparatus that does not use mass spectrometry, all ions 506 generated from a mixed gas containing 5% of phosphine and a balance of helium gas are used as a mask with the gate electrode as a mask and at a substrate temperature of 200 ° C. or higher, preferably 30
While maintaining the temperature at 0 ° C. or more and 500 ° C. or less, the phosphorus concentration is 1 × 10 ¹⁵ / cm ² to 1 × with an energy of 110 keV.
The source / drain region 507 is formed by implanting an arbitrary concentration in the range of 10 ¹⁶ / cm ² . The concentration of phosphine in the mixed gas is not particularly limited. However, if the concentration of phosphine exceeds 10%, phosphorus is deposited in the ion implantation apparatus, and the operation rate of the apparatus is reduced. A mixed gas having a phosphorus concentration of less than 10% is used. In addition to the method of adjusting the temperature of the substrate, in addition to the method of heating from the back surface side of the substrate described in the present embodiment, there is a method of performing the implantation while adjusting the ion beam current during the implantation. Further, in the implantation step, the implantation energy is selected according to the type of the impurity ions and the thickness of the gate insulating film, and it is apparent that the implantation energy is not limited to this embodiment. For example, when boron ions are implanted in the ion implantation step, the energy of the implantation may be set to 40 keV by using a gas containing diborane and the balance being helium gas. Next, impurities are activated by thermal annealing at 600 ° C. for 1 hour. Next, as shown in FIG.
A silicon oxide film is deposited to a thickness of 5000.degree., An interlayer insulating film 508 is formed, and a contact hole is opened in the source / drain region.
Perform Step 9.

(Embodiment 2) Another embodiment using the method of manufacturing a thin film transistor according to the present invention will be described below with reference to the process chart of FIG. First, as shown in FIG. 6A, a silicon oxide film having a thickness of 2000 mm is deposited as an insulating film on a substrate such as a glass substrate or a quartz substrate. The purpose of the insulating film is to prevent heavy metals and the like contained in the substrate from diffusing into the element portion at the time of heat treatment, and the substrate need not have sufficiently high purity. Next, polycrystalline silicon 60 containing no impurities
1 is deposited in a thickness of not less than 250 ° and not more than 500 ° and patterned. The polycrystalline silicon has a crystallization ratio of 75.
% Or more, preferably 90% or more. Next, a silicon oxide film is deposited to a thickness of 1500 ° to form a gate insulating film 6.
02 is formed. Next, a gate electrode 603 is formed by depositing a metal film of Cr, Ta, Al, or the like with a thickness of 3000 ° or more and patterning. Next, as shown in FIG. 6B, using an ion implantation apparatus that does not use mass spectrometry,
All ions 604 generated from a gas containing 5% phosphine and the balance being helium gas are used as a mask, using a gate electrode as a mask, at an energy of 110 keV and a phosphorus concentration of 1 × 10 ¹⁵ / cm ² to 1 × 10 ^16. The source / drain region 605 is formed by implanting at an arbitrary concentration in the range of / cm ² . The substrate temperature was set at 2
The temperature is maintained at 00 ° C or higher, preferably 300 ° C or higher and 500 ° C or lower. The method of adjusting the substrate temperature is not particularly limited. In addition to the method of heating from the back side of the substrate shown in the present embodiment, there is a method of performing the implantation while adjusting the ion beam current at the time of the implantation. Next, thermal annealing is performed at 300 ° C. or more for 1 hour or more to activate the impurities in the source / drain regions. Next, as shown in FIG. 6C, an interlayer insulating film is formed, and after contact holes are opened in the source / drain regions, electrode wiring is performed using Al or ITO.

[0008]

According to the present invention, the following effects can be obtained.

(1). The productivity can be improved by lowering the resistance of the thin film of 500 ° or less by annealing at 600 ° C or less for a short time.

(2). Inexpensive glass substrates can be used.

(3). The gate electrode can be formed of metal, and the resistance of the gate line can be reduced.

(4). Using an ion implanter that does not use mass spectrometry, implanting all ions generated from a gas mixture serving as an impurity and a balance gas consisting of helium gas, the thin film transistor of the gate electrode is thinned. Can be avoided from being implanted into the channel portion. Thus, the characteristics of the thin film transistor can be stabilized and the surface of the thin film transistor can be flattened.

(5). Since impurity activation can be performed at a low temperature, it is possible to avoid warpage or undulation of the substrate, which is a problem in a large-area substrate, thereby improving productivity.

[Brief description of the drawings]

FIG. 1 is a diagram showing the relationship between the sheet resistance of a source / drain region of a thin film transistor and an activation heat treatment temperature.

FIG. 2 is an enlarged cross-sectional view of a source / drain region immediately after impurity implantation when a conventional ion implantation method is used.

FIG. 3 is an enlarged cross-sectional view of a source / drain region immediately after impurity implantation in the case of using the method for manufacturing a thin film transistor of the present invention.

FIG. 4 is a cross-sectional view of one embodiment of a thin film transistor manufactured by using the method for manufacturing a thin film transistor of the present invention.

FIGS. 5A to 5C are process diagrams of one embodiment using the method of manufacturing a thin film transistor according to the present invention.

FIGS. 6A to 6C are process diagrams of another embodiment using the method for manufacturing a thin film transistor according to the present invention.

[Explanation of symbols]

101 Sheet resistance curve of source / drain region when conventional ion implantation is used 102 In the method of manufacturing a thin film transistor of the present invention, 5% of phosphine is contained using an ion implantation apparatus without mass spectrometry, and the rest is helium. Source when all ions generated from gas consisting of gas are implanted
Sheet resistance curve of drain region 401 Substrate 402 Insulating film 403 Non-doped polycrystalline silicon 404 Gate insulating film 405 Gate electrode 406 Source / drain region 407 Interlayer insulating film 408 Electrode wiring 501 Substrate 502 Silicon oxide film 503 Crystalline silicon 504 Gate insulating film 505 Gate electrode 506 Ion beam of all ions containing 5% of phosphine and the remainder formed from a gas composed of helium gas 507 Source / drain regions 508 Interlayer insulating film 509 Electrode wiring 601 Many impurities-free Crystal silicon 602 Gate insulating film 603 Gate electrode 604 Ion beam of all ions generated from a gas containing 5% of phosphine and the balance being helium gas 605 Source / drain regions

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/265 H01L 21/265 602 H01L 21/336

Claims (5)

(57) [Claims] In a method of manufacturing a thin film transistor formed on a substrate, a step of forming a gate electrode on a silicon film to be a source / drain region via an insulating film, and thereafter, performing ion implantation without using mass spectrometry Implanting all ions generated from a mixed gas composed of a gas serving as an impurity and a helium gas into the silicon film by using an apparatus, wherein the temperature of the substrate is 200 ° C. or more and 500 ° C. or more. A method of manufacturing a thin film transistor, wherein the impurity ions are implanted while maintaining the following. 2. The method according to claim 1, wherein said silicon film has a thickness of not less than 250 angstroms and not more than 500 angstroms. 3. The method for manufacturing a thin film transistor according to claim 1, wherein a gas mixture containing less than 10% of said impurity gas is used. 4. The method according to claim 1, wherein the temperature of the substrate is 300.degree.
4. The method for manufacturing a thin film transistor according to claim 1, wherein: 5. The method according to claim 1, wherein the step of implanting the impurity ions comprises the step of:
5. The method for manufacturing a thin film transistor according to claim 1, wherein the annealing is performed at a temperature of not less than 600C and not more than 600C.