JP3186056B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a thin film transistor in a self-aligned manner.

[Conventional technology]

In order to achieve a self-aligned structure of a polycrystalline silicon thin film transistor (hereinafter, TFT), ion implantation into a staggered structure is known. However, in this structure, the element in the gate insulating film is knocked on the polycrystalline silicon in the channel portion, and there is a problem in improving the characteristics by reducing the thickness of the channel portion.

[Problems to be solved by the invention]

An object of the present invention is to devise a self-aligned manufacturing method of an inversely staggered TFT which prevents knock-on to a channel portion for the purpose of improving TFT characteristics.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention is to solve the above problems, and a method for manufacturing a semiconductor device according to the present invention comprises the steps of: Forming and patterning a silicon layer, forming a gate insulating film on the first silicon layer, and forming a second silicon layer serving as a source / drain on the first silicon layer and the gate insulating film. Forming a layer, self-aligning a gate electrode by ion-implanting the first silicon layer using the second silicon layer as a mask, and forming the gate insulating film on the gate electrode. Forming a third silicon layer serving as a channel, which is disposed to face through the third silicon layer.

〔Example〕

The details of the present invention will be described with reference to examples. FIG. 1 is an embodiment showing steps of a method of manufacturing a semiconductor device according to the present invention.

First, an insulating film 102 is formed on a glass substrate 101 as shown in FIG. The purpose of the insulating film is to prevent heavy metals and the like contained in the glass substrate from diffusing into the element portion during heat treatment, and the purity of the glass substrate may not be sufficiently high. Next, non-doped polycrystalline silicon 103 is deposited and patterned so as to form a part of the gate electrode of the semiconductor element. Next, as shown in FIG.
A gate insulating film 104 is deposited for 1000 Å. Next, a polycrystalline silicon film 105 containing an impurity of phosphorus or boron is deposited for 3000 Å and patterned to form a drain / source region. Here, the source / drain regions may be formed by depositing polycrystalline silicon containing no impurity and implanting impurities by ion implantation. Next, as shown in FIG. 1C, phosphorus ions 106 are implanted into the polycrystalline silicon 103 at an energy of 150 KeV using the drain / source portions as a mask. Impurities are implanted into the first polycrystalline silicon in a self-aligned manner. The next implanted impurity is 600
Activate by annealing at ℃ for 20 hours. Thereby, gate electrode 107 is formed in polycrystalline silicon 103 in a self-aligned manner. Next, as shown in FIG. 1D, polycrystalline silicon 108 for forming a channel is formed, and an interlayer insulating film 109 is formed.
Is deposited, contacts are opened in the source / drain regions, and electrode wiring is performed with Al.

By using the pre-fabrication method as described above,
Since the gate electrode can be formed in a self-aligned manner using the source / drain region as a mask, the parasitic capacitance of the TFT can be reduced and the characteristics of the TFT can be improved.

[Effects of the Invention] According to the present invention, an inverted staggered thin film transistor having a self-aligned gate structure can be manufactured.

[Brief description of the drawings]

1 (a) to 1 (d) are process diagrams of one embodiment showing a method for manufacturing a semiconductor device according to the present invention. 101 glass substrate 102 insulating film 103 first polycrystalline silicon containing no impurity 104 gate insulating film 105 polycrystalline silicon containing impurity 106 ion beam 107 self-aligned Gate electrode 108 ... Second polycrystalline silicon containing no impurities 109 ... Interlayer insulating film 110 ... Al electrode

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-308385 (JP, A) JP-A-1-243572 (JP, A)

Claims (1)

(57) [Claims] A step of forming and patterning a first silicon layer on an insulating substrate or an insulating film; a step of forming a gate insulating film on the first silicon layer; Forming a second silicon layer serving as a source / drain on the gate insulating film; and ion-implanting the first silicon layer using the second silicon layer as a mask to form a self-aligned gate electrode. Forming a third silicon layer serving as a channel, which is disposed to face the gate electrode with the gate insulating film interposed therebetween.