JPH0832075A - Thin film transistor cmos circuit - Google Patents

Abstract

PURPOSE:To suppress variation in the transistor characteristics due to the dispersion of water content in channel regions within a CMOS circuit using a top gate thin film transistors. CONSTITUTION:Phosphorus ions 5 are implanted in polycrystalline silicon film 3 for a channel part source/drain electrodes while boron ions 6 are implanted in polycrystalline film 3 for p channel source/drain electrodes. Next, source/drain region 8 for n channel and source/drain region 9 for p channel are formed by photolithgraphy so as to form a polycrystalline silicon film 12 to be an active layer is formed thereon by an excimer laser annealing method. Next, said film 12 is insularly patterned and after forming a gate insulating silicon oxide film 13 by a low pressure CVD method, a gate electrode 16, a source electrode 17 and a drain electrode 18 are formed. At this time, in relation to the overlaps of a gate electrode with the polycrystalline silicon films for source, drain, the overlap 20 of n channel transistor is made smaller than the overlap 19 of p channel transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film transistor for a CMOS drive circuit for the purpose of application to a liquid crystal display integrated with a CMOS drive circuit, an image sensor, etc., and particularly to a gate, a source and a drain. It is intended to improve the reliability of the transistor while minimizing the deterioration of the driving capability of the circuit due to the parasitic capacitance between them.

[0002]

2. Description of the Related Art With the development of an excimer laser annealing method, a technique for forming a polycrystalline silicon thin film transistor on a borosilicate glass substrate which has a low cost but a low strain temperature has been established. If the temperature at the time of producing polycrystalline silicon by excimer laser irradiation has almost no effect on the glass substrate, the maximum process temperature in the future will be about 450 to 500 ° C., and it is expected that a cheaper glass substrate can be used. . Development of a low-cost high-definition liquid crystal display using a CMOS drive circuit using a polycrystalline silicon thin film transistor and a liquid crystal pixel switching transistor on this inexpensive glass substrate is expected.

FIG. 5 is a structural sectional view of a CMOS circuit using a forward staggered thin film transistor according to a conventional method. In the figure, 41 is a glass substrate, 42 is a metal silicide film, and 43.
Is a source / drain polycrystalline silicon film, 44 is an active layer polycrystalline silicon film, 45 is a silicon oxide film for a gate insulating film, 46 is a phosphorus-doped polycrystalline silicon film, 48 is a gate electrode, 49 is a source electrode, and 50 is a drain. It is an electrode.

In the case of the stagger structure, the gate electrode 48 and the source / drain polycrystalline silicon film 43 are overlapped in consideration of misalignment in the photolithography process. 51 is the gate electrode 4 of the p-channel transistor
8 and the source / drain polycrystalline silicon film 43 are overlapped, and 52 is the n-channel transistor gate electrode 48 and the source / drain polycrystalline silicon film 43 are overlapped. The lengths of the overlaps 51 and 52 are normally the same for both n-channel transistors and p-channel transistors.

FIG. 6 is a structural sectional view of a CMOS circuit using a planar structure thin film transistor according to a conventional method.
In the figure, 61 is a glass substrate, 62 is a p-channel source,
Drain region, 63 is an n-channel source and drain region, 64 is an active layer polycrystalline silicon film, 65 is a gate insulating film silicon oxide film, 66 is a phosphorus-doped polycrystalline silicon film, 68 is a gate electrode, and 69 is a source electrode. , 70 are drain electrodes.

In the case of the planar structure, since the impurity implantation for forming the source and drain regions is normally performed in a self-aligned manner using the gate electrode, there is no overlap between the gate electrode and the source and drain regions as in the forward stagger structure. .

[0007]

When the process temperature is lowered as in the prior art described above, there arises a problem of transistor characteristic variation due to deterioration of the film quality of the gate insulating film. The lower the formation temperature of the gate insulating film, the further away from the stoichiometric composition, and the film becomes sparse. In addition, the content of OH groups, dangling bonds, etc. also increases. If the film is sparse, water easily enters and diffuses from the atmosphere. The Si—OH hydrogen-bonded to the invading water, the Si—OH generated by the reaction of the water and the dangling bond, or the invading water itself is ionized under the electric field stress to generate an electric charge, which largely changes the transistor characteristics. To solve this problem, if the overlap between the gate electrode and the source / drain polycrystalline silicon film in the staggered structure of FIG. 5 is increased, the distance between the gate electrode edge, which is the water intrusion point, and the channel region becomes long, and the channel region Since the amount of diffused water is reduced, there is an effect that the characteristic variation is less likely to occur or the characteristic variation is reduced.

However, in the above configuration,
When the overlap between the gate electrode and the source / drain polycrystalline silicon film is increased, the gate-drain (source)
There is a problem that the inter-capacitance becomes large and causes a signal delay in the drive circuit.

Further, in the planar structure shown in FIG. 4, since there is almost no overlap between the gate electrode and the source / drain regions, there is no effect of reducing the amount of diffused water as described above.

The present invention has been devised in view of the above problems. In an n-channel transistor, phosphorus injected into the source and drain has a gettering action against water, so that characteristic variation due to water intrusion does not easily occur. , Or the characteristic variation is reduced, in a CMOS circuit using a top gate type thin film transistor, the gate-source and drain overlap lengths for suppressing the amount of water diffused from the edge of the gate electrode to the channel region are set to p It is an object of the present invention to make an n-channel transistor smaller than a channel transistor and to suppress fluctuations in transistor characteristics due to water diffusion into a channel region without excessively increasing gate-source / drain capacitance.

[0011]

According to the present invention, a source / drain polycrystalline silicon layer, a polycrystalline silicon layer formed on the source / drain to serve as an active layer, and the active layer multi-layer are provided on an insulating substrate. In a CMOS circuit using an insulating film formed on a crystalline silicon layer to serve as a gate insulating film and a thin film transistor having a gate electrode on the insulating film,
The overlap between the source / drain polycrystalline silicon layer and the gate electrode is smaller in the n-channel transistor than in the p-channel transistor.

Further, according to the present invention, a polycrystalline silicon layer to be an active layer, source and drain regions formed by impurity implantation in the polycrystalline silicon layer, and an polycrystalline silicon layer formed on the polycrystalline silicon layer on an insulating substrate. In a CMOS circuit using an insulating film serving as a gate insulating film and a thin film transistor having a gate electrode on the insulating film, the overlap between the source and drain regions and the gate electrode is larger in an n-channel transistor than in a p-channel transistor. Is small.

[0013]

[Operation] CM using top gate type thin film transistor
In the OS circuit, the overlap length of the gate and the drain and the gate and the source for suppressing the amount of water diffused from the edge of the gate electrode to the channel region, the n-channel transistor is made smaller than the p-channel transistor, and the gate-drain ( Variation in transistor characteristics due to water diffusion into the channel region can be suppressed without excessively increasing the capacitance between the sources).

[0014]

EXAMPLE An example of the present invention will be described based on element cross-sectional views in the manufacturing process of a polycrystalline silicon thin film transistor.

(Embodiment 1) FIG. 1 is a sectional view of an element showing a concrete first embodiment of the present invention, showing a CMOS circuit using a forward stagger type polycrystalline silicon thin film transistor.

In the figure, 1 is a glass substrate, 2 is a metal silicide film, 3 is a polycrystalline silicon film for source and drain, and 12
Is an active layer polycrystalline silicon film, 13 is a silicon oxide film for a gate insulating film, 14 is a phosphorus-doped polycrystalline silicon film, 16 is a gate electrode, 17 is a source electrode, and 18 is a drain electrode.

In this CMOS circuit, the gate electrode 16 of the p-channel transistor and the source / drain polycrystalline silicon film 3 overlap 19 with each other, and the n-channel transistor gate electrode 16 and the source / drain polycrystalline silicon film 3 overlap 20 with each other. Greater than

A process for manufacturing this CMOS circuit is shown in FIG.
It will be described based on.

First, as shown in FIG. 2A, after depositing a metal silicide film 2 on a substrate 1 such as a glass substrate, at least the surface of which is an insulating material, and the lower portions of the source and drain electrodes are formed by photolithography. A source / drain electrode polycrystalline silicon film 3 is deposited.

Next, as shown in FIG. 2B, a silicon oxide film 4 for an ion implantation cover is deposited, and a resist mask 7 is formed thereon. Using this resist mask 7, phosphorus ions 5 are implanted through the ion implantation cover silicon oxide film 4 into the n-channel partial source / drain electrode polycrystalline silicon film 3.

Subsequently, as shown in FIG. 2C, boron ions 6 are implanted into the p-channel partial source / drain electrode polycrystalline silicon film 3.

Next, as shown in FIG. 2D, the n-channel source / drain region 8 is formed by photolithography.
A p-channel source / drain region 9 is formed, the ion implantation silicon oxide film 4 is removed, and then an amorphous silicon film 10 is formed. Here, a polycrystalline silicon film may be used instead of the amorphous silicon film 10. The amorphous silicon film 10 is irradiated with XeCl excimer laser light 11 to form a polycrystalline silicon film 12 to be an active layer by melt recrystallization as shown in FIG. The active layer polycrystalline silicon film 12 may be formed by a solid phase growth method or a CVD method. In the next step, the polycrystalline silicon film 12 is patterned into an island shape by photolithography, and subsequently a silicon oxide film 13 for a gate insulating film is formed.

Finally, as shown in FIG. 2F, the gate electrode 16, the source electrode 17, and the drain electrode 18 are formed by using the phosphorus-doped polycrystalline silicon film 14 and the aluminum film. At this time, the overlap between the gate electrode and the source / drain polycrystalline silicon film is formed so that the overlap 20 of the n-channel transistors is smaller than the overlap 19 of the p-channel transistors. Note that the overlap 20 of the n-channel transistors also includes zero or less. Considering both suppression of excessive increase of parasitic capacitance caused by overlapping of gate, source and drain and suppression of characteristic fluctuation due to moisture intrusion, the overlap 20 of n-channel transistors is about 1 μm.
The overlap 19 of m and p channel transistors is 1-2 μm
Is the best.

As described above, the highly reliable CMOS circuit using the forward stagger type polycrystalline silicon thin film transistor can be formed without excessively increasing the parasitic capacitance.

(Embodiment 2) FIG. 3 is a sectional view of an element showing another embodiment, showing a CMOS circuit using a planar type polycrystalline silicon thin film transistor.

In the figure, 21 is a glass substrate, 26 is an n-channel source / drain region, 28 is a p-channel source / drain region, 30 is an active layer polycrystalline silicon film, 3
1 is a silicon oxide film for a gate insulating film, 32 is a phosphorus-doped polycrystalline silicon film, 34 is a gate electrode, 35 is a source electrode, and 36 is a drain electrode.

In this CMOS circuit, the overlap 37 of the gate electrode 34 of the p-channel transistor and the source / drain region 28 is the gate electrode 3 of the n-channel transistor.
4 is larger than the overlap 38 of the source / drain regions 26.

The manufacturing process of this CMOS circuit is shown in FIG.
It will be described based on.

First, as shown in FIG. 4A, an amorphous silicon film 22 and a silicon oxide film 23 for an ion implantation cover are formed on a substrate 21 such as a glass substrate, at least the surface of which is an insulating material. Here, a polycrystalline silicon film may be used instead of the amorphous silicon film 22.

Next, as shown in FIG. 4B, using the resist mask 24, phosphorus ions 25 are implanted into the n-channel partial silicon film to form the n-channel partial source / drain regions 2.
6 is formed.

Subsequently, as shown in FIG. 4C, boron ions 27 are implanted into the p-channel partial silicon film to form p-channel partial source / drain electrodes 28.

Next, as shown in FIG. 4D, the silicon film is irradiated with XeCl excimer laser light 29 to form a polycrystalline silicon film 30 serving as an active layer by melt recrystallization. The active layer polycrystalline silicon film 30 may be formed by forming polycrystalline silicon by a solid phase growth method or a CVD method without performing excimer laser recrystallization. In the step of the excimer laser annealing shown in FIG. 4D, the temperature of silicon is 1420 K or higher, which is the melting point, but the pulse width of the laser is very short, such as several tens of nanoseconds. Impurities do not diffuse significantly into the channel region. If the diffusion distance is known and reproducible, the pattern design may be performed in consideration of the diffusion distance.

As the next step, as shown in FIG.
The polycrystalline silicon film 30 is patterned into an island shape by photolithography, and the silicon oxide film 3 for a gate insulating film is formed.
1 is formed.

Finally, as shown in FIG. 4F, the gate electrode 34, the source electrode 35, and the drain electrode 36 are formed by using the phosphorus-doped polycrystalline silicon film 32 and the aluminum film. At this time, the overlap between the gate electrode and the source / drain regions is formed so that the overlap 38 of the n-channel transistors is smaller than the overlap 37 of the p-channel transistors. The overlap of n-channel transistors 3
It also includes that 8 is zero or less. Considering both suppression of excessive increase in parasitic capacitance between the gate, source, and drain and suppression of characteristic fluctuation due to moisture intrusion, the overlap 38 of the n-channel transistors is about 1 μm and the overlap 37 of the p-channel transistors is similar to the first embodiment. 1-2 μm is optimal.

As described above, a highly reliable CMOS circuit using the planar type polycrystalline silicon thin film transistor can be formed without excessively increasing the parasitic capacitance.

[0036]

As described above, according to the present invention,
In a CMOS circuit using a top gate type polycrystalline silicon thin film transistor, it is possible to realize a characteristic variation due to moisture intrusion due to the overlapping of the gate and the source and the gate and the drain without excessively increasing the parasitic capacitance.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing an embodiment of a thin film transistor CMOS circuit according to the present invention.

FIG. 2 is a schematic cross-sectional view showing a manufacturing process of the thin film transistor CMOS circuit of FIG.

FIG. 3 is a schematic cross-sectional view showing another embodiment of the thin film transistor CMOS circuit according to the present invention.

FIG. 4 is a schematic cross-sectional view showing a manufacturing process of the thin film transistor CMOS circuit of FIG.

FIG. 5 is a structural cross-sectional view of a forward staggered thin film transistor having a gate, a source, and a drain having the same overlap according to the related art.

FIG. 6 is a structural cross-sectional view of a planar structure thin film transistor in which a gate, a source, and a drain do not have an overlap according to a conventional technique.

[Explanation of symbols]

1, 21, 41, 61 Glass substrate 2, 42 Metal silicide film 3, 43 Polycrystalline silicon film for source and drain 4, 23 Silicon oxide film for ion implantation cover 5, 25 Phosphorus ion 6, 27 B ion 7, 24 Resist 8,26,63 n-channel source / drain region 9,28,62 p-channel source / drain region 10,22 amorphous silicon film 11,29 XeCl excimer laser light 12,30,44,64 active layer polycrystal Silicon film 13, 31, 45, 65 Silicon oxide film for gate insulating film 14, 32, 46, 66 Phosphorus-doped polycrystalline silicon film 16, 34, 48, 68 Gate electrode 17, 35, 49, 69 Source electrode 18, 36 , 50, 70 Drain electrode 19, 37, 51 Weight of gate, source and drain of p-channel transistor Ri gate and source of 20,38,52 n-channel transistor, the drain overlap

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 27/08 331 E H01L 27/08 321 C

Claims (4)

[Claims] 1. A source / drain polycrystalline silicon layer on an insulating substrate, a polycrystalline silicon layer formed on the source / drain to serve as an active layer, and a gate formed on the active layer polycrystalline silicon layer. In a CMOS circuit using an insulating film to be an insulating film and a thin film transistor having a gate electrode on the insulating film, an overlap between the source / drain polycrystalline silicon layer and the gate electrode is an n-channel transistor rather than a p-channel transistor. Is a thin film transistor CMOS circuit. 2. The overlap of the n-channel transistors is
1 μm, the overlap of the p-channel transistors is 1-2
The thin film transistor CMOS circuit according to claim 1, wherein the thin film transistor CMOS circuit has a thickness of μm. 3. A polycrystalline silicon layer serving as an active layer on an insulating substrate, source and drain regions formed by implanting impurities into the polycrystalline silicon layer, and a gate insulating layer formed on the polycrystalline silicon layer. In a CMOS circuit using an insulating film to be a film and a thin film transistor having a gate electrode on the insulating film, an overlap between the source / drain region and the gate electrode is smaller in an n-channel transistor than in a p-channel transistor. Thin film transistor C characterized by
MOS circuit. 4. The overlap of the n-channel transistors is
1 μm, the overlap of the p-channel transistors is 1-2
The thin film transistor CMOS circuit according to claim 3, wherein the thickness is μm.