JP3515132B2 - Method for manufacturing thin film transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor. 2. Description of the Related Art One of the methods for improving the characteristics of a thin film transistor is to form a self-aligned source / drain region using an ion implantation method for reducing a parasitic capacitance. On the other hand, it has been found that it is advantageous to reduce the thickness of the polycrystalline silicon film in order to improve the characteristics of the thin film transistor. However, when the thickness of the polycrystalline silicon film is reduced to 300 ° or less, if a normal ion implantation method is used, the formation of the source / drain region is performed at 600 ° C. or more for several tens of hours under a condition other than specific conditions. Anneal or laser anneal was required. Such a thermal anneal makes it impossible to use an inexpensive glass substrate, resulting in poor productivity. [0003] In a thin film transistor manufactured by using an ion implantation technique, a source having a sufficiently low resistance even by thermal annealing at 600 ° C or less for several hours.
An ion implantation method capable of forming a source / drain region is devised, and an inexpensive glass substrate can be used. According to a method of manufacturing a thin film transistor of the present invention, a method of manufacturing a thin film transistor using a polycrystalline semiconductor thin film on an insulating substrate is provided. A step of forming a polycrystalline semiconductor thin film having a crystallization ratio of 75% or more by crystallizing the amorphous semiconductor thin film by an annealing method, and using an ion implantation apparatus that does not perform mass spectrometry. 10
% Of all the ions generated from the mixed gas composed of a gas which is less than impurities and hydrogen as the remainder.
The crystallization rate of 7 maintained at not less than 00 ° C and not more than 500 ° C.
Forming a source and drain region in which a crystalline region remains by implanting into a polycrystalline semiconductor thin film having 5% or more; and activating and recrystallizing the source and drain region by an annealing method. It is characterized by. FIG. 1A is a view showing a portion of a semiconductor device immediately after implanting impurities.
FIG. 4 is a diagram showing a relationship between a crystallization ratio of a source / drain region having a film thickness of Å and a substrate temperature at the time of implantation. If the substrate temperature is lower than 300 ° C., the implanted source / drain region is amorphous. FIG. 1B is a diagram showing the relationship between the sheet resistance of the source / drain region having a thickness of 250 ° and the activation heat treatment temperature. A line 101 is a sheet resistance curve when a conventional semiconductor device manufacturing method is used. Line 102 indicates the case where the ion implantation apparatus is used in the method of manufacturing a semiconductor device according to the present invention, and the substrate temperature is 3
A sheet resistance curve in the case where the implantation is carried out while maintaining the temperature at not less than 00 ° C., a line 103 is generated from a gas containing 5% of phosphine and the balance being hydrogen gas by using an ion implantation apparatus without mass spectrometry. When all ions are implanted while maintaining the substrate temperature at 300 ° C. or higher.
3 shows a resistance curve. The activation heat treatment time is several hours.
FIG. 2 is a cross-sectional view of one embodiment of a thin film transistor manufactured by using the method of manufacturing a semiconductor device according to the present invention. A gate made by patterning a substrate 201 such as a glass substrate or a quartz substrate, a silicon oxide film 202, a non-doped polycrystalline silicon 203, a silicon oxide film 204, and a polycrystalline silicon film doped with impurities. The figure shows an electrode 205, a source / drain region 206 formed by impurity implantation, a silicon oxide film 207, and an electrode wiring 208. Hereinafter, a method for manufacturing a semiconductor device of the present invention will be described with reference to the process chart of FIG. First, as shown in FIG. 3A, a silicon oxide film 302 is deposited on a substrate 301 such as a glass substrate or a quartz substrate to a thickness of 2000 ° as an insulating film. The purpose of the insulating film is to prevent heavy metals and the like contained in the substrate from diffusing into the element portion during heat treatment, and the purity of the substrate does not need to be sufficiently high. Next, polycrystalline silicon 303 containing no impurity is deposited to a thickness of 250 ° and patterned. The crystallization rate of the polycrystalline silicon is 75%
Above, preferably 90% or more film is used. Next, a silicon oxide film is deposited to a thickness of 1500 ° to form a gate insulating film 30.
4 is formed. Next, polycrystalline silicon containing phosphorus is
The gate electrode 305 is deposited with a thickness of 0 ° and patterned.
To form Next, as shown in FIG. 3B, a phosphorus ion beam 306 is applied for 110 ke using the gate electrode as a mask.
The source / drain region 307 is formed by implanting V at an arbitrary concentration in the range of 1 × 10 ¹⁵ / cm ² to 1 × 10 ¹⁶ / cm ² . In the above-described implantation, the substrate is heated from the back surface side so that the substrate temperature can be maintained at 300 ° C. or higher, preferably 400 ° C. or higher and 500 ° C. or lower. Driving energy
Can be adjusted according to the type of impurity ions and the thickness of the gate insulating film, and it is apparent that the present invention is not limited to this embodiment. For example, in the case of boron ions, it may be set to 40 keV. Next, impurities are activated by heat treatment at 600 ° C. for one hour. In the step of implanting impurities, all the ions generated from a gas containing 5% of phosphine and the remainder being hydrogen gas are implanted using an ion implantation apparatus not using mass spectrometry to form a source / drain region. In order to fill the irregular bond, the source / drain region can be formed at a lower temperature. Next, FIG.
As shown in FIG. 3C, a silicon oxide film is deposited to a thickness of 5000.degree., An interlayer insulating film 308 is formed, and a contact hole is opened in the source / drain region.
The electrode wiring 309 is formed by TO. FIG. 4 is a cross-sectional view of a semiconductor device immediately after impurity implantation in the case of using the conventional semiconductor device manufacturing method.
FIG. 4 is an enlarged sectional view of a source / drain region having a thickness of 50 °. The implantation makes the polycrystalline silicon film amorphous. FIG. 5 is an enlarged cross-sectional view of a source / drain region having a thickness of 250 ° immediately after impurity implantation in the case of using the semiconductor device manufacturing method of the present invention.
Crystals remain in the film even after implantation. Since the remaining crystal is used as a seed, recrystallization and low resistance can be performed at a low temperature and in a short time. According to the present invention, the following effects can be obtained. (1). Since the resistance of the thin film of 250 ° or less can be reduced at 600 ° C. or less and with a short annealing time, the productivity is improved. (2). Inexpensive glass substrates can be used. In addition, using an ion implantation apparatus that does not use mass spectrometry, a gas that is an impurity of 0% or more and less than 10% and all ions generated from a gas whose balance is hydrogen gas are implanted. Since hydrogen ions effectively fill the irregular bonds, activation at lower temperatures is possible, and at the same time, the channel portion of the thin film transistor can be hydrogenated, and the characteristics of the thin film transistor are improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 (a) is a diagram showing the relationship between the crystallization ratio of a source / drain region of a thin film transistor immediately after impurity implantation and the substrate heating temperature at the time of implantation. (B) shows the source
FIG. 4 is a diagram showing a relationship between a sheet resistance of a drain region and an activation heat treatment temperature. FIG. 2 is a sectional view of one embodiment of a method for manufacturing a semiconductor device according to the present invention. FIG. 3 is a process chart of one embodiment of a method of manufacturing a semiconductor device according to the present invention. FIG. 4 is an enlarged cross-sectional view of a source / drain region immediately after impurity implantation when a conventional method for manufacturing a semiconductor device is used. FIG. 5 is an enlarged cross-sectional view of a source / drain region immediately after impurity implantation when the method of manufacturing a semiconductor device according to the present invention is used. DESCRIPTION OF THE SYMBOLS 101 Sheet resistance curve of source / drain region in the case of using the conventional method of manufacturing a semiconductor device 102 In the method of manufacturing the semiconductor device of the present invention, the source −Sheet of drain / drain region
Resistance curve 103 In the method of manufacturing a semiconductor device of the present invention, when the ion implantation apparatus without mass spectrometry is used,
Drain region sheet resistance curve 201 Substrate 202 Silicon oxide film 203 Non-doped polycrystalline silicon 204 Silicon oxide film 205 Gate electrode 206 Source / drain region 207 Silicon oxide film 208 Electrode wiring 301 Substrate 302 Silicon oxide Film 303 impurity-free polycrystalline silicon 304 gate insulating film 305 gate electrode 306 phosphorus ion beam 307 source / drain region 308 interlayer insulating film 309 electrode wiring

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-63-194326 (JP, A)                 JP-A-3-139825 (JP, A)                 JP-A-2-226732 (JP, A)                 JP-A-3-36767 (JP, A)                 JP-A-3-36768 (JP, A)                 JP-A-1-187814 (JP, A)

Claims (1)

(1) In a method of manufacturing a thin film transistor formed using a polycrystalline semiconductor thin film on an insulating substrate, an amorphous semiconductor thin film is formed on the insulating substrate. Crystal growth of an amorphous semiconductor thin film by an annealing method, the crystallization rate is 7
Forming a polycrystalline semiconductor thin film having 5% or more;
Using an ion implanter without mass spectrometry, 10%
All ions generated from a mixed gas composed of a gas serving as a full impurity and a balance of hydrogen are converted to a substrate temperature of 400.
The crystallization rate of 75%, which is maintained at not less than 500 ° C.
Forming a source and drain region in which a crystalline region remains by implanting into the polycrystalline semiconductor thin film having the above, and activating and recrystallizing the source and drain region by an annealing method. Of manufacturing a thin film transistor.