JP4281103B2 - Device simulation method for polycrystalline semiconductor device, method for designing polycrystalline semiconductor device, and method for manufacturing polycrystalline semiconductor device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor device, and more particularly to a polycrystalline thin film transistor using a polycrystalline semiconductor for an active layer.
[0002]
[Prior art]
Polycrystalline thin-film transistors are semiconductor elements that use a polycrystalline semiconductor as the active layer, and are widely used as devices for realizing lightweight and thin display devices such as liquid crystal displays and electroluminescent displays, and scanners. It has been.
[0003]
In general, prior to the manufacture of semiconductor elements, device simulation is performed to predict device characteristics and analyze device operation using parameters such as the device structure and the physical properties of the materials used. Device structure and manufacturing conditions are determined.
[0004]
Therefore, although it is expected that device characteristics can be predicted with high accuracy for polycrystalline thin film transistors, it can be a useful tool for device structure optimization. An effective device simulation method has not been proposed, and as a result, it has been difficult to determine the structure and manufacturing conditions of a polycrystalline thin film transistor having desired device characteristics.
[0005]
[Problems to be solved by the invention]
The inventors of the present invention have studied in detail the problems in applying the conventional device simulation method to a polycrystalline thin film transistor. As a result, the device structure of the polycrystalline thin film transistor is determined by the active layer of the polycrystalline semiconductor. It was found that it is extremely important to determine the device structure etc. after accurately handling the carrier transport phenomenon in the crystal in consideration of the carrier scattering phenomenon in the crystal grain boundary existing at high density in the inside. .
[0006]
Accordingly, the object of the present invention is to calculate the carrier flow density flowing in the active layer based on device simulation that accurately handles the scattering effect of carriers at the grain boundaries in the active layer, and to determine device parameters based on this value. A polycrystalline thin film transistor designed as described above is provided.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the device simulation method for a polycrystalline semiconductor device of the present invention takes into account the carrier scattering effect at the crystal grain boundary in the device simulation method for a polycrystalline semiconductor device using a polycrystalline semiconductor for the active layer. It is characterized by that.
[0008]
By adopting such a configuration, a simulation for obtaining a semiconductor element having an optimized device structure in a laser-crystallized polycrystalline silicon thin film transistor in which the carrier transport mechanism of the crystal grain boundary is particularly dominant with respect to the transistor characteristics can be performed. It becomes possible.
[0009]
Preferably, the thermoionic emission effect at the crystal grain boundary is taken into consideration.
[0010]
Preferably, the carrier current density J _t passing through the grain boundaries, characterized by being represented by the following formula.
[0011]
J _t = (1-c / 2) v (n ₁ -n ₂ ) / 4
(1-c / 2) v / 4 = A * T 2 / (qN e)
J _t : Carrier flow density c: Rate at which the carrier flow is trapped at the grain boundary v: Electron average heat speed n ₁ : Carrier density on one side of the crystal grain boundary n ₂ : Carrier density on the other side of the crystal grain boundary A ^* : Effective Richardson constant T: Absolute temperature q: Elementary charge N _e : Effective state density Preferably, the polycrystalline semiconductor element is a polycrystalline silicon thin film transistor in which polycrystalline silicon is used as an active layer. And
[0012]
Preferably, the polycrystalline semiconductor element is a laser-crystallized polycrystalline silicon thin film transistor in which polycrystalline silicon is used for an active layer and polycrystalline silicon is crystallized by a laser crystallization process.
[0013]
In the semiconductor device of the present invention, the carrier flow density (J _t ) is calculated by the following equation in consideration of the free carrier scattering effect at the crystal grain boundary in the semiconductor device using a polycrystalline semiconductor as the active layer. The parameters governing the device characteristics are determined based on the design.
[0014]
J _t = (1-c / 2) · v · (n ₁ −n ₂ ) / 4
c: Rate at which carrier flow is trapped at the grain boundary v: Electron average heat speed n ₁ : Carrier density on one side of the grain boundary n ₂ : Carrier density on the other side of the grain boundary Preferably, the semiconductor element is active A polycrystalline silicon thin film transistor using polycrystalline silicon as a layer, and more preferably a polycrystalline silicon thin film transistor manufactured by performing polycrystallization of an active layer by a laser crystallization process, In a laser crystallized polycrystalline silicon thin film transistor in which the carrier transport mechanism of the crystal grain boundary is particularly dominant with respect to the transistor characteristics, a semiconductor element having an optimized device structure can be obtained.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the semiconductor device of the present invention will be described in detail with reference to the drawings.
(Carrier flow density at grain boundaries)
FIG. 4 is a diagram showing the structure of a polycrystalline silicon thin film transistor constructed using polycrystalline silicon for the active layer.
[0016]
In the polycrystalline silicon thin film transistor shown in FIG. 4, first, a polycrystalline silicon film is formed on a substrate 16 by a CVD method, and a gate insulating film 17 is formed on the polycrystalline silicon film by a silicon oxide film grown by a thermal oxidation method. Is formed. A gate electrode 18 is formed on the gate oxide film, and the polycrystalline silicon film under the gate electrode 18 is operated as a gate region. Further, the polycrystalline silicon film regions sandwiching the gate region from the left and right act as a source region 14 and a drain region 15 to operate as a polycrystalline thin film transistor. In FIG. 4, a straight line penetrating the polycrystalline silicon film obliquely from the substrate 16 toward the gate insulating film 17 is a grain boundary 13 formed by silicon crystals having different crystal orientations constituting the polycrystalline silicon film. It is.
[0017]
The characteristics of the polycrystalline thin film transistor compared to the single crystal thin film transistor are that the semiconductor film that forms the active layer of the transistor is composed of polycrystals, and therefore there are crystal grains with different crystal orientations in the active layer. As a result, there is a crystal grain boundary 13 between the crystal grains.
[0018]
In general, it is known that a crystal grain boundary acts as a carrier trapping center, and carrier traps exist at a high density in the vicinity of the crystal grain boundary. Once carriers are trapped in the trap, charges are locally accumulated by the amount of charges of the trapped carriers and a so-called “potential barrier” is formed (for example, M. Kimura et al .: J Appl.Phys.89 (2001) 596). When a potential barrier is formed at the crystal grain boundary by trapping carriers, free carriers having thermal excitation energy lower than that of the potential barrier cannot pass through the crystal grain boundary.
[0019]
On the other hand, not all free carriers having thermal excitation energy higher than this potential barrier can freely pass through the grain boundary, and it is known that such free carriers are also scattered by so-called “Thermic Emission”. (For example, S. M. Sze: Physics of Semiconductor Devices, 2nd Edition (John Wiley & Sons, New York, 1981)).
[0020]
In this way, the transport phenomenon of free carriers in the vicinity of grain boundaries in a polycrystalline semiconductor that essentially contains grain boundaries at a high density should be analyzed simply based on the statistical distribution of thermal energy of free carriers. However, it is not sufficient, and it is necessary to sufficiently consider the carrier trap and potential barrier existing in the crystal grain boundary, and the carrier scattering phenomenon due to thermionic emission.
[0021]
Therefore, in the design of the semiconductor device of the present invention, the carrier transport phenomenon is handled in consideration of the carrier scattering effect at the crystal grain boundary, which has been ignored in the conventional device design stage. More specifically, handling is performed in consideration of the Thermic Emission effect at the grain boundaries.
[0022]
When this handling is expressed by a mathematical expression, the carrier flow density (J _t ) passing through the grain boundary is
J _t = (1-c / 2) · v · (n ₁ −n ₂ ) / 4
Given by. Here, c is the rate at which the carrier flow is trapped at the crystal grain boundary, v is the average heat velocity of electrons, and n ₁ and n ₂ are the carrier densities on one side and the other side of the crystal grain boundary.
[0023]
Further, the above relational expression, using the effective Richardson constant ^{A *,} and the effective density of states _{N e,}
(1-c / 2) · v / 4 = A ^* · T ² / (q · N _e )
Based on the relation of
^{_{J t = (n 1 -n 2}} ) · A * · T 2 / (q · N e)
It may be expressed as Here, T is an absolute temperature and q is an elementary charge.
[0024]
These formulas are basically based on the band structure theory of the semiconductor material, but the final result is that the carrier flow density (J _t ) is the difference between the carrier densities on both sides of the grain boundary (n ₁ −n _It is very simple to be proportional to ₂ ).
[0025]
Here, the effective Richardson constant A ^* is a constant depending on the quality of the crystal grain boundary, and is large when the crystal orientation is aligned or when adjacent crystal grains are normally connected. In this case, the carrier flow density J _t takes a large value. On the other hand, when the crystal orientation is not aligned or when an oxide film is present at the crystal grain boundary, the effective Richardson constant A ^* is small, and the carrier flow density _Jt is small. It is known that the effective Richardson constant A ^* of high-quality polycrystalline silicon produced carefully is 110 A / cm ² / K ² .
[0026]
FIG. 1 and FIG. 2 show the potential distribution in the vicinity of the grain boundary (FIG. 1) and the free carriers in the vicinity of the grain boundary when the Thermic Emission effect based on the above theoretical consideration is taken into consideration and when the effect is not taken into account. It is the result of having compared density distribution (FIG. 2). In either case, it is assumed that a crystal grain boundary exists at the position of 0 nm, and the relative distance from the crystal grain boundary is plotted on the horizontal axis.
[0027]
According to FIG. 1, when the simulation is performed in consideration of the Thermic Emission effect, the potential value tends to decrease as the relative position from the grain boundary moves from the minus side to the plus side. A sudden potential drop occurs near the grain boundary position.
[0028]
On the other hand, when the Thermic Emission effect is not taken into consideration, the relative value from the grain boundary tends to decrease in potential value from the minus side to the plus side, but the maximum value of the potential value at the grain boundary position. Appears. This means that a potential barrier exists at the grain boundary position.
[0029]
That is, when the Thermic Emission effect is taken into account in the carrier transport phenomenon, the resistance at the crystal grain boundary caused by the Thermic Emission effect becomes dominant with respect to the carrier transport. However, if the Thermic Emission effect is not taken into account, the resistance at the crystal grain boundary due to the potential barrier formed at the crystal grain boundary becomes dominant for carrier transport. Appears as a difference.
[0030]
This qualitative difference has an extremely important meaning in the design of a polycrystalline semiconductor device that essentially includes a high density of grain boundaries.
[0031]
Also, reflecting the difference in the potential distribution, there is a great difference in the simulation result of the free carrier density distribution when the thermal emission effect is taken into consideration and when it is not taken into consideration. The result is shown in FIG.
[0032]
Considering the Thermic Emission effect, in order to generate a carrier flow density that passes through the grain boundary, the free carrier density distribution becomes asymmetric on both sides of the grain boundary, and a sudden drop in free carrier density is observed at the grain boundary. Is done. On the other hand, when the Thermic Emission effect is not taken into consideration, the free carrier density shows a symmetric distribution across the crystal grain boundary and also shows a gradual drop in the crystal grain boundary. In addition to the qualitative difference, a large difference is also observed in the value of the carrier flow density in the vicinity of the grain boundary.
[0033]
Thus, there is a big difference in the simulation results of the potential distribution and the free carrier density distribution between the case where the thermal emission effect is taken into consideration and the case where the thermoelectric emission effect is not taken into account. It is possible to correctly express the carrier transport mechanism in a semiconductor element including high density, and to perform highly accurate device simulation of a polycrystalline semiconductor element.
(Design procedure of semiconductor device of the present invention)
Next, a procedure for optimizing device parameters of a semiconductor element to be designed by the above-described device simulation method will be described below.
[0034]
FIG. 5 is a block diagram showing a device simulator for simulating device characteristics of the semiconductor device of the present invention.
[0035]
The device simulator 31 includes a control unit 32, an input unit 33, a calculation unit 34, and an output unit 35. The control unit 32 controls the entire device simulator 31.
[0036]
The input means 33 includes a simulation condition input means 36 for inputting simulation conditions such as a gate voltage to be applied, and a crystallinity such as a structure and shape of a semiconductor element and a polycrystalline grain size operating as an active layer. The device structure input means 37 for inputting parameters, and the calculation means 34, the carrier flow density calculation means 38 for calculating the density of the carrier flow flowing in the active layer based on the above-described theory, and the result and input. A device characteristic calculation means 39 for calculating a desired device characteristic based on various conditions inputted by the means 33 is constituted.
[0037]
FIG. 6 shows a processing procedure when a device simulation is executed by the device simulator 31.
[0038]
First, simulation data such as a gate voltage condition of a semiconductor element is input by the simulation condition input unit 36 of the input unit 33 (S46).
[0039]
Further, data on the device structure such as the structure and shape of the semiconductor element is input from the device structure input means 37 (S47). Here, the device structure data includes, for example, gate oxide film thickness, source / drain spacing, crystallinity of the active layer, contact hole shape, wiring shape, dopant concentration, etc., and can be freely selected according to the device to be designed. It can be set. The device structure data may be input directly by a user of the device simulator 31 or input data calculated by a process simulator provided separately from the device simulator 31. Also good.
[0040]
The carrier flow density calculation means 38 receives the device structure data from the device structure input means 37 and calculates the carrier flow density based on the relational expression described above.
[0041]
The device characteristic calculation means 39 receives the simulation data and the calculated carrier flow density value, calculates device characteristics such as CV characteristics (S49), and the result is output by the output means 35.
[0042]
The user of the device simulator 31 repeats the procedure shown in FIG. 6 while comparing the output device characteristics with the design characteristics, so that the gate oxide film thickness, the source-drain spacing, the crystallinity of the active layer, the contact By optimizing device parameters such as hole shape, wiring shape, and dopant concentration, a device structure capable of obtaining desired characteristics is determined.
(Polycrystalline thin film transistor considering grain boundaries)
Next, a manufacturing process of the thin film transistor of the present invention having the device structure determined by the above device simulation will be described with reference to the drawings.
[0043]
FIG. 3 is a diagram showing a manufacturing process of the polycrystalline thin film transistor of the present invention. Note that in this embodiment, a case where a silicon thin film is formed as a semiconductor layer for manufacturing a transistor over an insulating substrate such as glass will be described as an example. The polycrystalline silicon thin film transistor of this example is a laser crystallized polycrystalline silicon thin film transistor in which the carrier transport mechanism of the crystal grain boundary is particularly dominant with respect to the transistor characteristics.
[0044]
First, a silane-based reactive gas is used on the insulating substrate 1 as a silicon atom supply source. For example, a low pressure CVD (LPCVD) method using a disilane (Si ₂ H ₆ ) gas, or a monosilane (SiH ₄ ), for example. ) An amorphous silicon film 2 is formed by plasma enhancement CVD (PECVD) using gas. Here, the silicon film 2 is formed so that the film thickness is a film thickness calculated in advance as an optimum film thickness by the above-described device simulation.
[0045]
Following this, the amorphous silicon film 2 is recrystallized by supplying energy necessary for crystallizing amorphous silicon atoms from the outside to form the polycrystalline silicon film 2 (FIG. 3). (A)). Here, the crystallinity such as the grain size and crystal orientation of the polycrystal is preset so that various characteristics such as required carrier mobility can be obtained by the above-described device simulation. In addition, as for the recrystallization technique, an optimum technique and conditions are selected in order to realize such crystallinity. For example, as shown in FIG. 3A, a laser crystal irradiated with light using an excimer laser or the like. A method of performing solid phase growth by performing heat treatment in a chemical conversion method or a heat treatment furnace is selected.
[0046]
The polycrystalline silicon film 2 thus formed is subjected to desired patterning using a photolithography technique, and further a dielectric film 3 to be used later as a gate oxide film is formed. This dielectric film is, for example, a silicon oxide film (SiO _x ) formed by a thermal CVD method, and is deposited on the entire surface of the substrate (FIG. 3B).
[0047]
Next, impurity doping is performed on the active layer, and an ion implantation method is employed in which precise doping level control can be performed easily and accurately. The type of element to be doped is determined by the design of the thin film transistor. In this embodiment, the case of an n-type thin film transistor is shown. Group III impurity boron (B ) Is injected (FIG. 3B). The doping amount to be ion-implanted is set to a value calculated in advance by simulation.
[0048]
Subsequent to the doping step into the active layer, a thin film for forming the gate electrode 4 is formed. A thin film such as a metal or polysilicon selected as a gate electrode material is deposited on the entire surface of the substrate by a CVD method or a sputtering method, and then patterned to have a desired gate electrode shape by photolithography (FIG. 3 ( c)).
[0049]
Furthermore, in order to make the conductivity type of the source region 5 and the drain region 6 n ⁺ type, for example, phosphorus (P) is ion-implanted (FIG. 3C). In this step, phosphorus (P) is implanted in a self-aligning manner using the already patterned gate electrode 4 as a mask. That is, there is no phosphorus implantation into the polycrystalline silicon film region directly under the gate electrode, and the state in which boron ions are implanted in the step of FIG. 3B is maintained.
[0050]
After boron implantation into the active layer region and phosphorus implantation into the source region 5 and drain region 6, the crystal lattice state disturbed by these ion implantations is recovered and electrically activated using boron and phosphorus as dopants. The process for making it into is performed.
[0051]
Various methods are known as the dopant activation method. For example, if a thermal activation method for keeping the substrate at a high temperature for a long time is selected, the dopant activation can be performed with a simple apparatus at a low cost. There is an advantage that a thin film transistor can be manufactured. The dopant activation is not limited to the above-described thermal activation method, and may be performed by, for example, a laser activation method. When the dopant activation is performed by the laser activation method, the same laser light source as that used in the crystallization process of the amorphous silicon thin film shown in FIG. 3A may be used. It is good also as providing and using the laser light source of another different wavelength.
[0052]
Subsequent to the dopant activation, an interlayer insulating film 7 is formed to electrically insulate the individual transistors formed on the substrate from each other (FIG. 3D). Further, the source region 5 and the drain region 6 are formed. The dielectric film 3 and the interlayer insulating film 7 formed thereon are removed by a photolithography technique to form contact holes, and then a thin film for the source electrode 8 and the drain electrode 9 is deposited, and then the source electrode 8 and The drain electrode 9 is patterned. In this way, a polycrystalline thin film transistor is completed (FIG. 3D).
[0053]
In the above embodiment, an example in which an ion implantation method involving mass spectrometry of a dopant is selected as a doping method for the active layer is shown, but the doping method is not limited to this. That is, other doping methods that perform doping without mass analysis of dopants may be used. In particular, when an ion doping method without mass spectrometry is employed, structural defects such as dislocations existing in the active layer, gate insulating film, substrate insulating film, or their interface due to ion doping, and electric charges such as fixed charges There is an advantage that it is possible to reduce the mechanical defects. On the other hand, when ion implantation with mass spectrometry is adopted, structural defects such as dislocations and fixed charges induced in the active layer, gate insulating film, substrate insulating film, or their interfaces due to excessive ion bombardment or fixed charges It is possible to suppress electrical defects such as these. Therefore, an optimal method may be selected as appropriate in order to obtain desired thin film transistor characteristics.
[0054]
Further, the doping to the active layer is not necessarily performed after the polycrystallizing process of the amorphous silicon layer, and may be performed simultaneously with the film formation of the amorphous silicon. For example, when doping is performed by ion doping, an amorphous silicon film is formed by simultaneously using a gas containing a silicon element and a gas containing a dopant element as a base material of a transistor, thereby containing impurities as a dopant. An amorphous silicon film is obtained.
[0055]
Needless to say, the impurity doping process to the active layer region, the source region, and the drain region may be set in any order of manufacturing steps as long as the doping to these layers is realized. The active layer region may not be doped.
[0056]
In this example, the device simulation method of the present invention was applied to a polycrystalline silicon thin film transistor using polycrystalline silicon as an active layer. However, a polycrystalline semiconductor using other polycrystal such as GaAs as an active layer. It can also be applied to elements.
[0057]
【The invention's effect】
As described above, according to the present invention, it is possible to obtain a semiconductor element having an optimized device structure in a polycrystalline silicon thin film transistor in which the carrier transport mechanism of the grain boundary is particularly dominant to the transistor characteristics. It becomes possible.
[Brief description of the drawings]
FIG. 1 is a diagram showing the structure of a polycrystalline silicon thin film transistor.
FIG. 2 is a diagram comparing the potential distribution in the vicinity of a grain boundary when the Thermic Emission effect is taken into consideration and when the effect is not taken into account.
FIG. 3 is a diagram comparing the free carrier density distribution in the vicinity of a crystal grain boundary when the Thermic Emission effect is considered and when the effect is not considered.
FIG. 4 is a diagram illustrating a manufacturing process of a polycrystalline silicon thin film transistor.
FIG. 5 is a block diagram of a device simulator for manufacturing a semiconductor device of the present invention.
FIG. 6 is a flowchart for explaining the operation of a device simulator for manufacturing the semiconductor device of the present invention.
[Explanation of symbols]
13 Grain boundary 14 Source region 15 Drain region 16 Substrate 17 Gate insulating film 18 Gate electrode

Claims (5)

A device simulation method of a polycrystalline semiconductor element using a polycrystalline semiconductor in an active layer ,
A device simulation method for a polycrystalline semiconductor device, characterized in that a carrier flow density passing through a crystal grain boundary is calculated by the following equation.
J _t = (1−c / 2) v (n ₁ −n ₂ ) / 4
(1-c / 2) v / 4 = A * T 2 / (qN e)
J _t : Carrier flow density c: Rate at which the carrier flow is trapped at the crystal grain boundary v: Electron average heat speed n ₁ : Carrier density on one side of the crystal grain boundary n ₂ : Carrier density A on the other side of the crystal grain boundary A ^* : Effective Richardson constant T: Absolute temperature q: Elementary charge N _e : Effective state density 2. A device simulation method for a polycrystalline semiconductor device according to claim 1, wherein the polycrystalline semiconductor device is a thin film transistor using polycrystalline silicon as an active layer. 2. The device simulation method for a polycrystalline semiconductor device according to claim 1, wherein the polycrystalline semiconductor device is a laser crystallized polycrystalline silicon thin film transistor using polycrystalline silicon formed in an active layer by a laser crystallization process. A device simulation method for a polycrystalline semiconductor device, characterized by A method for designing a polycrystalline semiconductor device using a polycrystalline semiconductor in an active layer,
Design method of the polycrystalline semiconductor element characterized in that the carrier flow density passing through the grain boundary, having a device simulation step of the polycrystalline semiconductor element is calculated using the following equation.
J _t = (1−c / 2) v (n ₁ −n ₂ ) / 4
(1-c / 2) v / 4 = A * T 2 / (qN e)
J _t : Carrier flow density c: Rate at which the carrier flow is trapped at the crystal grain boundary v: Electron average heat speed n ₁ : Carrier density on one side of the crystal grain boundary n ₂ : Carrier density A on the other side of the crystal grain boundary A ^* : Effective Richardson constant T: Absolute temperature q: Elementary charge N _e : Effective state density A method of manufacturing a polycrystalline semiconductor device using a polycrystalline semiconductor in an active layer,
Method for manufacturing a polycrystalline semiconductor device, characterized in that the carrier flow density passing through the grain boundary, having a device simulation step of the polycrystalline semiconductor element is calculated using the following equation.
J _t = (1−c / 2) v (n ₁ −n ₂ ) / 4
(1-c / 2) v / 4 = A * T 2 / (qN e)
J _t : Carrier flow density c: Rate at which the carrier flow is trapped at the crystal grain boundary v: Electron average heat speed n ₁ : Carrier density on one side of the crystal grain boundary n ₂ : Carrier density A on the other side of the crystal grain boundary A ^* : Effective Richardson constant T: Absolute temperature q: Elementary charge N _e : Effective state density

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