JP2003110114A - Device simulation method for semiconductor element and semiconductor element using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element having an optimized device structure which includes at lease one interface between a semiconductor and an insulator or a grain boundary made between semiconductor crystal grains. SOLUTION: In setting a simulation mesh for determining a device parameter for designing a device, the interface or the grain boundary (13) is expressed by an extremely small region (14), a defect level is set in the extremely small region, potential distribution is calculated by setting the mesh width adjacent to the extremely small region at 10% or below of the mesh width of the extremely small region, and the device parameter is determined based on the calculated potential distribution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a thin film transistor using a polycrystalline semiconductor in an active layer.

[0002]

2. Description of the Related Art A polycrystalline thin film transistor is a semiconductor element using a polycrystalline semiconductor in an active layer, and is used to realize a light and thin display device represented by a liquid crystal display or an electroluminescence display, and a device such as a scanner. Widely used as a device.

In general, prior to the manufacture of semiconductor elements, device simulation is performed in which the device characteristics are predicted using the structure of the semiconductor device and the physical properties of the materials used as parameters, and the operation of the device is analyzed. The final device structure, manufacturing conditions, etc. are determined based on the result.

Therefore, even if it is possible to predict the device characteristics in the development stage with high accuracy even for a polycrystalline thin film transistor, it is expected that it can be a useful tool for optimizing the device structure. An effective device simulation method for a crystalline thin film transistor has not been proposed, and as a result, there is a problem that it is difficult to determine the structure and manufacturing conditions of a transistor having desired device characteristics.

[0005]

DISCLOSURE OF THE INVENTION The inventor of the present invention has made a detailed study on the problems in applying the conventional device simulation method to a polycrystalline thin film transistor, and as a result, determined the device structure of the polycrystalline thin film transistor. In order to determine the device structure, etc., the carrier transport phenomenon in the crystal is correctly handled in consideration of the defect level existing at a high density in the interface between the semiconductor and the insulating film and / or in the active layer. Has proved to be extremely important.

Therefore, an object of the present invention is to provide a polycrystalline thin film transistor designed by determining device parameters based on a device simulation that accurately handles the carrier trapping phenomenon due to the above defect level.

[0007]

In order to achieve the above object, a method for simulating a device of a semiconductor device according to the present invention is directed to a semiconductor device including at least one grain boundary in an interface between a semiconductor and an insulator or in a polycrystalline semiconductor. A device simulation method, in which a model of a semiconductor device is divided into a mesh having a two-dimensional or three-dimensional structure, the interface or the grain boundary is represented by a minute area of the mesh, and a defect level is set in the minute area. Then, the physical equations such as the potential equation and the carrier continuity equation are solved in each mesh, in which the width of the mesh adjacent to the minute region is set narrower than the width of the mesh of the minute region, It is characterized by

According to such a method, it is possible to realize a highly accurate device simulation method for a semiconductor device.

Preferably, the width of the mesh adjacent to the minute area is 10% of the width of the mesh of the minute area.
It is set below. As a result, the accuracy of the device simulation method of the semiconductor element can be more reliably realized.

Preferably, the mesh width is continuously changed from the mesh adjacent to the minute area as the distance from the minute area increases. As a result, high convergence of the device simulation method for semiconductor devices can be realized.

[0011] Preferably, the mesh width continuously changes from the mesh adjacent to the minute area as the distance from the minute area increases, and the width ratio of the meshes adjacent to each other is within the range of 0.5 to 2. Is set to. As a result, the convergence of the device simulation method of the semiconductor element can be more reliably realized.

Preferably, the finite element method is used to solve the physical equations such as the potential equation of each mesh and the carrier continuity equation. As a result, it is possible to realize a highly accurate and highly convergent device simulation method for semiconductor devices using the finite element method.

Preferably, the difference method is used to solve the physical equations such as the potential equation of each mesh and the carrier continuity equation. As a result, it is possible to realize a highly accurate and highly convergent device simulation method for semiconductor devices using the difference method.

Further, the semiconductor element of the present invention is a semiconductor element including at least one of an interface between a semiconductor and an insulator or a grain boundary between semiconductor crystal grains, and in setting a simulation mesh for determining device parameters,
The interface and / or the grain boundary is expressed by a minute area, a defect level is set in the minute area, and the mesh width adjacent to the minute area is set to 10% or less of the mesh width of the minute area. The potential distribution is calculated, and device parameters are determined based on the calculated potential distribution to design.

Preferably, the meshes are set such that the ratio of mesh widths adjacent to each other is 0.5 or more and 2.0 or less.

By such handling, it becomes possible to provide a semiconductor element designed by deciding device parameters based on a device simulation that accurately handles the carrier trapping phenomenon due to the defect level.

Further, preferably, the semiconductor device of the present invention is a polycrystalline thin film transistor using polycrystalline silicon for an active layer, and more preferably, the active layer is polycrystallized by a laser crystallization process. It is a polycrystalline thin film transistor.

With such a structure, it is possible to provide an element having an optimized device structure in a laser crystallized polycrystalline thin film transistor in which the carrier trapping phenomenon at the crystal grain boundary is particularly important in device design.

[0019]

DETAILED DESCRIPTION OF THE INVENTION The contents of a semiconductor device of the present invention will be described in detail below with reference to the drawings. (Handling of Defect Levels) FIG. 4 is a structural cross-sectional view of a polycrystalline thin film transistor having an active layer made of a polycrystalline semiconductor.

The polycrystalline thin film transistor has C on the substrate 1.
A gate region, a source region 5 and a drain region 6 are formed on a polycrystalline film grown by the VD method or the like, and a gate insulating film 3 grown by a thermal oxidation method or the like is formed on the polycrystalline film. There is. The gate electrode 4 is formed on the gate insulating film.
Is formed, and the polycrystalline film under the gate electrode 4 is operated as a gate region.

In FIG. 4, from the substrate 1 to the gate insulating film 3
A straight line that obliquely penetrates through the polycrystalline semiconductor film toward is a crystal grain boundary 12 formed by semiconductor crystals having different crystal orientations. One of the characteristics of the polycrystalline thin film transistor when compared with the single crystal thin film transistor is that since the semiconductor film forming the transistor is made of polycrystal, crystal grains having different crystal orientations exist in the semiconductor film. As a result, the crystal grain boundaries 12 exist between the crystal grains.

In general, the grain boundary has a high density of carrier defect levels, and a potential barrier is generated by the charges of the trapped carriers (for example, M. Kimura e).
tal. J. Appl. Phys. 89 (2001)
596). That is, it is known that the crystal grain boundaries act as trap centers for carriers, and that carrier traps exist at high density in the vicinity of the crystal grain boundaries. The so-called potential barrier is formed by locally accumulating electric charges by the amount of electric charges. When a potential barrier is formed in the vicinity of the crystal grain boundary due to the capture of carriers, free carriers having lower thermal excitation energy than the potential barrier cannot pass through the crystal grain boundary.

Further, the thin film transistor has another feature that defect levels are present at a high density at an interface between a semiconductor and an insulating film, as compared with a crystalline semiconductor element.

The defect level existing at the interface between the semiconductor and the insulating film traps free carriers and charges them, so that the carriers normally start from the gate electrode and enter the semiconductor to generate free carriers. The electric lines of force acting in this way are terminated at the interface between the semiconductor and the insulating film. For this reason,
This results in a relative decrease in free carriers in the semiconductor (see, for example, M. Kimura et al., Jp.
n. J. Appl. Phys. 40 (2001) 11
2).

Therefore, in device simulation when designing a polycrystalline thin film transistor, high-precision simulation should be performed only by sufficiently considering the defect levels existing at the crystal grain boundaries and the interface between the semiconductor and the insulating film. You can

Generally, in order to execute a device simulation, a physical system to be handled is divided into a large number of meshes, and an operation is executed so that a boundary condition defined for each mesh is satisfied. Therefore, the accuracy of the simulation result is determined by how the mesh is set. In other words, the effectiveness as a device simulation method is determined by what kind of mesh is set in the crystal grain boundary in the semiconductor, the interface, and the region in the vicinity thereof.

FIG. 1 is a diagram showing a method of dividing a mesh for device simulation used in the conventional method and in the design of a semiconductor device of the present invention. Here, a method of dividing a mesh in the vicinity of the interface 13 between the semiconductor 11 and the insulator 12 is assumed, but the same applies to a grain boundary between crystal grains forming a polycrystal. Can be handled. Further, in this figure, the interface 13 is represented as a minute region 14, and a defect level is set in the minute region 14.

FIG. 1B shows a mesh division method adopted for designing the semiconductor device of the present invention. In this mesh division method, the mesh is set so that the width of the mesh 15 adjacent to the micro area 14 is narrower than the width of the mesh of the micro area 14. Specifically, the width of the mesh 15 adjacent to the micro area 14 is set to 10% or less of the mesh width of the micro area 14.

In the mesh thus set,
Consider a case where the finite element method or the difference method is applied to the element 16 adjacent to the minute region 14 to execute the calculation of the physical quantity.

Since the node 17 of the element 16 adjacent to the micro region 14 facing the micro region 14 belongs to the micro region 14, the density of defect levels is set high at the node 17 and the calculated charge density is obtained. However, since the width of the mesh 15 adjacent to the micro area 14 is set narrower than the mesh width of other areas, the peculiarity of the micro area 14 is executed over the entire area. The effect on the simulation results is not large. Approximately, the simulation result will be as if the width of the minute region 14 was increased and the number of all defect levels was also increased.
The degree of increase can be suppressed to 10% or less. This ensures the accuracy of the simulation result.

On the other hand, in the conventional mesh division method shown in FIG. 1A, the mesh width of the minute area 14 and the width of the mesh 15 adjacent to the minute area 14 are set to be approximately the same.

When the finite element method or the difference method is applied to the element 16 adjacent to the minute region 14 using the mesh thus divided, the nodes 17 facing the minute region of the element 16 adjacent to the minute region 14 are minute. Since the node belongs to the region 14, the density of the defect level is calculated to be high at the node 17, and the value of the charge density is greatly affected. However, the portion other than the node 17 of the element 16 does not belong to the minute region 14 and should actually be hardly affected by this charge density.
This difference causes reduction in accuracy of the simulation result. Approximately, the simulation result is as if the width of the minute region 16 increased and the number of all defect levels also increased. In such a case, it is conceivable to switch the numerical value such as the charge density of the contact point 17 facing the small area between the element belonging to the small area and the element 16 adjacent to the small area. The value at will have two different values, creating a physically impossible state. Moreover, such a thing is not allowed by the finite element method or the difference method. Therefore, the mesh division method shown in FIG. 1B described above is an effective means.

Further, in the present embodiment, the mesh width of the mesh 15 adjacent to the minute area 14 continuously changes as the distance from the minute area 14 increases, thereby ensuring high convergence of the simulation result. . Specifically, the width of the mesh 15 adjacent to the minute area 14 is set so that the ratio of the mesh widths adjacent to each other is 0.5 to 2.0.

In this embodiment, the finite element method and the difference method are used as the calculation method for solving the physical equations such as the potential equation and the carrier continuity equation in each mesh. However, the calculation method is limited to these. It is not necessary and may be the case by other solution methods.

More specifically, the calculation based on which the device simulation is actually executed by using the mesh set as shown in FIGS. 1A and 1B will be described.

First, the Poisson's equation Δψ = −ρ / ε (ψ is the potential, ρ is the charge volume density, ε is the dielectric constant) is adopted as the potential equation, and the carrier continuity equation ∇ of electron and hole is defined as the carrier transport equation. _{· {(-n n · μ n} · E) - (D n · ∇n n)} - G = 0 ∇ · {(-n p · μ p · E) - (D p · ∇n p)} - G = 0 (n _n or n _p is the electron or hole carrier density, μ
_n or μ _p is the electron or hole mobility, E is the electric field strength, D _n or D _p is the electron or hole diffusion coefficient, and G is the carrier generation / annihilation ratio.

Further, by adopting the finite element method or the difference method as the formulating method and using various matrix solving methods as the solving method of the equations, these equations are repeatedly solved and converged, and finally the potential, the carrier density, the carrier Flow densities and the like are calculated, and then simulations such as capacitance-voltage characteristics and transistor characteristics are executed.

In the simulation method based on the Poisson equation, when an interface or a grain boundary is treated as a surface region, ρ included in the right side of the Poisson equation is used.
Becomes ρ = ∞ at the grain boundary, and ψ cannot be analytically obtained. Therefore, it becomes impossible to calculate E that should be calculated from ψ by the electron or hole carrier continuity equation.

On the other hand, according to the device simulation method of the present invention in which the crystal grain boundary is treated as a minute region, the problem that the solution corresponding to the physical quantity to be obtained diverges is solved, and a highly accurate device simulation can be performed. It will be possible.

The following is a result obtained by assuming the MOS structure and executing the simulation while changing the width of the mesh 15 adjacent to the minute region 14.

FIG. 2 assumes a MOS-structured transistor, and a small region 14 is formed at the interface 13 between the semiconductor 11 and the insulator 12.
FIG. 6 is a diagram showing a potential distribution when the simulation is executed by setting the above, changing the width of the mesh 15 adjacent to the minute region 14.

The horizontal axis of FIG. 2 represents the position of the gate electrode of the MOS structure transistor as 0 nm, and the relative distance from this is displayed in the depth direction.
insulator 12 up to nm, position 100 nm to 150 nm
Up to semiconductor 11, position 150 nm to the right corresponds to the insulator of the substrate.

By changing the voltage applied to the gate electrode, the potential distribution in the semiconductor 11 changes. The width of the minute region is 1 nm, and
The width of the mesh 15 adjacent to is 10%, 20%, 50
% And compared for comparison.

As is apparent from FIG. 2, when the width of the mesh 15 adjacent to the minute region 14 is 10%, 20% and 50%, there is a slight difference in the potential distribution. Comparing these results with the potential distribution measurement result of the transistor having the actual MOS structure, it was confirmed that the result shows a good agreement with the simulation result when the width of the mesh 15 adjacent to the minute region 14 is 10%. Therefore,
It can be seen that the larger the mesh 15 adjacent to the minute region 14, the more error occurs compared to the potential distribution actually generated in the device. This error causes an error in the carrier density distribution in the crystal and the electric conductivity of the semiconductor.

In this embodiment, the MOS transistor is assumed, but other semiconductor elements may be used.
For example, the device simulation method of the present invention is also effective for a thin film transistor formed by a low temperature process of 600 degrees Celsius or less and a thin film transistor crystallized by laser irradiation.

In the present embodiment, the simulation is performed assuming electrons as free carriers and acceptor-like traps as carrier traps. However, holes are assumed as free carriers and donor-like traps as carrier traps. Needless to say, a similar analysis can be performed. (Design Procedure of Semiconductor Element of the Present Invention) Next, the procedure for optimizing the device parameters of the semiconductor element to be designed by the above-described device simulation method will be described below.

FIG. 5 is a block diagram showing a device simulator for simulating the device characteristics of the semiconductor device of the present invention.

The device simulator 31 includes the control means 3
2, input means 33, calculation means 34, output means 35
The control means 32 is a means for controlling the entire device simulator 31.

The input means 33 includes a simulation condition input means 36 for inputting a simulation condition such as a gate voltage to be applied, a structure / shape of a semiconductor element, a grain size of a polycrystal operating as an active layer, and the like. Device structure input means 3 for inputting crystallinity parameters
7, the calculation means 34 includes a carrier flow density calculation means 38 for calculating the density and the like of the carrier flow flowing in the device based on the above-mentioned theory, and the result and the kind of the variety inputted by the input means 33. It is composed of a device characteristic calculation means 39 for calculating a desired device characteristic based on the condition.

FIG. 6 shows a processing procedure when the device simulator 31 executes a device simulation.

First, the simulation data such as the gate voltage condition of the semiconductor element is input by the simulation condition input means 36 of the input means 33 (S46).

Data relating to the device structure such as the structure and shape of the semiconductor element is also input to the device structure input means 37.
Is input from (S47). Here, the device structure data (device parameter) is, for example, the gate oxide film thickness, the source / drain spacing, the crystallinity of the active layer, the contact hole shape, the wiring shape, the dopant concentration, etc. It can be freely set accordingly. In addition,
The device structure data is the device simulator 31.
May be directly input by the user, or may be data input by a process simulator provided separately from the device simulator 31.

The carrier flow density calculation means 38 receives the device structure data from the device structure input means 37 and calculates the carrier flow density and the like based on the above-mentioned relational expression.

Then, the device characteristic calculation means 39 receives the simulation data and the calculated values of the carrier flow density and the like and calculates the device characteristics such as the CV characteristic (S49), and the result is outputted by the output means 35. Is output.

The user of the device simulator 31 repeats the procedure shown in FIG. 6 while comparing the output device characteristics with the design characteristics, to thereby obtain the gate oxide film thickness, the source / drain spacing, and the crystal of the active layer. The device structure that obtains the desired characteristics is determined by optimizing the device parameters such as conductivity, contact hole shape, wiring shape, and dopant concentration. (Polycrystalline thin film transistor in consideration of grain boundaries) Next,
A manufacturing process of a thin film transistor to which the device simulation method of the present invention is applied will be described with reference to the drawings.

FIG. 3 is a diagram showing a manufacturing process of the polycrystalline thin film transistor of the present invention. In this embodiment, a case where a silicon thin film is formed as a semiconductor layer for forming a transistor on an insulating substrate such as glass will be described as an example. In addition, the polycrystalline silicon thin film transistor of this embodiment is a laser crystallized polycrystalline silicon thin film transistor which is formed by a low temperature process of 600 ° C. or less and the carrier transport mechanism of crystal grain boundaries is particularly dominant to the transistor characteristics. .

First, on the insulating substrate 1, a silane-based reactive gas is used as a silicon atom supply source, for example, low pressure CVD using disilane (Si ₂ H ₆ ) gas.
(LPCVD) method or plasma enhancement CVD (PECV) using, for example, monosilane (SiH ₄ ) gas
The amorphous silicon film 2 is formed by the method D). Here, the silicon film 2 is formed so that the film thickness thereof is a film thickness calculated in advance as an optimum film thickness by the device simulation described above.

Subsequently, the formed amorphous silicon film 2 is re-crystallized by supplying the energy necessary for crystallization of amorphous silicon atoms from the outside to form a polycrystalline silicon film 2. (Fig. 3
(A)). Here, the crystallinity such as the grain size and crystal orientation of the polycrystal is set in advance so that various characteristics such as the required carrier mobility can be obtained by the above device simulation. Further, in the recrystallization method, an optimum method and conditions are selected in order to realize such crystallinity. For example, as shown in FIG. 3A, a laser crystal for light irradiation using an excimer laser or the like is used. A chemical treatment method or a method of performing solid phase growth by performing heat treatment in a heat treatment furnace is selected.

The polycrystalline silicon film 2 thus formed is subjected to desired patterning by using a photolithography technique, and further a dielectric film 3 which will be used as a gate oxide film later is formed. It This dielectric film is, for example, a silicon oxide film (SiO _x ) formed by a thermal CVD method, and is deposited on the entire surface of the substrate (FIG. 3).
(B)).

Next, impurity doping is performed on the active layer, but an ion implantation method is employed which enables easy and accurate doping level control with high precision. The type of element to be doped is determined by the design of the thin film transistor, but in the case of this embodiment, the case of an n-type thin film transistor is shown. First, boron (B), which is a group III impurity that acts as an acceptor in the silicon crystal for adjusting the threshold value, is implanted (FIG. 3B). The doping amount to be ion-implanted is set to a value calculated in advance by simulation.

Following the doping step into the active layer, a thin film for forming the gate electrode 4 is formed. After depositing a thin film of metal or polysilicon selected as a gate electrode material on the entire surface of the substrate by a CVD method or a sputtering method, patterning is performed by photolithography so as to obtain a desired gate electrode shape (FIG. 3).
(C)).

Further, in order to make the conductivity type of the source region 5 and the drain region 6 n ⁺ type, for example, phosphorus (P) is ion-implanted (FIG. 3C). In this step, the already patterned gate electrode 4 is used as a mask to implant phosphorus (P) in a self-aligned manner. That is, there is no phosphorus implantation into the polycrystalline silicon film region immediately below the gate electrode, and the state in which boron ions are implanted in the step of FIG. 3B is maintained.

After the implantation of boron into the active layer region and the implantation of phosphorus into the source region 5 and the drain region 6, the crystal lattice state disturbed by these ion implantations is restored, and boron and phosphorus are used as dopants to generate an electrical charge. Processing for activating the image is performed.

Various methods are known as the method for activating the above-mentioned dopants. For example, if a thermal activation method for holding the substrate at a high temperature for a long time is selected, the dopant activation can be executed with a simple apparatus. There is an advantage that a thin film transistor can be manufactured at low cost. Further, the dopant activation is not limited to the above thermal activation method, and may be, for example, a laser activation method. When the dopant activation is performed by the laser activation method, the same laser light source as the laser used in the crystallization process of the amorphous silicon thin film shown in FIG. 3A may be used. A laser light source having another different wavelength may be provided and used.

Subsequent to the above dopant activation, an interlayer insulating film 7 for electrically insulating the individual transistors formed on the substrate from each other is formed (FIG. 3D), and further,
The dielectric film 3 and the interlayer insulating film 7 formed on the source region 5 and the drain region 6 are removed by photolithography to open contact holes, and then thin films for the source electrode 8 and the drain electrode 9 are deposited. After that, the source electrode 8 and the drain electrode 9 are patterned. In this way, a polycrystalline thin film transistor is completed (FIG.
(D)).

In the above-mentioned embodiment, an example in which the ion implantation method with mass spectrometry of the dopant is selected as the doping method for the active layer is shown, but the doping method is not limited to this. That is, another doping method may be used in which doping is performed without mass spectrometry of the dopant. In particular, when adopting the ion doping method without mass spectrometry, structural defects such as dislocations existing at the active layer, the gate insulating film, the substrate insulating film, or their interfaces due to the ion doping, and electrical charges such as fixed electric charges. There is an advantage that it is possible to reduce the physical defects. On the other hand, when the ion implantation method accompanied by mass spectrometry is adopted, structural defects such as dislocations or fixed charges induced in the active layer, the gate insulating film, the substrate insulating film, or their interfaces due to excessive ion bombardment are used. It is possible to suppress electrical defects such as. Therefore, an optimum method may be appropriately selected to obtain desired characteristics of the thin film transistor.

Furthermore, the doping of the active layer does not have to be performed after the step of polycrystallizing the amorphous silicon layer, and may be performed simultaneously with the film formation of the amorphous silicon. For example, in the case of performing doping by an ion doping method, an amorphous silicon film is formed by using a gas containing a silicon element, which is a base material of a transistor, and a gas containing a dopant element at the same time, so as to contain impurities serving as a dopant. An amorphous silicon film is obtained.

Needless to say, the impurity doping process for the active layer region, the source region, and the drain region may be set in any manufacturing process order as long as the doping of these layers is realized.

In this embodiment, the device simulation method of the present invention is applied to the polycrystalline silicon thin film transistor using polycrystalline silicon for the active layer.
It can also be applied to a polycrystalline semiconductor device using other polycrystal such as GaAs in the active layer.

[0070]

As described above, in the device simulation method for a semiconductor device of the present invention, the model of the semiconductor device is divided into meshes having a two-dimensional or three-dimensional structure, and the interface between the semiconductor and the insulator or the semiconductor crystal is divided. The grain boundary is expressed by a minute area of the mesh, and the width of the mesh adjacent to the minute area is set to be narrower than the width of the mesh of the minute area. As a result, the influence of the charge density in the minute region on the simulation of the entire region is reduced, and the device simulation can be made highly accurate.

Further, according to the present invention, in setting a mesh for simulation for determining a device parameter of an interface between a semiconductor and an insulator or at least one grain boundary between semiconductor crystal grains, the interface or the grain boundary is set. Is expressed by a micro area, a defect level is set in the micro area, the mesh width adjacent to the micro area is set to 10% or less of the mesh width of the micro area to calculate the potential distribution, and We decided to design the device by determining the device parameters based on the potential distribution.

By such handling, it becomes possible to provide a semiconductor element designed by determining device parameters based on a device simulation that accurately handles the carrier trapping phenomenon due to the defect level, and in particular, the carrier trapping phenomenon at a grain boundary. It is possible to provide an element having an optimized device structure in a laser crystallization polycrystalline thin film transistor, which is particularly important in device design.

[Brief description of drawings]

FIG. 1A is a diagram showing a mesh division method adopted in a conventional device simulation. FIG. 1B is a diagram showing a mesh division method adopted in the device simulation of the present invention.

FIG. 2 is a result of simulating a potential distribution assuming a transistor having a MOS structure.

FIG. 3 is a diagram illustrating a manufacturing process of a polycrystalline thin film transistor.

FIG. 4 is a structural cross-sectional view of a polycrystalline thin film transistor.

FIG. 5 is a block diagram of a device simulator for manufacturing a semiconductor device of the present invention.

FIG. 6 is a flowchart for explaining the operation of the device simulator for manufacturing the semiconductor device of the present invention.

[Explanation of symbols]

11 Semiconductor 12 insulator 13 Interface 14 Micro area 15 mesh adjacent to micro area 16 Elements adjacent to a micro area 17 Nodes facing the micro area

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B046 AA08 JA07                 5F110 AA25 BB01 CC02 DD02 EE02                       EE09 EE44 EE45 FF02 FF23                       FF29 GG02 GG04 GG13 GG32                       GG44 GG45 GG47 GG51 GG52                       HJ01 HJ12 HJ13 HJ23 PP01                       PP03 QQ11

Claims (10)

[Claims] 1. A device simulation method for a semiconductor device including an interface between a semiconductor and an insulator or at least one grain boundary in a polycrystalline semiconductor, wherein a model of the semiconductor device is divided into meshes having a two-dimensional or three-dimensional structure. Then, the interface or the grain boundary is expressed by a minute area of the mesh, a defect level is set in the minute area, and a physical equation such as a potential equation or a carrier continuity equation is solved in each mesh, 2. The device simulation method for a semiconductor device according to, wherein the width of the mesh adjacent to the micro area is set narrower than the width of the mesh of the micro area. 2. The device simulation method for a semiconductor device according to claim 1, wherein the width of the mesh adjacent to the minute region is set to 10% or less of the width of the mesh of the minute region. Method for device simulation of semiconductor device. 3. The device simulation method for a semiconductor device according to claim 1, wherein the mesh width is continuously changed from a mesh adjacent to the minute region as the distance from the minute region increases. A device simulation method for a semiconductor device, comprising: 4. The device simulation method for a semiconductor device according to claim 3, wherein the mesh width continuously changes from the mesh adjacent to the minute region as the distance from the minute region increases, and the width ratio of the adjacent meshes is increased. Is set so as to fall within a range of 0.5 to 2. A device simulation method for a semiconductor device, comprising: 5. The device simulation method for a semiconductor device according to claim 1, wherein a finite element method is used to solve a physical equation such as a potential equation and a carrier continuity equation of each mesh. Semiconductor device device simulation method. 6. The device simulation method for a semiconductor device according to claim 1, wherein a difference method is used to solve a physical equation such as a potential equation and a carrier continuity equation of each mesh. Method for simulating device of semiconductor device. 7. A semiconductor element including an interface between a semiconductor and an insulator or at least one grain boundary in a polycrystalline semiconductor, wherein in the setting of a simulation mesh for determining device parameters, the interface and / or the A grain boundary is expressed by a minute region, a defect level is set in the minute region, and a mesh width adjacent to the minute region is set to 10% or less of the mesh width of the minute region to calculate a potential distribution, A semiconductor device designed by determining device parameters based on the calculated potential distribution. 8. The semiconductor device according to claim 7, wherein the meshes are set such that a width ratio between adjacent meshes is 0.5 or more and 2.0 or less. 9. The semiconductor element according to claim 7, wherein the semiconductor element is a polycrystalline thin film transistor using polycrystalline silicon for an active layer. 10. The semiconductor according to claim 7, wherein the semiconductor element is a polycrystal thin film transistor manufactured by performing polycrystallization of an active layer by a laser crystallization process. element.