TWI414006B - Formation of in-situ phosphorus doped epitaxial layer containing silicon and carbon - Google Patents

Formation of in-situ phosphorus doped epitaxial layer containing silicon and carbon Download PDF

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TWI414006B
TWI414006B TW096147287A TW96147287A TWI414006B TW I414006 B TWI414006 B TW I414006B TW 096147287 A TW096147287 A TW 096147287A TW 96147287 A TW96147287 A TW 96147287A TW I414006 B TWI414006 B TW I414006B
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Yihwan Kim
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Abstract

Methods for formation epitaxial layers containing silicon and carbon doped with phosphorus are disclosed. The pressure is maintained equal to or above 100 torr during deposition. The methods result in the formation of a film including substitutional carbon. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.

Description

含有矽及碳之磷摻雜磊晶層的原位形成方法In-situ formation method of phosphorus-doped epitaxial layer containing germanium and carbon

本發明之實施例涉及原位(in-situ)形成含矽及碳之磷摻雜磊晶層,特定實施例係關於在諸如金氧半場效電晶體(Metal Oxide Semiconductor Field Effect Transistor,MOSFET)之類的半導體元件中形成此種磊晶層。Embodiments of the present invention relate to in-situ formation of a phosphorus-doped epitaxial layer comprising germanium and carbon, a specific embodiment relating to, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Such an epitaxial layer is formed in a semiconductor element of the type.

流經MOS電晶體之通道的電流量係直接與通道中載子(carrier)的遷移率(mobility)成比例,使用高遷移率之MOS電晶體使得更多電流流動,並造成較快之電路效能。可藉由在通道中產生機械應力而可使載子在MOS電晶體之通道中的遷移率增加。處於壓縮應變之通道(例如生長在矽上之矽鍺通道層)具有大幅增進的電洞遷移率,以提供pMOS電晶體。處於拉伸應變之通道(例如生長在鬆弛矽鍺上的薄矽通道層)可達到大幅增進之電子遷移率,以提供nMOS電晶體。The amount of current flowing through the channel of the MOS transistor is directly proportional to the mobility of the carrier in the channel. The use of a high mobility MOS transistor allows more current to flow and results in faster circuit performance. . The mobility of the carrier in the channel of the MOS transistor can be increased by generating mechanical stress in the channel. The channel in compressive strain (e.g., the channel layer grown on the crucible) has a greatly enhanced hole mobility to provide a pMOS transistor. A channel in tensile strain (e.g., a thin channel layer grown on a relaxed crucible) can achieve a greatly enhanced electron mobility to provide an nMOS transistor.

亦可藉由形成一或多層之碳摻雜矽磊晶層而提供處於拉伸應變下之nMOS電晶體通道,而其係與pMOS電晶體中的壓縮應變SiGe通道為互補。因此,碳摻雜矽及矽鍺磊晶層可分別沉積在nMOS及pMOS電晶體之源極/汲極。源極及汲極區可藉由選擇性Si乾蝕刻而為平坦或凹陷。當經過適當之製造,覆蓋有碳摻雜矽磊晶之nMOS源極及汲極會施加拉伸應變於通道中,並增加nMOS驅動電流。The nMOS transistor channel under tensile strain can also be provided by forming one or more layers of carbon doped germanium epitaxial layers, which are complementary to the compressive strained SiGe channels in the pMOS transistor. Therefore, carbon doped germanium and germanium epitaxial layers can be deposited on the source/drain of the nMOS and pMOS transistors, respectively. The source and drain regions can be flat or recessed by selective Si dry etching. When properly fabricated, the nMOS source and drain covered with carbon-doped germanium epitaxial will apply tensile strain to the channel and increase the nMOS drive current.

為了利用碳摻雜矽磊晶而達到具有凹陷源極/汲極之nMOS電晶體的通道中增進之電子遷移率,係期望藉由選擇性沉積或是後沉積處理而在源極/汲極上形成碳摻雜矽磊晶層。再者,亦期望碳摻雜矽磊晶層含有取代C原子,以在通道中誘導拉伸應變。在碳摻雜矽源極/汲極中具有較多之取代C含量可達到較高之通道拉伸應變。In order to achieve enhanced electron mobility in a channel of a nMOS transistor having a recessed source/drain using carbon-doped germanium epitaxy, it is desirable to form on the source/drain by selective deposition or post-deposition treatment. Carbon doped erbium epitaxial layer. Furthermore, it is also desirable for the carbon-doped germanium epitaxial layer to contain a substituted C atom to induce tensile strain in the channel. A higher channel tensile strain can be achieved by having a higher substitution C content in the carbon-doped germanium source/drain.

一般來說,100奈米以下(sub-100 nm)的CMOS(互補金氧半導體)元件需要小於30 nm之接面深度。通常使用選擇性磊晶沉積而在接面中形成含矽材料(例如:Si、SiGe及SiC)之磊晶層。選擇性磊晶沉積係允許磊晶層生長在矽場區(silicon moat)上,而非生長在介電區域上。選擇性磊晶可以用於半導體元件中,例如作為高起之源極/汲極、源極/汲極延伸部、接點插塞或雙極元件之基底層沉積。In general, CMOS (complementary MOS) components below 100 nm (sub-100 nm) require a junction depth of less than 30 nm. Epitaxial layers of germanium-containing materials (eg, Si, SiGe, and SiC) are typically formed in the junctions using selective epitaxial deposition. Selective epitaxial deposition allows the epitaxial layer to grow on the silicon moat rather than on the dielectric region. Selective epitaxy can be used in semiconductor devices, for example as a high source/drain, source/drain extension, contact plug or base layer deposition of bipolar elements.

典型之選擇性磊晶製程包括沉積反應及蝕刻反應。在沉積製程中,磊晶層係形成在單晶表面上,多晶層則沉積在至少第二層上(例如:既存之多晶層及/或非晶層)。沉積反應及蝕刻反應可同時發生,且對於磊晶層及多晶層有相對不同的反應速率。然而,沉積的多晶層通常較磊晶層而以較快之速率蝕刻。因此,藉由改變蝕刻劑氣體的濃度,選擇性製程之淨結果係造成磊晶材料之沉積,以及有限(或是無)的多晶材料沉積。舉例來說,選擇性磊晶製程可造成含矽材料之磊晶層形成在單晶矽表面上,而無沉積在間隙物(spacer)上。Typical selective epitaxial processes include deposition reactions and etching reactions. In the deposition process, an epitaxial layer is formed on the surface of the single crystal, and a polycrystalline layer is deposited on at least the second layer (for example, an existing polycrystalline layer and/or an amorphous layer). The deposition reaction and the etching reaction can occur simultaneously, and have relatively different reaction rates for the epitaxial layer and the polycrystalline layer. However, the deposited polycrystalline layer is typically etched at a faster rate than the epitaxial layer. Thus, by varying the concentration of the etchant gas, the net result of the selective process is the deposition of epitaxial material and the deposition of limited (or no) polycrystalline material. For example, a selective epitaxial process can result in an epitaxial layer of germanium-containing material being formed on the surface of the single crystal germanium without depositing on the spacer.

含矽材料之選擇性磊晶沉積成為在高起之源極/汲極及源極/汲極延伸部特徵結構之形成過程中的有用技術,舉例來說,在含矽MOSFET(金氧半場效電晶體)元件之形成過程中。源極/汲極延伸部特徵結構之製造係藉由蝕刻矽表面以形成凹陷之源極/汲極特徵結構,並接著藉由以選擇性生長的磊晶層(例如矽鍺【SiGe】材料)來填充被蝕刻的表面。選擇性磊晶允許近乎完全的摻質活化並伴隨有原位摻雜,因而可省略後退火處理。因此,接面深度可藉由矽蝕刻及選擇性磊晶而精確地界定。另一方面,超淺源極/汲極接面必然地會造成串聯電組的增加。另外,在矽化物形成過程中的接面消耗(junction consumption)更會使串聯電組增加。為了補償接面消耗,高起的源極/汲極係磊晶地及選擇性地生長在接面上。一般來說,高起的源極/汲極層為未摻雜矽。Selective epitaxial deposition of germanium-containing materials is a useful technique in the formation of high-level source/drain and source/drain extension features, for example, in germanium-containing MOSFETs During the formation of the transistor) component. The source/drain extension feature is fabricated by etching the tantalum surface to form a recessed source/drain feature and then by selectively growing an epitaxial layer (eg, [SiGe] material) To fill the etched surface. Selective epitaxy allows near-complete dopant activation with in-situ doping, so post-annealing can be omitted. Therefore, the junction depth can be precisely defined by germanium etching and selective epitaxy. On the other hand, an ultra-shallow source/drain junction will inevitably result in an increase in series power. In addition, the junction consumption during the formation of the telluride will increase the series power. To compensate for junction wear, the raised source/drain is epitaxially and selectively grown on the junction. Generally, the raised source/drain layer is undoped germanium.

在含矽層之沉積過程中,沉積氣體可包括有元素摻質源(例如硼、砷、磷、鎵、或鋁),因而造成磊晶層之原位摻雜。摻質係提供沉積的含矽化合物具有多種傳導特性,例如電子元件所需之在受控及期望路徑中的方向性電子流。During the deposition of the germanium containing layer, the deposition gas may include an elemental dopant source (e.g., boron, arsenic, phosphorus, gallium, or aluminum), thereby causing in situ doping of the epitaxial layer. The dopant system provides a deposited ruthenium containing compound with a variety of conductive properties, such as directional electron flow in a controlled and desired path required for the electronic component.

目前的選擇性磊晶製程通常需要高反應溫度,例如約800℃、1000℃或更高,此種高溫通常為製造過程所不期望具有的,此乃因為熱預算之考量及可能發生在基材表面之未受控的氮化反應。另外,在較高製程溫度下,透過一般選擇性Si:C磊晶製程所併入之大多數的C原子會佔據Si 晶格之非取代(即,空隙)部位。藉由降低生長溫度,可達到較高部分的取代碳層級(例如:在550℃之生長溫度下可達到接近100%),然而,在此種低溫下之慢速生長速率對於元件應用係為不期望的,且此種選擇性處理在較低溫度下為不可能發生的。再者,摻雜有磷之Si:C薄膜存在有更低的生長速率。Current selective epitaxial processes typically require high reaction temperatures, such as about 800 ° C, 1000 ° C or higher, which are typically undesirable for the manufacturing process due to thermal budget considerations and may occur on the substrate. Uncontrolled nitridation of the surface. In addition, at higher process temperatures, most of the C atoms incorporated by the general selective Si:C epitaxial process will occupy Si. The unsubstituted (ie, void) portion of the crystal lattice. By lowering the growth temperature, a higher fraction of the substituted carbon layer can be achieved (for example, close to 100% at a growth temperature of 550 ° C), however, the slow growth rate at this low temperature is not for the component application. Desirably, such selective treatment is not possible at lower temperatures. Furthermore, the Si:C film doped with phosphorus has a lower growth rate.

因此,係需要一種製程,其可磊晶地沉積矽及含矽化合物,並伴隨有例如磷之摻質。再者,該製程應存在有快速之沉積速率、維持製程溫度(例如約800℃或更低,且較佳為700℃或更低),並具有高取代碳濃度。此種方法可用於電晶體元件之製造。Therefore, there is a need for a process for epitaxial deposition of germanium and germanium containing compounds accompanied by dopants such as phosphorus. Further, the process should have a rapid deposition rate, maintain process temperature (e.g., about 800 ° C or less, and preferably 700 ° C or less), and have a high substitution carbon concentration. This method can be used in the manufacture of transistor elements.

本發明之一實施例係關於形成及處理含有矽、碳及磷之磊晶層的方法。其他實施例係關於製造電晶體元件之方法,該電晶體元件包括含有矽、碳及磷之磊晶層。根據本發明之實施例,Si:C薄膜中的取代碳含量係增加。在一或多個實施例中,當沉積過程中的壓力升高至至少約100托(Torr)時,磊晶生長及蝕刻劑活性亦增加。One embodiment of the invention is directed to a method of forming and processing an epitaxial layer comprising tantalum, carbon, and phosphorus. Other embodiments are directed to methods of making a transistor element comprising an epitaxial layer comprising tantalum, carbon, and phosphorus. According to an embodiment of the invention, the substituted carbon content in the Si:C film is increased. In one or more embodiments, epitaxial growth and etchant activity also increase as the pressure during deposition increases to at least about 100 Torr.

根據本發明之一實施例,提供一種用於在基材上形成含有矽及碳之磊晶層的方法,該方法包括:將一基材放置在製程室中;以及將基材暴露於一矽源、碳源及磷源,並同時使製程室中的壓力維持在至少約100托,以在基材之至少一部分上形成摻雜有磷之Si:C磊晶薄膜。在部分實施 例中,製程室中的壓力係維持在至少約200托。在特定實施例中,壓力係維持在約300托。在一實施例中,製程室中的溫度係小於或等於約700℃。根據一或多個實施例,所形成之磊晶薄膜含有取代碳(substitutional carbon),而取代碳佔薄膜中所含之總碳的至少約40%(例如50%)。在部分實施例中,磷源包括膦(phosphine),且該磊晶薄膜中之磷濃度至少為約1020 原子/立方公分(atoms/cm3 )。According to an embodiment of the present invention, there is provided a method for forming an epitaxial layer containing tantalum and carbon on a substrate, the method comprising: placing a substrate in a process chamber; and exposing the substrate to a stack The source, carbon source, and phosphorus source, while maintaining the pressure in the process chamber at least about 100 Torr, form a Si:C epitaxial film doped with phosphorus on at least a portion of the substrate. In some embodiments, the pressure system in the process chamber is maintained at at least about 200 Torr. In a particular embodiment, the pressure system is maintained at about 300 Torr. In one embodiment, the temperature in the process chamber is less than or equal to about 700 °C. In accordance with one or more embodiments, the epitaxial film formed contains a substitutional carbon that is at least about 40% (e.g., 50%) of the total carbon contained in the film. In some embodiments, the phosphorus source comprises phosphine, and the concentration of phosphorus in the epitaxial film is at least about 10 20 atoms per cubic centimeter (atoms/cm 3 ).

根據部分實施例,基材包括一單晶表面及至少一第二表面,第二表面係選自非晶表面、多晶表面及其組成,其中磊晶層係形成在單晶表面上,非晶或多晶層則形成在第二表面上。在一或多個實施例中,可藉由將基材暴露於一蝕刻氣體而進一步處理基材。根據一或多個實施例,蝕刻氣體可包括HCl,且暴露於蝕刻氣體之步驟係發生在小於約700℃之溫度。According to some embodiments, the substrate comprises a single crystal surface and at least a second surface, the second surface being selected from the group consisting of an amorphous surface, a polycrystalline surface and a composition thereof, wherein the epitaxial layer is formed on the surface of the single crystal, amorphous Or a polycrystalline layer is formed on the second surface. In one or more embodiments, the substrate can be further processed by exposing the substrate to an etch gas. According to one or more embodiments, the etching gas may include HCl, and the step of exposing to the etching gas occurs at a temperature of less than about 700 °C.

在一或多個實施例中,係提供在一基材上形成含有矽及碳之磊晶層的方法,該方法包括:將一基材放置於製程室中,該基材包括一單晶表面及至少一第二表面,該第二表面選自非晶表面、多晶表面及其組成;以及將基材暴露於矽源、碳源、磷源及蝕刻源,並同時將製程室中的壓力維持在至少約100托(例如大於約200托),以在單晶表面上形成摻雜有磷之矽碳磊晶薄膜,而不生長在第二表面上。在一或多個實施例中,第二表面包括介電表面。In one or more embodiments, a method of forming an epitaxial layer comprising tantalum and carbon on a substrate, the method comprising: placing a substrate in a process chamber, the substrate comprising a single crystal surface And at least a second surface selected from the group consisting of an amorphous surface, a polycrystalline surface, and a composition thereof; and exposing the substrate to a source of germanium, a source of carbon, a source of phosphorus, and an etch source, and simultaneously applying pressure in the process chamber Maintaining at least about 100 Torr (e.g., greater than about 200 Torr) to form a phosphorous-doped ruthenium epitaxial film on the surface of the single crystal without growing on the second surface. In one or more embodiments, the second surface includes a dielectric surface.

本發明之製程可以作為電晶體製程之製造步驟。因此,本發明之實施例係關於製造電晶體之方法,該方法包 括:在一製程室中,於一基材上形成一閘極介電層;在該閘極介電層上形成一閘極電極;在基材上之閘極電極的相對側上形成源極/汲極區,並在源極/汲極區之間界定出一通道區;以及直接在源極/汲極區上沉積一磊晶薄膜,該磊晶薄膜含有矽及碳且摻雜有磷,而在上述步驟之同時係將製程室中的壓力維持在至少約100托。製程條件可如上所述而作調整。The process of the present invention can be used as a manufacturing step of a transistor process. Accordingly, embodiments of the present invention are directed to a method of fabricating a transistor, the method package The method comprises: forming a gate dielectric layer on a substrate in a process chamber; forming a gate electrode on the gate dielectric layer; forming a source on the opposite side of the gate electrode on the substrate / drain region, and define a channel region between the source/drain regions; and deposit an epitaxial film directly on the source/drain region, the epitaxial film containing germanium and carbon and doped with phosphorus At the same time as the above steps, the pressure in the process chamber is maintained at at least about 100 Torr. Process conditions can be adjusted as described above.

上方說明係廣泛地提出本發明之部分特徵結構及技術優點。熟悉此技術領域之人士應瞭解所揭露之特定實施例可容易地作為屬於本發明之範疇內之其他結構或製程之改良及設計之基礎。且熟悉此技術領域之人士亦應瞭解此種等效實施例並未偏離如後方申請專利範圍所界定之本發明的精神及範疇。The above description is a broad description of some of the features and technical advantages of the present invention. It will be appreciated by those skilled in the art that the specific embodiments disclosed may be readily utilized as a basis for the modification and design of other structures or processes within the scope of the invention. Those skilled in the art should also understand that such equivalent embodiments do not depart from the spirit and scope of the invention as defined by the appended claims.

本發明之實施例一般係提供一種形成磊晶層之方法,該磊晶層含有矽及碳且摻雜磷。其他實施例係關於製造電晶體之方法。根據一或多個實施例,在磊晶沉積之過程中,製程室之壓力至少為約100 Torr(托)。在特定實施例中,壓力可以為至少約200托或至少約300托。Embodiments of the present invention generally provide a method of forming an epitaxial layer comprising germanium and carbon and doped with phosphorus. Other embodiments are directed to methods of making a transistor. In accordance with one or more embodiments, the process chamber pressure is at least about 100 Torr during the epitaxial deposition process. In particular embodiments, the pressure can be at least about 200 Torr or at least about 300 Torr.

此處所使用之磊晶沉積係指基材上之單晶層沉積,故沉積層之結晶結構會符合基材之結晶結構。因此,磊晶層或薄膜係為一單晶層或薄膜,其結晶結構係符合基材之結晶結構。磊晶層係與塊體基材及多晶層區分開。As used herein, epitaxial deposition refers to the deposition of a single crystal layer on a substrate, so that the crystalline structure of the deposited layer conforms to the crystalline structure of the substrate. Therefore, the epitaxial layer or film is a single crystal layer or a film whose crystal structure conforms to the crystal structure of the substrate. The epitaxial layer is distinguished from the bulk substrate and the polycrystalline layer.

根據本發明之實施例,磊晶薄膜所沉積之基材通常為 矽基材,且其可以為圖案化(patterned)之基材。圖案化之基材係為基材表面內或基材表面上形成有電子特徵結構之基材。圖案化基材可含有單晶表面以及非單晶之至少一第二表面,例如多晶或非晶表面。單晶表面包括裸晶基材或是沉積之單晶層,其通常由例如矽、矽鍺或矽碳之材料製成。多晶或是非晶表面可包括介電材料,例如氧化物或是氮化物,特定的說是氧化矽或是氮化矽,以及非晶矽表面。According to an embodiment of the invention, the substrate deposited by the epitaxial film is usually The substrate is ruthenium and it can be a patterned substrate. The patterned substrate is a substrate having an electronic feature formed on or within the surface of the substrate. The patterned substrate can comprise a single crystal surface and at least a second surface that is non-single crystalline, such as a polycrystalline or amorphous surface. The single crystal surface includes a bare substrate or a deposited single crystal layer, which is typically made of a material such as tantalum, niobium or tantalum carbon. The polycrystalline or amorphous surface may comprise a dielectric material such as an oxide or a nitride, specifically germanium oxide or tantalum nitride, and an amorphous germanium surface.

矽碳層可利用磊晶製程而在一適當製程室中進行沉積,此製程室例如為購自加州聖克拉拉之應用材料公司(Applied Materials)的Epi RP或Centura。一般來說,製程室在整個磊晶製程中係維持在一致之溫度下,然而,部分步驟可以在不同的溫度下進行。製程室維持在溫度介於約250℃~約1000℃之間,例如介於約500℃~約900℃之間。進行磊晶製程之適當溫度係取決於用於沉積及/或蝕刻含碳及矽材料的特定前驅物,且可由熟悉此技藝之人士能判定。製程室通常維持在約0.1托~約600托,而壓力在沉積步驟過程中以及沉積步驟之間變動,但一般係維持恆定。The tantalum carbon layer can be deposited in a suitable process chamber using an epitaxial process, such as Epi RP or Centura, available from Applied Materials, Santa Clara, California. Generally, the process chamber is maintained at a uniform temperature throughout the epitaxial process, however, some of the steps can be performed at different temperatures. The process chamber is maintained at a temperature between about 250 ° C and about 1000 ° C, such as between about 500 ° C and about 900 ° C. The appropriate temperature for performing the epitaxial process depends on the particular precursor used to deposit and/or etch the carbon and germanium containing materials, and can be determined by those skilled in the art. The process chamber is typically maintained at from about 0.1 Torr to about 600 Torr, and the pressure varies between the deposition step and the deposition step, but is generally maintained constant.

在磊晶沉積製程中,基材係暴露於沉積氣體,以在單晶表面上形成磊晶層,同時在第二表面上形成多晶層。沉積製程之特定暴露時間的決定係與蝕刻處理之暴露時間,以及製程中所使用之特定前驅物及溫度相關。一般來說,基材係暴露於沉積氣體足夠長的時間,以形成磊晶層之最大厚度,並且形成多晶層之最小厚度,而使多晶層在沉積 期間可被輕易地蝕刻移除。In the epitaxial deposition process, the substrate is exposed to a deposition gas to form an epitaxial layer on the surface of the single crystal while forming a polycrystalline layer on the second surface. The specific exposure time of the deposition process is determined by the exposure time of the etch process, as well as the particular precursor and temperature used in the process. Generally, the substrate is exposed to the deposition gas for a sufficient period of time to form a maximum thickness of the epitaxial layer and to form a minimum thickness of the polycrystalline layer, while the polycrystalline layer is deposited. The period can be easily removed by etching.

沉積氣體含有至少一矽源、一載氣以及一碳源。在一選擇性實施例中,沉積氣體可包括至少一蝕刻劑,例如氯化氫或氯。The deposition gas contains at least one helium source, one carrier gas, and one carbon source. In an alternative embodiment, the deposition gas can include at least one etchant, such as hydrogen chloride or chlorine.

矽源通常提供至製程室之速率為約5 sccm~約500 sccm,舉例來說,約10 sccm~約300 sccm,且特定地為約50 sccm~約200 sccm,更特定地為100 sccm。可用於沉積氣體中以沉積含矽及碳之化合物的矽源包括但不限於為矽烷、鹵化矽烷及有機矽烷。矽烷包括矽烷(SiH4 )以及具有實驗式為Six H(2x+2) 之較高層級的矽烷,例如二矽烷(Si2 H6 )、三矽烷(Si3 H8 )以及四矽烷(Si4 H10 )等。鹵化矽烷包括具有實驗式為X’y Six H(2x+2-y) 之化合物,其中X’=F、Cl、Br或I,例如:六氯二矽烷(Si2 Cl6 )、四氯矽烷(SiCl4 )、二氯矽烷(Cl2 SiH2 )以及三氯矽烷(Cl3 SiH)。有機矽烷包括具有實驗式為Ry Six H(2x+2-y) 之化合物,其中R=甲基、乙基、丙基或丁基,例如甲基矽烷((CH3 )SiH3 )、二甲基矽烷((CH3 )2 SiH2 )、乙基矽烷((CH3 CH2 )SiH3 )、甲基二矽烷((CH3 )Si2 H5 )、二甲基二矽烷((CH3 )2 Si2 H4 )及六甲基二矽烷((CH3 )6 Si2 )。The source of germanium is typically supplied to the process chamber at a rate of from about 5 sccm to about 500 sccm, for example, from about 10 sccm to about 300 sccm, and specifically from about 50 sccm to about 200 sccm, more specifically 100 sccm. Sources of ruthenium that can be used in deposition gases to deposit compounds containing ruthenium and carbon include, but are not limited to, decane, decane, and organodecane. The decane includes decane (SiH 4 ) and a higher level of decane having the experimental formula of Si x H (2x+2) , such as dioxane (Si 2 H 6 ), trioxane (Si 3 H 8 ), and tetraoxane (Si). 4 H 10 ) and so on. Halogenated halogen includes a compound of the formula X' y Si x H (2x+2-y) , wherein X'=F, Cl, Br or I, for example: hexachlorodioxane (Si 2 Cl 6 ), tetrachloro Oxane (SiCl 4 ), dichlorodecane (Cl 2 SiH 2 ), and trichlorodecane (Cl 3 SiH). The organodecane includes a compound having the formula R y Si x H (2x+2-y) , wherein R = methyl, ethyl, propyl or butyl, such as methyl decane ((CH 3 )SiH 3 ), Dimethyldecane ((CH 3 ) 2 SiH 2 ), ethyl decane ((CH 3 CH 2 )SiH 3 ), methyldioxane ((CH 3 )Si 2 H 5 ), dimethyldioxane (( CH 3 ) 2 Si 2 H 4 ) and hexamethyldioxane ((CH 3 ) 6 Si 2 ).

矽源通常伴隨載氣而輸送至製程室中。載氣之流速介於約1 slm(標準狀態下單位時間之體積流率)~約100 slm,例如約5 slm~約75 slm,更特定地為約10 slm~約50 slm,例如約25 slm。載氣可包括氮氣(N2 )、氫氣(H2 )、氬氣、氦氣及其組合。惰性載氣為較佳的,且包括氮氣、 氬氣、氦氣及其組合。載氣之選擇係基於磊晶製程中所使用之前驅物及/或製程溫度。通常在各個步驟中係使用相同之載氣。然而,部分實施例可以在特定步驟中使用不同之載氣。The helium source is typically delivered to the process chamber with the carrier gas. The flow rate of the carrier gas is between about 1 slm (volume flow rate per unit time under standard conditions) ~ about 100 slm, for example about 5 slm to about 75 slm, more specifically about 10 slm to about 50 slm, for example about 25 slm . The carrier gas may include nitrogen (N 2 ), hydrogen (H 2 ), argon, helium, and combinations thereof. An inert carrier gas is preferred and includes nitrogen, argon, helium, and combinations thereof. The choice of carrier gas is based on the precursor and/or process temperatures used in the epitaxial process. The same carrier gas is typically used in each step. However, some embodiments may use different carrier gases in a particular step.

步驟中提供至製程室之碳源係伴隨矽源及載氣以形成含矽及碳之化合物,例如矽碳物質,碳源提供至製程室之速率通常介於約0.1 sccm~約20 sccm,例如約0.5 sccm~約10 sccm,且更特定係介於約1 sccm~約5 sccm,例如約2 sccm。可用於沉積含矽及碳之化合物的碳源包括但不限於為有機矽烷、乙基、丙基及丁基之烴、烯烴、炔烴。此種碳源包括甲基矽烷(CH3 SiH3 )、二甲基矽烷((CH3 )2 SiH2 )、三甲基矽烷((CH3 )3 SiH)、乙基矽烷(CH3 CH2 SiH3 )、甲烷(CH4 )、乙烯(C2 H4 )、乙炔(C2 H2 )、丙烷(C3 H8 )、丙烯(C3 H6 )等。磊晶層之碳濃度係介於約200 ppm~約5原子百分比(atomic %),舉例來說,介於約1 atomic%~約3 atomic%,更特定地為至少2 atomic%,或至少為約1.5 atomic%。在一實施例中,磊晶層中的碳濃度為漸變的(graded),較佳的,磊晶層之較低部分相對於較高部分而具有較高之碳濃度。可選擇地,鍺源及碳源可以伴隨矽源及載氣而一同加入製程室中,以形成含矽及碳之化合物,例如矽鍺碳物質。The carbon source provided to the process chamber in the step is accompanied by a helium source and a carrier gas to form a compound containing ruthenium and carbon, such as a ruthenium carbon material, and the rate at which the carbon source is supplied to the process chamber is generally from about 0.1 sccm to about 20 sccm, for example, From about 0.5 sccm to about 10 sccm, and more specifically from about 1 sccm to about 5 sccm, such as about 2 sccm. Carbon sources useful for depositing compounds containing ruthenium and carbon include, but are not limited to, hydrocarbons, olefins, alkynes that are organodecane, ethyl, propyl, and butyl. Such carbon sources include methyl decane (CH 3 SiH 3 ), dimethyl decane ((CH 3 ) 2 SiH 2 ), trimethyl decane ((CH 3 ) 3 SiH), ethyl decane (CH 3 CH 2 ) SiH 3 ), methane (CH 4 ), ethylene (C 2 H 4 ), acetylene (C 2 H 2 ), propane (C 3 H 8 ), propylene (C 3 H 6 ), and the like. The epitaxial layer has a carbon concentration of from about 200 ppm to about 5 atomic percent, for example, from about 1 atomic % to about 3 atomic %, more specifically at least 2 atomic %, or at least About 1.5 atomic%. In one embodiment, the concentration of carbon in the epitaxial layer is graded. Preferably, the lower portion of the epitaxial layer has a higher carbon concentration relative to the upper portion. Alternatively, the helium source and the carbon source may be added to the process chamber along with the helium source and the carrier gas to form a compound containing ruthenium and carbon, such as ruthenium carbon.

沉積製程結束。在一實例中,可以利用淨化氣體(purge gas)或是載氣來沖洗製程室,及/或利用真空幫浦而將製程室排空。淨氣及/或排氣處理係將過多的製程氣體、反應 副產物及其他污染物移除。在另一實例中,一旦沉積製程結束,蝕刻處理則接著進行,而不需對製程室進行淨氣及/或排氣動作。The deposition process is over. In one example, the process chamber can be flushed with a purge gas or a carrier gas, and/or the process chamber can be evacuated using a vacuum pump. Clean gas and / or exhaust treatment will be excessive process gas, reaction By-products and other contaminants are removed. In another example, once the deposition process is complete, the etching process is then performed without the need to purge and/or vent the process chamber.

蝕刻Etching

可進行一選擇性蝕刻處理,蝕刻處理係移除基材表面上之部分磊晶層。蝕刻處理移除磊晶或單晶物質以及非晶或多晶物質兩者。沉積在基材表面上之多晶層(若有的話)相較於磊晶層而以較快之速度移除。蝕刻處理之持續時間與沉積製程之持續時間係達成平衡,藉以獲得磊晶層選擇性地形成在基材上之期望區域的淨沉積結果。因此,沉積製程及蝕刻處理之淨結果為形成選擇性地及磊晶地生長之含矽及碳之物質,並同時使得多晶物質(若有的話)之生長最少化。A selective etching process can be performed which removes portions of the epitaxial layer on the surface of the substrate. The etching process removes both epitaxial or single crystalline materials as well as amorphous or polycrystalline materials. The polycrystalline layer, if any, deposited on the surface of the substrate is removed at a faster rate than the epitaxial layer. The duration of the etching process is balanced with the duration of the deposition process to obtain a net deposition result of the desired region of the epitaxial layer selectively formed on the substrate. Thus, the net result of the deposition process and the etch process is the formation of germanium and carbon containing species that selectively and epitaxially grow while minimizing the growth of polycrystalline materials, if any.

在蝕刻處理期間,基材暴露於蝕刻氣體之時間為約10秒~約90秒,例如約20秒~60秒,且更特定地為約30秒~約45秒。蝕刻氣體包括至少一蝕刻劑及載氣。蝕刻劑通常供應至製程室之速度為約10 sccm~約700 sccm,例如介於約50 sccm~約500 sccm。蝕刻氣體中所使用之蝕刻劑可包括氯(Cl2 )、氯化氫(HCl)、三氯化硼(BCl3 )、氯甲烷(CH3 Cl)、四氯化碳(CCl4 )、氟化氯(ClF3 )及其組合。較佳的,係使用氯或氯化氫作為蝕刻劑。The time during which the substrate is exposed to the etching gas during the etching process is from about 10 seconds to about 90 seconds, such as from about 20 seconds to 60 seconds, and more specifically from about 30 seconds to about 45 seconds. The etching gas includes at least one etchant and a carrier gas. The etchant is typically supplied to the process chamber at a rate of from about 10 sccm to about 700 sccm, such as from about 50 sccm to about 500 sccm. The etchant used in the etching gas may include chlorine (Cl 2 ), hydrogen chloride (HCl), boron trichloride (BCl 3 ), methyl chloride (CH 3 Cl), carbon tetrachloride (CCl 4 ), and chlorine fluoride. (ClF 3 ) and combinations thereof. Preferably, chlorine or hydrogen chloride is used as an etchant.

蝕刻劑通常與載氣一同提供至製程室。載氣的流速介於約1 slm~約100 slm,例如約5 slm~約75 slm,更特 定地為約10 slm~約50 slm,例如為約25 slm。載氣通常包括氮氣(N2 )、氫氣(H2 )、氬氣、氦氣及其組合。在部分實施例中,較佳為惰性載氣,包括氮氣、氬氣、氦氣及其組合。載氣係根據特定之前驅物及/或磊晶製程中所使用之溫度而選擇。The etchant is typically supplied to the process chamber along with the carrier gas. The flow rate of the carrier gas is from about 1 slm to about 100 slm, for example from about 5 slm to about 75 slm, more specifically from about 10 slm to about 50 slm, for example about 25 slm. The carrier gas typically includes nitrogen (N 2 ), hydrogen (H 2 ), argon, helium, and combinations thereof. In some embodiments, an inert carrier gas is preferred, including nitrogen, argon, helium, and combinations thereof. The carrier gas system is selected based on the temperature used in the particular precursor and/or epitaxial process.

蝕刻處理結束。在一實例中,可以利用淨化氣體或是載氣來沖洗製程室,及/或利用真空幫浦而將製程室排空。淨氣及/或排氣處理係將過多的蝕刻氣體、反應副產物及其他污染物移除。在另一實例中,一旦蝕刻處理結束,則接著量測磊晶層之厚度,而不需對製程室進行淨氣及/或排氣動作。The etching process is finished. In one example, the process chamber can be flushed with purge gas or carrier gas, and/or the process chamber can be evacuated using a vacuum pump. The scrubbing and/or exhaust treatment removes excess etching gases, reaction byproducts, and other contaminants. In another example, once the etching process is complete, the thickness of the epitaxial layer is then measured without the need to purge and/or vent the process chamber.

可測定磊晶層及多晶層的厚度。一旦達到預定厚度,則接著停止磊晶製程。然而,一旦未達到預定厚度,則接著重複循環進行沉積製程直到達到期望厚度。所生長的磊晶層厚度係介於約10Å~約2000 Å,例如約100 Å~約1500 Å,更特定地為約400 Å~約1200 Å,例如約800 Å。所沉積之多晶層(若有的話)厚度係介於一原子層~約500 Å之間。磊晶之含矽及碳層或是多晶之含矽及碳層的期望或預定厚度對於特定之製程係為特有的。在一實例中,磊晶層可達到預定厚度且同時多晶層為太厚。The thickness of the epitaxial layer and the polycrystalline layer can be measured. Once the predetermined thickness is reached, the epitaxial process is then stopped. However, once the predetermined thickness is not reached, the cycle is followed by a deposition process until the desired thickness is reached. The thickness of the epitaxial layer grown is from about 10 Å to about 2000 Å, such as from about 100 Å to about 1500 Å, more specifically from about 400 Å to about 1200 Å, for example about 800 Å. The deposited polycrystalline layer, if any, has a thickness ranging from one atomic layer to about 500 Å. The desired or predetermined thickness of the epitaxial germanium-containing and carbon layer or polycrystalline germanium-containing and carbon-containing layers is unique to a particular process system. In one example, the epitaxial layer can reach a predetermined thickness while the polycrystalline layer is too thick.

摻質暴露Doping exposure

在磊晶沉積期間,磊晶層係暴露於摻質。一般的摻質包括至少一摻質化合物,以提供元素摻質源,例如:硼、 砷、磷、鎵或鋁。在本發明之特定實施例中,含矽及碳之化合物為摻雜n型(doped n-type),例如摻雜有濃度介於約1015 atoms/cm3 (原子/立方公分)~約1021 atoms/cm3 之磷及/或砷。During epitaxial deposition, the epitaxial layer is exposed to the dopant. Typical dopants include at least one dopant compound to provide an elemental dopant source such as boron, arsenic, phosphorus, gallium or aluminum. In a particular embodiment of the invention, the ruthenium and carbon containing compound is doped n-type, for example doped at a concentration of between about 10 15 atoms/cm 3 (atoms per cubic centimeter) to about 10 21 atoms/cm 3 of phosphorus and/or arsenic.

通常將摻質源提供至製程室中。摻質源可包括胂(AsH3 )、膦(PH3 )以及烷基膦,例如具有實驗式Rx PH(3-x) ,其中R=甲基、乙基、丙基或丁基,且x=1、2或3。烷基膦包括三甲基膦((CH3 )3 P)、二甲基膦((CH3 )2 PH)、三乙基膦((CH3 CH2 )3 P)及二乙基膦((CH3 CH2 )2 PH)。The dopant source is typically supplied to the process chamber. Sources of dopants may include hydrazine (AsH 3 ), phosphine (PH 3 ), and alkyl phosphines, for example, having the experimental formula R x PH (3-x) wherein R = methyl, ethyl, propyl or butyl, and x=1, 2 or 3. Alkylphosphines include trimethylphosphine ((CH 3 ) 3 P), dimethylphosphine ((CH 3 ) 2 PH), triethylphosphine ((CH 3 CH 2 ) 3 P), and diethyl phosphine ( (CH 3 CH 2 ) 2 PH).

本發明之特定實施例關於在超過100托(Torr)之高壓下形成原位磷摻雜之選擇性Si:C磊晶層。超過100托之高壓會造成生長速率增加以及取代碳濃度增加,如「第1圖」所示。實驗進行之溫度及矽與碳前驅物與載氣之流速係維持恆定。在不同之實驗中,壓力則改變為6托、100托及300托,結果係示於「第1圖」中。如「第1圖」所示,較高的壓力係造成較高之取代碳濃度。更特定的說,在其他製程條件保持恆定之下,於6托之壓力下所產生之樣品,其取代碳為0.8%;於100托之壓力下所產生之樣品,其取代碳為1.1%;於300托之壓力下所產生之樣品,其取代碳為1.4%。A particular embodiment of the invention relates to the formation of an in situ phosphorus doped selective Si:C epitaxial layer at a high pressure in excess of 100 Torr. A high pressure of more than 100 Torr causes an increase in growth rate and an increase in the carbon concentration of substitution, as shown in Figure 1. The temperature at which the experiment was carried out and the flow rate of the ruthenium and carbon precursor and the carrier gas were maintained constant. In different experiments, the pressure was changed to 6 Torr, 100 Torr and 300 Torr. The results are shown in Figure 1. As shown in Figure 1, a higher pressure results in a higher substituted carbon concentration. More specifically, the sample produced under a pressure of 6 Torr has a carbon substitution of 0.8% while the other process conditions are kept constant; the sample produced under a pressure of 100 Torr has a substituted carbon of 1.1%; The sample produced under a pressure of 300 Torr had a substituted carbon of 1.4%.

根據本發明之一實施例,在選擇性Si:C磊晶之適當製程實例中係造成磷濃度大於約2×1020 atoms/cm3 、碳濃度為約1.3 atomic%,以及取代層級為約0.6 atomic%。製程 室可維持在約700℃之溫度、約300托之壓力、10 slm之氫氣載氣流速、200 sccm之二氯矽烷源之氣體流速以及30 sccm之HCl流速之下。甲基矽烷(稀釋於氫氣中為1%)之流速為240 sccm,膦(稀釋於氫氣中為1%)之流速為240 sccm。所有製程氣體同時流入製程室中,且摻雜有磷的含碳之矽層係形成於基材上。觀察到於較高壓力下所產生之樣品具有較高之HCl蝕刻活性。因此,根據本發明之實施例,在HCl活性較弱之溫度下(例如小於約700℃)所進行之蝕刻可以採用較高壓製程。在產生磷摻雜之實例中,二次離子質譜儀(SIMS)數據顯示超過100托之壓力會造成磷含量大於2×1020 atoms/cm3According to an embodiment of the invention, in a suitable process example of selective Si:C epitaxy, the phosphorus concentration is greater than about 2 x 10 20 atoms/cm 3 , the carbon concentration is about 1.3 atomic %, and the substitution level is about 0.6. Atomic%. The process chamber can be maintained at a temperature of about 700 ° C, a pressure of about 300 Torr, a hydrogen carrier gas flow rate of 10 slm, a gas flow rate of a 200 sccm dichlorodecane source, and a HCl flow rate of 30 sccm. The flow rate of methyl decane (1% diluted in hydrogen) was 240 sccm, and the flow rate of phosphine (1% diluted in hydrogen) was 240 sccm. All of the process gas flows into the process chamber at the same time, and a carbon-containing ruthenium layer doped with phosphorus is formed on the substrate. Samples produced at higher pressures were observed to have higher HCl etch activity. Thus, in accordance with embodiments of the present invention, etching performed at a temperature at which HCl activity is weak (e.g., less than about 700 ° C) may employ a higher press. In the example of generating phosphorus doping, secondary ion mass spectrometer (SIMS) data shows that a pressure in excess of 100 Torr results in a phosphorus content greater than 2 x 10 20 atoms/cm 3 .

上述類型之製程可用於選擇性沉積製程中,其中沉積及蝕刻氣體係同時流入腔室中,而造成基材之單晶表面上具有摻雜磷之Si:C磊晶薄膜,但在介電表面上並無任何生長情形。在較高壓力下之較高HCl活性係允許蝕刻於較低溫下進行,例如低於約700℃。Processes of the above type can be used in a selective deposition process in which a deposition and etching gas system simultaneously flows into the chamber, resulting in a Si-C epitaxial film doped with phosphorus on the single crystal surface of the substrate, but on a dielectric surface. There is no growth on the top. The higher HCl activity at higher pressures allows the etching to proceed at lower temperatures, such as below about 700 °C.

根據本發明之實施例的磊晶薄膜可更進行退火處理,例如藉由快速熱製程,如:快速熱退火、快速熱處理、雷射退火、微秒退火及/或尖峰退火或閃光退火或其組合。退火溫度取決於所使用之製程。The epitaxial film according to an embodiment of the present invention may be further annealed, for example, by a rapid thermal process such as rapid thermal annealing, rapid thermal processing, laser annealing, microsecond annealing, and/or spike annealing or flash annealing or a combination thereof. . The annealing temperature depends on the process used.

本發明之一或多個實施例提供特別可用於形成互補金氧半導體(CMOS)積體電路元件之方法,且將於下描述之。其他元件及應用亦屬於本發明之範圍。「第2圖」繪示一般CMOS元件之FET對的部分剖面視圖。元件100包括 在形成井(well)之後的半導體基材,該些井提供NMOS元件及PMOS元件之源極/汲極區、閘極介電層及閘極電極。元件100可以藉由習知之半導體製程來形成,例如:生長單晶矽並藉由溝渠蝕刻而形成淺溝渠隔離結構,以及在溝渠開口中生長或沉積介電質。形成該些結構之詳細步驟為此技術領域所熟知者,故在此處不再贅述。One or more embodiments of the present invention provide a method that is particularly useful for forming complementary metal oxide semiconductor (CMOS) integrated circuit components and will be described below. Other elements and applications are also within the scope of the invention. Figure 2 shows a partial cross-sectional view of a FET pair of a typical CMOS device. Element 100 includes The semiconductor substrate after forming a well provides a source/drain region, a gate dielectric layer, and a gate electrode of the NMOS device and the PMOS device. Element 100 can be formed by conventional semiconductor processes, such as growing a single crystal germanium and forming a shallow trench isolation structure by trench etching, and growing or depositing a dielectric in the trench opening. The detailed steps for forming such structures are well known to those skilled in the art and will not be described again herein.

元件100包括:摻雜有p型材料之半導體基材155(例如矽基材)、基材155上之p型磊晶矽層165、定義於磊晶層165中的p型井區120及n型井區150、定義於p型井區120中的n型電晶體(NMOS FET)110,以及定義於n型井區150中的p型電晶體(NMOS FET)140。第一隔離區158係電性隔離n型電晶體110及p型電晶體140,第二隔離區160係將電晶體110、140與基材155上之其他半導體元件電性隔離。Element 100 includes a semiconductor substrate 155 (eg, a germanium substrate) doped with a p-type material, a p-type epitaxial layer 165 on substrate 155, p-well regions 120 and n defined in epitaxial layer 165 A well region 150, an n-type transistor (NMOS FET) 110 defined in the p-type well region 120, and a p-type transistor (NMOS FET) 140 defined in the n-type well region 150. The first isolation region 158 electrically isolates the n-type transistor 110 and the p-type transistor 140. The second isolation region 160 electrically isolates the transistors 110, 140 from other semiconductor components on the substrate 155.

根據本發明之一或多個實施例,NMOS電晶體110包括閘極電極122、第一源極區114及汲極區116。NMOS閘極電極122的厚度係為可變的,並可基於元件效能之考量而做調整。NMOS閘極電極122的功函數係相應於N型元件之功函數。源極及汲極區係為位於閘極電極122之相對側的n型區域。通道區118係位於源極區114與汲極區116之間。閘極介電層112分隔通道區118與閘極電極122。用於形成NMOS閘極電極122與介電層之製程係為此技術領域熟知者,故在此不再贅述。In accordance with one or more embodiments of the present invention, NMOS transistor 110 includes a gate electrode 122, a first source region 114, and a drain region 116. The thickness of the NMOS gate electrode 122 is variable and can be adjusted based on component performance considerations. The work function of the NMOS gate electrode 122 corresponds to the work function of the N-type element. The source and drain regions are n-type regions on opposite sides of the gate electrode 122. Channel region 118 is located between source region 114 and drain region 116. The gate dielectric layer 112 separates the channel region 118 from the gate electrode 122. The process for forming the NMOS gate electrode 122 and the dielectric layer is well known in the art and will not be described herein.

根據一或多個實施例,PMOS電晶體140包括閘極電 極152、源極區144及汲極區146。PMOS閘極電極152的厚度係為可變的,並可基於元件效能之考量而做調整。PMOS閘極電極152的功函數係相應於N型元件之功函數。源極及汲極區係為位於閘極電極152之相對側的p型區域。通道區148係位於源極區144與汲極區146之間。閘極介電層142分隔通道區148與閘極電極152。介電層142係使閘極電極152與通道區148絕緣。應了解「第2圖」所示以及上方所描述之之電晶體110、140結構係僅作為示範性,然而材料及層中的多種變化例亦屬於本發明之範疇。According to one or more embodiments, the PMOS transistor 140 includes a gate electrode The pole 152, the source region 144 and the drain region 146. The thickness of the PMOS gate electrode 152 is variable and can be adjusted based on component performance considerations. The work function of the PMOS gate electrode 152 corresponds to the work function of the N-type element. The source and drain regions are p-type regions on opposite sides of the gate electrode 152. Channel region 148 is located between source region 144 and drain region 146. Gate dielectric layer 142 separates channel region 148 from gate electrode 152. Dielectric layer 142 insulates gate electrode 152 from channel region 148. It should be understood that the structures of the transistors 110, 140 shown in "Fig. 2" and described above are merely exemplary, but various variations in materials and layers are also within the scope of the present invention.

現請參照「第3圖」,其係顯示「第2圖」之NMOS元件110在間隙物、源極/汲極區上之層(例如矽化物層)形成以及蝕刻終止層形成之後的額外細節。應了解「第3圖」所示之PMOS元件可含有相似之間隙物及層,其尺寸及/或組成可經修改以影響NMOS元件之通道中所誘導的應力,如下所描述者。然而,為了說明之目的,僅示出並詳細描述NMOS元件。Referring now to "Fig. 3", it is an additional detail showing the formation of the NMOS device 110 of the "Fig. 2" on the spacer, the source/drain region (e.g., a germanide layer), and the formation of an etch stop layer. . It should be understood that the PMOS device shown in FIG. 3 may contain similar spacers and layers whose size and/or composition may be modified to affect the induced stress in the channel of the NMOS device, as described below. However, for purposes of illustration, only NMOS elements are shown and described in detail.

「第3圖」係顯示間隙物175可以由併入閘極119周圍之適當介電材料形成。偏移間隙物177亦可設置於各個間隙物175之周圍。用於形成間隙物175、177之形狀、尺寸及厚度的製程係為此技術領域所熟知者,故在此處不再贅述。金屬矽化物層179可以形成於源極區114與汲極區116之上。金屬矽化物層179可以藉由適當之製程(例如濺鍍或物理氣相沉積【PVD】)並由適當之金屬形成,例如: 鎳、鈦或鈷。矽化物層179可擴散至部分之下方表面。汲極區116之高度係由箭頭181顯示,而其係為基材表面180至矽化物層179之頂端的距離。源極與汲極區的面183係顯示為具角度的表面。如同熟悉此技術領域之人士所能了解者,上述之示範性元件可以經過修改而包括具有Si:C磊晶層的源極/汲極或源極/汲極延伸部,而其更可根據本發明之方法而進一步修改之。"Picture 3" shows that the spacer 175 can be formed of a suitable dielectric material that is incorporated around the gate 119. Offset spacers 177 may also be disposed around each of the spacers 175. The process for forming the shape, size and thickness of the spacers 175, 177 is well known to those skilled in the art and will not be described again herein. A metal telluride layer 179 can be formed over the source region 114 and the drain region 116. The metal telluride layer 179 can be formed by a suitable process (eg, sputtering or physical vapor deposition [PVD]) and from a suitable metal, such as: Nickel, titanium or cobalt. The telluride layer 179 can diffuse to a portion of the lower surface. The height of the drain region 116 is indicated by arrow 181, which is the distance from the substrate surface 180 to the top end of the telluride layer 179. The faces 183 of the source and drain regions are shown as angled surfaces. As will be appreciated by those skilled in the art, the exemplary components described above can be modified to include source/drain or source/drain extensions having a Si:C epitaxial layer, which can be further Further modifications are made by the method of the invention.

說明書中任何參照「一實施例」、「部分實施例」、「一或多個實施例」之詞係指與該實施例關聯描述之一特定特徵結構、構造、材料或是特徵係包括在本發明之至少一實施例中。因此,在說明書中出現的此種用詞並非一定皆指向相同的實施例。再者,特定之特徵結構、構造、材料或是特徵可以利用適當方式而組合在一或多個實施例中。上述方法之描述順序不應作為限制之用,上述方法可利用順序外之操作,或是經過省略或是附加。Any reference to "an embodiment," "partial embodiment," or "one or more embodiments" in the specification means that a particular feature, structure, material, or feature is described in connection with the embodiment. In at least one embodiment of the invention. Therefore, such phrases as used in the specification are not necessarily referring to the embodiments. Furthermore, the particular features, structures, materials, or characteristics may be combined in one or more embodiments in a suitable manner. The order in which the above methods are described is not intended to be limiting, and the above methods may be performed in an out-of-sequence operation or omitted or added.

惟本發明雖以較佳實施例說明如上,然其並非用以限定本發明,任何熟習此技術人員,在不脫離本發明的精神和範圍內所作的更動與潤飾,仍應屬本發明的技術範疇。However, the present invention has been described above by way of a preferred embodiment, and is not intended to limit the present invention. Any modification and refinement made by those skilled in the art without departing from the spirit and scope of the present invention should still belong to the technology of the present invention. category.

100‧‧‧元件100‧‧‧ components

110,140‧‧‧電晶體110,140‧‧‧Optoelectronics

112,142‧‧‧介電層112, 142‧‧ dielectric layer

114,144‧‧‧源極區114,144‧‧‧ source area

116,146‧‧‧汲極區116, 146‧‧ ‧ bungee area

118,148‧‧‧通道區118,148‧‧‧Channel area

119‧‧‧閘極119‧‧‧ gate

120,150‧‧‧井區120,150‧‧‧ Well Area

122,152‧‧‧閘極電極122,152‧‧‧gate electrode

155‧‧‧基材155‧‧‧Substrate

158,160‧‧‧隔離區158,160‧‧‧Isolated area

165‧‧‧矽層/磊晶層165‧‧‧矽/Eplayer

175‧‧‧間隙物175‧‧ ‧ spacers

177‧‧‧間隙物177‧‧‧ spacers

179‧‧‧矽化物層179‧‧‧ Telluride layer

180‧‧‧表面180‧‧‧ surface

181‧‧‧箭頭181‧‧‧ arrow

183‧‧‧面183‧‧‧ face

為讓本發明之上述特徵更明顯易懂,可配合參考實施例說明,其部分乃繪示如附圖式。須注意的是,雖然所附圖式揭露本發明特定實施例,但其並非用以限定本發明之精神與範圍,任何熟習此技藝者,當可作各種之更動與潤 飾而得等效實施例。In order to make the above-mentioned features of the present invention more obvious and understandable, it can be explained with reference to the reference embodiment, and a part thereof is illustrated as a drawing. It is to be understood that the specific embodiments of the present invention are not intended to limit the spirit and scope of the invention. The equivalent embodiment is decorated.

第1圖,繪示在高壓下之含有碳及矽之磊晶層的高解析度X射線繞射光譜(HR-XRD spectra);第2圖,繪示根據本發明之一實施例的場效電晶體對之剖面視圖;以及第3圖,繪示第2圖之PMOS場效電晶體的剖面視圖,其在元件上形成有額外層。1 is a high-resolution X-ray diffraction spectrum (HR-XRD spectra) of an epitaxial layer containing carbon and germanium under high pressure; and FIG. 2 is a diagram showing field effect according to an embodiment of the present invention. A cross-sectional view of the transistor pair; and FIG. 3, a cross-sectional view of the PMOS field effect transistor of FIG. 2, with additional layers formed on the component.

Claims (11)

一種在一基材上形成一含有矽及碳之磊晶層的方法,包括將一基材置放在一製程室中,其中該基材包括一單晶表面及至少一第二表面,該第二表面係選自一非晶表面、一多晶表面及上述表面之組合,其中一磊晶層係形成於該單晶表面上,且一多晶層係形成於該第二表面上;將該基材暴露於一矽源、一碳源及一磷源,並同時將該製程室中的壓力維持在約200托(Torr)以上,以在該基材之至少一部分上形成一摻雜有磷之矽碳磊晶薄膜(Si:C epitaxial film);以及將該基材暴露於包括氯化氫(HCl)之一蝕刻氣體以進一步處理該基材,其中該製程室中的溫度係小於或等於約700℃。 A method of forming an epitaxial layer containing tantalum and carbon on a substrate, comprising placing a substrate in a process chamber, wherein the substrate comprises a single crystal surface and at least a second surface, the first The two surface is selected from the group consisting of an amorphous surface, a polycrystalline surface, and a combination of the above surfaces, wherein an epitaxial layer is formed on the surface of the single crystal, and a polycrystalline layer is formed on the second surface; The substrate is exposed to a source of germanium, a source of carbon and a source of phosphorus, and at the same time maintaining a pressure in the process chamber above about 200 Torr to form a doped phosphorus on at least a portion of the substrate a silicon epitaxial film (Si: C epitaxial film); and exposing the substrate to an etching gas including hydrogen chloride (HCl) to further process the substrate, wherein the temperature in the process chamber is less than or equal to about 700 °C. 如申請專利範圍第1項所述之方法,其中該製程室中的壓力維持在至少約300托。 The method of claim 1, wherein the pressure in the process chamber is maintained at at least about 300 Torr. 如申請專利範圍第1項所述之方法,其中所形成之該磊晶薄膜含有取代碳(substitutional carbon),而取代碳至少為該磊晶薄膜中之總含碳量的約50%。 The method of claim 1, wherein the epitaxial film is formed to contain a substitutional carbon, and the substituted carbon is at least about 50% of the total carbon content in the epitaxial film. 如申請專利範圍第1項所述之方法,其中該磷源包括膦 (phosphine),且該磊晶薄膜中之磷濃度至少為約1020 原子/立方公分(atoms/cm3 )。The method of claim 1, wherein the phosphorus source comprises phosphine, and the concentration of phosphorus in the epitaxial film is at least about 10 20 atoms/cm 3 . 一種在一基材上形成一含有矽及碳之磊晶層的方法,包括:將一基材置放在一製程室中,該基材包括一單晶表面及至少一第二表面,該第二表面係選自一非晶表面、一多晶表面及上述表面之組合;將該基材暴露於一矽源、一碳源、一磷源及包括氯化氫(HCl)之一蝕刻源,並同時將該製程室中的壓力維持在約200托(Torr)以上而溫度維持在約700℃以下,以在該單晶表面上形成一摻雜有磷之矽碳磊晶薄膜,而不生長在該第二表面上。 A method of forming an epitaxial layer containing tantalum and carbon on a substrate, comprising: placing a substrate in a process chamber, the substrate comprising a single crystal surface and at least a second surface, the first The surface is selected from an amorphous surface, a polycrystalline surface, and a combination of the above surfaces; the substrate is exposed to a source of germanium, a source of carbon, a source of phosphorus, and an etching source including hydrogen chloride (HCl), and simultaneously Maintaining the pressure in the process chamber above about 200 Torr and maintaining the temperature below about 700 ° C to form a phosphorus-doped bismuth carbon epitaxial film on the surface of the single crystal without growing on the surface On the second surface. 如申請專利範圍第5項所述之方法,其中該第二表面包括一介電表面。 The method of claim 5, wherein the second surface comprises a dielectric surface. 如申請專利範圍第5項所述之方法,其中所形成之該矽碳磊晶薄膜中之磷濃度大於約1020 原子/立方公分(atoms/cm3 )。The method of claim 5, wherein the concentration of phosphorus in the tantalum carbon epitaxial film formed is greater than about 10 20 atoms/cm 3 . 如申請專利範圍第1項所述之方法,其中該矽碳磊晶薄膜係在一電晶體製程之製造步驟中沉積,該製程包括: 在一製程室中,於一基材上形成一閘極介電層;在該閘極介電層上形成一閘極電極;在該基材上之該閘極電極的相對側上形成源極/汲極區,並在該等源極/汲極區之間界定出一通道區;以及直接在該等源極/汲極區上沉積該磊晶薄膜,該磊晶薄膜含有矽及碳且摻雜有磷。 The method of claim 1, wherein the tantalum carbon epitaxial film is deposited in a manufacturing process of a transistor process, the process comprising: Forming a gate dielectric layer on a substrate in a process chamber; forming a gate electrode on the gate dielectric layer; forming a source on an opposite side of the gate electrode on the substrate a drain region defining a channel region between the source/drain regions; and depositing the epitaxial film directly on the source/drain regions, the epitaxial film containing germanium and carbon It is doped with phosphorus. 如申請專利範圍第8項所述之方法,其中壓力維持在至少約300托。 The method of claim 8 wherein the pressure is maintained at at least about 300 Torr. 如申請專利範圍第8項所述之方法,其中該製程室中的溫度係維持在小於或等於約700℃。 The method of claim 8, wherein the temperature in the process chamber is maintained at less than or equal to about 700 °C. 如申請專利範圍第8項所述之方法,其中所形成之該磊晶薄膜含有取代碳(substitutional carbon),而取代碳至少為該磊晶薄膜中之總含碳量的約50%。 The method of claim 8, wherein the epitaxial film is formed to contain a substitutional carbon, and the substituted carbon is at least about 50% of the total carbon content in the epitaxial film.
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