US7132338B2 - Methods to fabricate MOSFET devices using selective deposition process - Google Patents

Methods to fabricate MOSFET devices using selective deposition process Download PDF

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US7132338B2
US7132338B2 US10845984 US84598404A US7132338B2 US 7132338 B2 US7132338 B2 US 7132338B2 US 10845984 US10845984 US 10845984 US 84598404 A US84598404 A US 84598404A US 7132338 B2 US7132338 B2 US 7132338B2
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silicon
sccm
containing layer
substrate
containing
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Arkadii V. Samoilov
Yihwan Kim
Errol Sanchez
Nicholas C. Dalida
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Applied Materials Inc
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Abstract

In one embodiment, a method for fabricating a silicon-based device on a substrate surface is provided which includes depositing a first silicon-containing layer by exposing the substrate surface to a first process gas comprising Cl2SiH2, a germanium source, a first etchant and a carrier gas and depositing a second silicon-containing layer by exposing the first silicon-containing layer to a second process gas comprising SiH4 and a second etchant. In another embodiment, a method for depositing a silicon-containing material on a substrate surface is provided which includes depositing a first silicon-containing layer on the substrate surface with a first germanium concentration of about 15 at % or more. The method further provides depositing on the first silicon-containing layer a second silicon-containing layer wherein a second germanium concentration of about 15 at % or less, exposing the substrate surface to air to form a native oxide layer, removing the native oxide layer to expose the second silicon-containing layer, and depositing a third silicon-containing layer on the second silicon-containing layer. In another embodiment, a method for depositing a silicon-containing material on a substrate surface is provided which includes depositing epitaxially a first silicon-containing layer on the substrate surface with a first lattice strain, and depositing epitaxially on the first silicon-containing layer a second silicon-containing layer with a second lattice strain greater than the first lattice strain.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of U.S. patent application Ser. No. 10/683,937, filed Oct. 10, 2003, which is herein incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention generally relate to the field of semiconductor manufacturing processes and devices, more particular, to methods of depositing silicon-containing films forming semiconductor devices.

2. Description of the Related Art

As smaller transistors are manufactured, ultra shallow source/drain junctions are becoming more challenging to produce. According to the International Technology Roadmap for Semiconductors (ITRS), junction depth is required to be less than 30 nm for sub-100 nm CMOS (complementary metal-oxide semiconductor) devices. Recently, selective SiGe epitaxy has become a useful material to deposit during formation of elevated source/drain and source/drain extension features. Source/drain extension features are manufactured by etching silicon to make a recessed source/drain feature and subsequently filling the etched surface with a selectively grown SiGe epilayer. Selective epitaxy permits near complete dopant activation with in-situ doping, so that the post annealing process is omitted. Therefore, junction depth can be defined accurately by silicon etching and selective epitaxy. On the other hand, the ultra shallow source/drain junction inevitably results in increased series resistance. Also, junction consumption during silicide formation increases the series resistance even further. In order to compensate for junction consumption, an elevated source/drain is epitaxially and selectively grown on the junction.

Selective Si-epitaxial deposition and SiGe-epitaxial deposition permits growth of epilayers on Si moats with no growth on dielectric areas. Selective epitaxy can be used in semiconductor devices, such as within elevated source/drains, source/drain extensions, contact plugs, and base layer deposition of bipolar devices. Generally, a selective epitaxy process involves two reactions: deposition and etch. The deposition and etch occur simultaneously with relatively different reaction rates on Si and on dielectric surface. A selective process window results in deposition only on Si surfaces by changing the concentration of an etchant gas (e.g., HCl).

Although SiGe-epitaxial deposition is suitable for small dimensions, this approach does not readily prepare doped SiGe, since the dopants react with HCl. The process development of heavily boron doped (e.g., higher than 5×1019 cm−3) selective SiGe-epitaxy is a much more complicated task because boron doping makes the process window for selective deposition narrow. Generally, when more boron concentration (e.g., B2H6) is added to the flow, a higher HCl concentration is necessary to achieve selectivity due to the increase growth rate of deposited film(s) on any dielectric areas. This higher HCl flow rate reduces boron incorporation into the epilayers presumably because the B—Cl bond is stronger than Ge—Cl and Si—Cl bonds.

Currently, there are two popular applications for selective silicon-based epitaxy in junction formation of silicon-containing MOSFET (metal oxide semiconductor field effect transistor) devices. One application is the process to deposit elevated source/drain (S/D) films by a selective epitaxy. Typically, this epitaxial layer is undoped silicon. Another application is filling of recessed junction areas with epitaxial silicon-containing films. Often, the silicon-based films contain germanium, carbon and/or a dopant.

MOSFET devices may contain a PMOS or a NMOS component, whereas the PMOS has a p-type channel, i.e., holes are responsible for conduction in the channel and the NMOS has an n-type channel, i.e., the electrons are responsible for conduction in the channel. For PMOS, the film in the recessed area is usually SiGe. For NMOS application, the film in the recessed area may be SiC. SiGe is used for PMOS application for several reasons. A SiGe material incorporates more boron than silicon alone, thus the junction resistivity is lowered. Also, the SiGe/silicide layer interface at the substrate surface has a lower Schottky barrier than the Si/silicide interface. Further, SiGe grown epitaxially on the top of silicon has compressive stress inside the film because the lattice constant of SiGe is larger than that of silicon. The compressive stress is transferred in the lateral dimension to create compressive strain in the PMOS channel and to increase mobility of the holes. For NMOS application, SiC can be used in the recessed areas to create tensile stress in the channel, since the lattice constant of SiC is smaller than that of silicon. The tensile stress is transferred into the channel and increases the electron mobility.

Therefore, there is a need to have a process for selectively and epitaxially depositing silicon and silicon-containing compounds with an enriched dopant concentration. Furthermore, the process should be versatile to form silicon-containing compounds with varied elemental concentrations.

SUMMARY OF THE INVENTION

In one embodiment, a method for fabricating a silicon-based device on a substrate surface is provided which includes depositing a first silicon-containing layer by exposing the substrate surface to a first process gas comprising Cl2SiH2, a germanium source, a first etchant and a carrier gas and depositing a second silicon-containing layer by exposing the first silicon-containing layer to a second process gas comprising SiH4 and a second etchant.

In another embodiment, a method for forming a silicon-based device on a substrate surface in a process chamber is provided which includes depositing a silicon-containing layer by exposing the substrate surface to a process gas comprising Cl2SiH2, Cl2SiH2, HCl, and H2. In one aspect, the process gas comprises Cl2SiH2 at a flow rate in a range from about 20 sccm to about 400 sccm, CH3SiH3 at a flow rate in a range from about 0.3 sccm to about 5 sccm, HCl at a flow rate in a range from about 30 sccm to about 500 sccm, and H2 at a flow rate in a range from about 10 slm to about 30 slm.

In another embodiment, a method for fabricating a silicon-based device on a substrate surface in a process chamber is provided which includes depositing a first silicon-containing layer by exposing the substrate surface to a process gas comprising SiH4, CH3SiH3, HCl, and H2. In one aspect, the process gas comprises SiH4 at a flow rate in a range from about 20 sccm to about 400 sccm, CH3SiH3 at a flow rate in a range from about 0.3 sccm to about 5 sccm, HCl at a flow rate in a range from about 30 sccm to about 500 sccm and H2 at a flow rate in a range from about 10 slm to about 30 slm.

In another embodiment, a method for fabricating a silicon-based device on a substrate surface in a process chamber is provided which includes depositing a first silicon-containing layer by exposing the substrate surface to a process gas comprising SiH4, GeH4, CH3SiH3, HCl, and H2. In one aspect, the process gas comprises SiH4 at a flow rate in a range from about 50 sccm to about 200 sccm, GeH4 at a flow rate in a range from about 0.5 sccm to about 5 sccm, CH3SiH3 at a flow rate in a range from about 0.3 sccm to about 5 sccm, HCl at a flow rate in a range from about 30 sccm to about 500 sccm and H2 at a flow rate in a range from about 10 slm to about 30 slm.

In another embodiment, a method for forming a silicon-based material on a substrate surface is provided which includes exposing the substrate surface to a process gas, depositing a first silicon-based layer with a crystalline lattice on the substrate surface containing less than 3 atomic percent (at %) carbon in interstitial sites of the crystalline lattice, and annealing the first silicon-based layer to incorporate at least a portion of the less than 3 at % carbon in substitutional sites of the crystalline lattice.

In another embodiment, a method for depositing a silicon-containing material on a substrate surface is provided which includes depositing a first silicon-containing layer on the substrate surface with a first germanium concentration of about 24 at % or less, depositing on the first silicon-containing layer a second silicon-containing layer wherein a second germanium concentration of about 25 at % or more of the second silicon-containing layer, and depositing on the second silicon-containing layer a third silicon-containing layer containing a third germanium concentration less than about 5 at % of the third silicon-containing layer.

In another embodiment, a method for depositing a silicon-containing material on a substrate surface is provided which includes depositing a first silicon-containing layer on the substrate surface with a first germanium concentration of about 15 at % or more. The method further provides depositing on the first silicon-containing layer a second silicon-containing layer wherein a second germanium concentration of about 15 at % or less, exposing the substrate surface to air to form a native oxide layer, removing the native oxide layer to expose the second silicon-containing layer, and depositing a third silicon-containing layer on the second silicon-containing layer.

In another embodiment, a method for depositing a silicon-containing material on a substrate surface is provided which includes depositing epitaxially a first silicon-containing layer on the substrate surface with a first lattice strain, and depositing epitaxially on the first silicon-containing layer a second silicon-containing layer with a second lattice strain greater than the first lattice strain.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

FIGS. 1A–C show several devices with epitaxially deposited silicon-containing layer; and

FIGS. 2A–F show schematic illustrations of fabrication techniques for a source/drain extension device within a MOSFET.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The invention provides a process to epitaxially deposit silicon-containing compounds during the manufacture of various device structures. In some embodiments, the process utilizes the silicon precursor silane (SiH4) during the deposition of silicon-containing materials. In some embodiments, the process utilizes the silicon precursor dichlorosilane (Cl2SiH2) during the deposition of silicon-containing materials. In other embodiments, a step-wise process using dichlorosilane in one step and silane in a later step is effective for depositing silicon-containing materials for silicon-based devices, in order to minimize defects in epitaxial layers.

Embodiments of the present invention teach processes to grow films of selective, epitaxial silicon-containing compounds. Selective silicon containing film growth generally is conducted when the substrate or surface includes more than one material, such as exposed single crystalline silicon surface areas and features that are covered with dielectric material, such as oxide or nitride layers. Usually, these features are dielectric material. Selective epitaxial growth to the crystalline, silicon surface is achieved while the feature is left bare, generally, with the utilization of an etchant (e.g., HCl). The etchant removes amorphous silicon or polysilicon growth from features quicker than the etchant removes crystalline silicon growth from the substrate, thus selective epitaxial growth is achieved.

Throughout the application, the terms “silicon-containing” materials, compounds, films or layers should be construed to include a composition containing at least silicon and may contain germanium, carbon, boron, arsenic and/or phosphorus. Other elements, such as metals, halogens or hydrogen may be incorporated within a silicon-containing material, film or layer, usually as impurities. Compounds or alloys of silicon-containing materials may be represented by an abbreviation, such as Si for silicon, SiGe, for silicon germanium, SiC for silicon carbon and SiGeC for silicon germanium carbon. The abbreviations do not represent chemical equations with stoichiometrical relationships, nor represent any particular reduction/oxidation state of the silicon-containing materials.

The processes are extremely useful while depositing silicon-containing layers in MOSFET and bipolar transistors as depicted in FIGS. 1A–1C. Herein, silicon-containing compounds are the deposited layers or films and include Si, SiGe, SiC, SiGeC, doped variants thereof and combinations thereof, epitaxially grown during the processes of the present invention. The silicon-containing compounds include strained or unstrained layers within the films.

FIGS. 1A–1B show the epitaxially grown silicon-containing compounds on a MOSFET. The silicon-containing compound is deposited to the source/drain features of the device. The silicon-containing compound adheres and grows from the crystal lattice of the underlying layer and maintains this arrangement as the silicon-containing compound grows with thickness. In one embodiment, FIG. 1A demonstrates the silicon-containing compound deposited as a recessed source/drain, while in another embodiment, FIG. 1B shows silicon-containing compounds deposited as a recessed source/drain and an elevated source/drain (ESD).

The source/drain layer 12 is formed by ion implantation of the substrate 10. Generally, the substrate 10 is doped n-type while the source/drain layer 12 is doped p-type. Silicon-containing layer 13 is selectively and epitaxially grown to the source/drain layer 12 or directly to substrate 10 by the various embodiments of the present invention. Silicon-containing layer 14 is selectively and epitaxially grown to the silicon-containing layer 13 by the various embodiments of the present invention A gate oxide layer 18 bridges the segmented silicon-containing layer 13. Generally, gate oxide layer 18 is composed of silicon dioxide, silicon oxynitride or hafnium oxide. Partially encompassing the gate oxide layer 18 is a spacer 16, which is usually an isolation material such as a nitride/oxide stack (e.g., Si3N4/SiO2/Si3N4). Gate layer 22 (e.g., polysilicon) may have a protective layer 19, such as silicon dioxide, along the perpendicular sides, as in FIG. 1A. Alternately, gate layer 22 may have a spacer 16 and off-set layers 20 (e.g., Si3N4) disposed on either side.

In another embodiment, FIG. 1C depicts the deposited silicon-containing compound layer 34 as a base layer of a bipolar transistor. The silicon-containing compound layer 34 is epitaxially grown with the various embodiments of the invention. The silicon-containing compound layer 34 is deposited to an n-type collector layer 32 previously deposited to substrate 30. The transistor further includes isolation layer 33 (e.g., SiO2 or Si3N4), contact layer 36 (e.g., heavily doped poly-Si), off-set layer 38 (e.g., Si3N4), and a second isolation layer 40 (e.g., SiO2 or Si3N4).

In one embodiment, as depicted in FIGS. 2A–2F, a source/drain extension is formed within a MOSFET wherein the silicon-containing layers are epitaxially and selectively deposited on the surface of the substrate. FIG. 2A depicts a source/drain layer 132 formed by implanting ions into the surface of a substrate 130. The segments of source/drain layer 132 are bridged by the gate 136 formed on gate oxide layer 135 and subsequent deposition of off-set layer 134. A portion of the source/drain layer is etched and wet-cleaned, to produce a recess 138, as in FIG. 2B. A portion of gate 136 may also be etched, or optionally a hardmask may be deposited prior to etching to avoid gate material removal.

FIG. 2C illustrates several embodiments of the present invention, in which silicon-containing layers 140 (epitaxial) and 142 (polycrystalline) are selectively deposited. Silicon-containing layer 142 is optionally omitted by depositing a hardmask over gate 136 prior to depositing silicon-containing layer 140. Silicon-containing compound layers 140 and 142 are deposited simultaneously without depositing on the off-set layer 134. In one embodiment, silicon-containing layers 140 and 142 are SiGe-containing layers with a germanium concentration at about 1 at % to about 50 at %, preferably about 24 at % or less. Multiple SiGe-containing layers containing varying amount of elements may be stacked to form silicon-containing layer 140 with a graded elemental concentration. For example, a first SiGe-layer may be deposited with a germanium concentration in a range from about 15 at % to about 25 at % and a second SiGe-layer may be deposited with a germanium concentration in a range from about 25 at % to about 35 at %.

In another embodiment, silicon-containing layers 140 and 142 are SiC-containing layers with a carbon concentration from about 200 ppm to about 5 at %, preferably about 3 at % or less, for example, from about 1 at % to about 2 at %, about 1.5 at %. In another embodiment, silicon-containing layers 140 and 142 are SiGeC-containing layers with a germanium concentration from about 1 at % to about 50 at %, preferably about 24 at % or less and a carbon concentration at about 200 ppm to about 5 at %, preferably about 3 at % or less, more preferably from about 1 at % to about 2 at %, for example, about 1.5 at %.

Multiple layers containing Si, SiGe, SiC or SiGeC may be deposited in varying order to form graded elemental concentrations of silicon-containing layer 140. The silicon-containing layers are generally doped with a dopant (e.g., B, As or P) having a concentration in the range from about 1×1019 atoms/cm3 to about 2.5×1021 atoms/cm3, preferably from about 5×1019 atoms/cm3 to about 2×1020 atoms/cm3. Dopants added in individual layers of silicon-containing material forms graded dopant. For example, silicon-containing layer 140 is formed by depositing a first SiGe-containing layer with a dopant concentration (e.g., boron) at a range from about 5×1019 atoms/cm3 to about 1×1020 atoms/cm3 and a second SiGe-containing layer with a dopant concentration (e.g., boron) at a range from about 1×1020 atoms/cm3 to about 2×1020 atoms/cm3.

Carbon incorporated in SiC-containing layers and SiGeC-containing layers is generally located in interstitial sites of the crystalline lattice immediately following the deposition of the silicon-containing layer. The interstitial carbon content is about 10 at % or less, preferably less then 5 at % and more preferably from about 1 at % to about 3 at %, for example, about 2 at %. The silicon-containing layer may be annealed to incorporate at least a portion, if not all of the interstitial carbon into substitutional sites of the crystalline lattice. The annealing process may include a spike anneal, such as rapid thermal process (RTP), laser annealing or thermal annealing with an atmosphere of gas, such as oxygen, nitrogen, hydrogen, argon, helium or combinations thereof. The annealing process is conducted at a temperature from about 800° C. to about 1,200° C., preferably from about 1,050° C. to about 1,100° C. The annealing process may occur immediately after the silicon-containing layer is deposited or after a variety of other process steps the substrate will endure.

During the next step, FIG. 2D shows a spacer 144, generally a nitride spacer (e.g., Si3N4) deposited to the off-set layer 134. Spacer 144 is usually deposited in a different chamber. Therefore, the substrate is removed from the process chamber that was used to deposit silicon-containing layer 140. During the transfer between the two chambers, the substrate may be exposed to ambient conditions, such as the temperature, pressure or the atmospheric air containing water and oxygen. Upon depositing the spacer 144, or performing other semiconductor process (e.g., anneal, deposition or implant), the substrate may be exposed to ambient conditions a second time prior to depositing silicon-containing layers 146 and 148. In one embodiment, an epitaxial layer (not shown) with no or minimal germanium (e.g., less than about 5 at %) is deposited on the top of layer 140 before exposing the substrate to ambient conditions since native oxides are easier to remove from epitaxial layers containing minimal germanium concentrations than from an epitaxial layer formed with a germanium concentration greater than about 5 at %.

FIG. 2E depicts another embodiment of the present invention, in which a silicon-containing compound is epitaxially and selectively deposited as silicon-containing layer 148, an elevated layer. Silicon-containing layer 148 is deposited on layer 140 (e.g., doped-SiGe) while polysilicon is deposited on the silicon-containing layer 142 to produce polysilicon layer 146. Depending on the elemental concentrations of silicon-containing layer 142 and polysilicon deposited thereto, the elemental concentrations of polysilicon layer 146 will inheritably contain these elemental concentrations, including graded concentrations when both layers are different.

In a preferred embodiment, silicon-containing layer 148 is epitaxially deposited silicon containing little or no germanium or carbon. However, in another embodiment, silicon-containing layer 148 does contain germanium and/or carbon. For example, silicon-containing layer 148 may have about 5 at % or less germanium. In another example, silicon-containing layer 148 may have about 2 at % or less carbon. Silicon-containing layer 148 may also be doped with a dopant, such as boron, arsenic or phosphorus.

In the next step shown in FIG. 2F, a metal layer 154 is deposited over the features and the device is annealed. The metal layer 154 includes cobalt, nickel or titanium, among other metals. During the annealing process, polysilicon layer 146 and silicon-containing compound layer 148 are converted to metal silicide layers, 150 and 152, respectively. That is, when cobalt is deposited as metal layer 154, then metal silicide layers 150 and 152 are cobalt silicide.

The silicon-containing compound may be heavily doped with the in-situ dopants. Therefore, annealing steps of the prior art are omitted and the overall throughput is shorter. An increase of carrier mobility along the channel and subsequent drive current is achieved with the optional addition of germanium and/or carbon into the silicon-containing compound layer. Selectively grown epilayers of the silicon-containing compound above the gate oxide level can compensate junction consumption during the silicidation, which can relieve concerns of high series resistance of ultra shallow junctions. These two applications can be implemented together as well as solely for CMOS device fabrication.

Silicon-containing compounds are utilized within embodiments of the processes to deposit silicon-containing compounds films used for Bipolar (e.g., base, emitter, collector, emitter contact), BiCMOS (e.g., base, emitter, collector, emitter contact) and CMOS (e.g., channel, source/drain, source/drain extension, elevated source/drain, substrate, strained silicon, silicon on insulator and contact plug). Other embodiments of processes teach the growth of silicon-containing compounds films that can be used as gate, base contact, collector contact, emitter contact, elevated source/drain and other uses.

In one embodiment of the invention, a silicon-containing film is epitaxially grown as a Si film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane or dichlorosilane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2) and an etchant (e.g., HCl). The flow rate of the silicon precursor is in the range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm. The flow rate of the carrier gas is from about 10 slm to about 30 slm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm, preferably from about 30 sccm to about 500 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 50 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 600° C. to about 900° C., more preferably from about 650° C. to about 750° C., for example about 720° C. The mixture of reagents is thermally driven to react and epitaxially deposit crystalline silicon. The HCl etches any deposited amorphous silicon or polycrystalline silicon from dielectric features upon the surface of the substrate. The process is conducted to form the deposited silicon film with a thickness in a range from about 10 Å to about 3,000 Å, for example, from about 40 Å to about 100 Å. In another example, the deposited silicon-containing film has a thickness in a range from about 200 Å to about 600 Å. In one embodiment, the silicon-containing film has a thickness greater than 500 Å, such as about 1,000 Å.

Etchants are utilized to control the areas on the device to be free of deposited silicon-containing compound. Etchants that are useful during deposition processes of the invention include HCl, HF, HBr, Si2Cl6, SiCl4, Cl2SiH2, CCl4, Cl2 and combinations thereof. Other silicon precursors, besides silane and dichlorosilane, which are useful while depositing silicon-containing compounds include higher silanes, halogenated silanes and organosilanes. Higher silanes include the compounds with the empirical formula SixH(2x+2), such as disilane (Si2H6), trisilane (Si3H8), and tetrasilane (Si4H10), as well as others. Halogenated silanes include compounds with the empirical formula X′ySixH(2x+2−y), where X′=F, Cl, Br or I, such as hexachlorodisilane (Si2Cl6), tetrachlorosilane (SiCl4), dichlorosilane (Cl2SiH2) and trichlorosilane (Cl3SiH). Organosilanes include compounds with the empirical formula RySixH(2x+2−y), where R=methyl, ethyl, propyl or butyl, such as methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CH3)2Si2H4) and hexamethyldisilane ((CH3)6Si2). Organosilane compounds have been found to be advantageous silicon sources and carbon sources during embodiments of the present invention to incorporate carbon in to deposited silicon-containing compound.

Carrier gases are used throughout the processes and include H2, Ar, N2, He, forming gas and combinations thereof. In one example, H2 is used as a carrier gas. In another example N2 is used as a carrier gas. In one embodiment, a carrier gas during an epitaxial deposition process is conducted with neither H2 nor atomic hydrogen. However, an inert gas is used as a carrier gas, such as N2, Ar, He and combinations thereof. Carrier gases may be combined in various ratios during some embodiments of the process. For example, a carrier gas may include N2 and/or Ar to maintain available sites on the silicon-containing compound film. The presence of hydrogen on the silicon-containing compound surface limits the number of available sites (i.e., passivates) for Si or SiGe to grow when an abundance of H2 is used as a carrier gas. Consequently, a passivated surface limits the growth rate at a given temperature, particularly at lower temperatures (e.g., <650° C.). Therefore, a carrier gas of N2 and/or Ar may be used during a process at lower temperature and reduce the thermal budget without sacrificing growth rate.

In another embodiment of the invention, a silicon-containing film is epitaxially grown as a SiGe film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane or dichlorosilane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a germanium source (e.g., GeH4) and an etchant (e.g., HCl). The flow rate of the silicon precursor is in the range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm. The flow rate of the carrier gas is from about 10 slm to about 30 slm. The flow rate of the germanium source is from about 0.1 sccm to about 10 sccm, preferably from about 0.5 sccm to about 5 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm, preferably from about 30 sccm to about 500 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 5 Torr, for example, about 3 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 700° C. to about 900° C. The reagent mixture is thermally driven to react and epitaxially deposit a silicon-containing compound, namely a silicon germanium film. The HCl etches any deposited amorphous SiGe compounds from dielectric features upon the surface of the substrate.

The process is conducted to form the deposited SiGe film with a thickness in a range from about 10 Å to about 3,000 Å, for example, from about 40 Å to about 100 Å. In another example, the deposited silicon-containing film has a thickness in a range from about 200 Å to about 600 Å. In one embodiment, the silicon-containing film has a thickness greater than 500 Å, such as about 1,000 Å. The germanium concentration may be graded within the SiGe film, preferably graded with a higher germanium concentration in the lower portion of the SiGe film than in the upper portion of the SiGe film. The germanium concentration is in the range from about 1 at % to about 30 at % of the SiGe compound, for example, about 20 at %.

Other germanium sources or precursors, besides germane, that are useful while depositing silicon-containing compounds include higher germanes and organogermanes. Higher germanes include the compounds with the empirical formula GexH(2x+2), such as digermane (Ge2H6), trigermane (Ge3H8) and tetragermane (Ge4H10), as well as others. Organogermanes include compounds with the empirical formula RyGexH(2x+2−y), where R=methyl, ethyl, propyl or butyl, such as methylgermane ((CH3)GeH3), dimethylgermane ((CH3)2GeH2), ethylgermane ((CH3CH2)GeH3), methyldigermane ((CH3)Ge2H5), dimethyldigermane ((CH3)2Ge2H4) and hexamethyldigermane ((CH3)6Ge2). Germanes and organogermane compounds have been found to be an advantageous germanium sources and carbon sources during embodiments of the present invention to incorporate germanium and carbon in to the deposited silicon-containing compounds, namely SiGe and SiGeC compounds. Germanium sources are often mixed with a carrier gas (e.g., H2) to dilute and therefore better control the germanium doses. For example, a germanium source with a flow rate in the range from about 0.5 sccm to about 5 sccm is equivalent to a flow of 1% germanium source in a carrier gas with a flow rate in the range from about 50 sccm to about 500 sccm. Throughout the disclosure, the flow rate of germanium source ignores the flow rate of the carrier gas.

In one embodiment of the invention, a silicon-containing film is epitaxially grown as a doped Si film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane or dichlorosilane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a dopant (e.g., B2H6) and an etchant (e.g., HCl). The flow rate of the silicon precursor is in the range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm. The flow rate of the carrier gas is from about 10 slm to about 30 slm. The flow rate of the dopant is from about 0.01 sccm to about 10 sccm, preferably from about 0.2 sccm to about 2 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm, preferably from about 30 sccm to about 500 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 5 Torr, for example, about 3 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 700° C. to about 900° C. The mixture of reagents is thermally driven to react and epitaxially deposit doped silicon films. The HCl etches any deposited amorphous silicon or polycrystalline silicon from dielectric features upon the surface of the substrate.

The process is conducted to form the deposited, doped silicon-containing film with a thickness in a range from about 10 Å to about 3,000 Å, for example, from about 40 Å to about 100 Å. In another example, the deposited silicon-containing film has a thickness in a range from about 200 Å to about 600 Å. In one embodiment, the silicon-containing film has a thickness greater than 500 Å, such as about 1,000 Å. The dopant concentration may be graded within the Si film, preferably graded with a higher dopant concentration in the lower portion of the Si film than in the upper portion of the Si film.

Dopants provide the deposited silicon-containing compounds with various conductive characteristics, such as directional electron flow in a controlled and desired pathway required by the electronic device. Films of the silicon-containing compounds are doped with particular dopants to achieve the desired conductive characteristic. In one embodiment, the silicon-containing compound is doped p-type, such as by using diborane to add boron at a concentration in the range from about 1015 atoms/cm3 to about 1021 atoms/cm3. In one embodiment, the p-type dopant has a concentration of at least 5×1019 atoms/cm3. In another embodiment, the p-type dopant is in the range from about 1×1020 atoms/cm3 to about 2.5×1021 atoms/cm3. In another embodiment, the silicon-containing compound is doped n-type, such as with phosphorus and/or arsenic to a concentration in the range from about 1015 atoms/cm3 to about 1021 atoms/cm3.

Besides diborane, other boron containing dopants include boranes and organoboranes. Boranes include borane, triborane, tetraborane and pentaborane, while alkylboranes include compounds with the empirical formula RxBH(3−x), where R=methyl, ethyl, propyl or butyl and x=0, 1, 2 or 3. Alkylboranes include trimethylborane ((CH3)3B), dimethylborane ((CH3)2BH), triethylborane ((CH3CH2)3B) and diethylborane ((CH3CH2)2BH). Dopants also include arsine (AsH3), phosphine (PH3) and alkylphosphines, such as with the empirical formula RxPH(3−x), where R=methyl, ethyl, propyl or butyl and x=0, 1, 2 or 3. Alkylphosphines include trimethylphosphine ((CH3)3P), dimethylphosphine ((CH3)2PH), triethylphosphine ((CH3CH2)3P) and diethylphosphine ((CH3CH2)2PH). Dopants are often mixed with a carrier gas (e.g., H2) to dilute and therefore better control the doping doses. For example, a flow rate of dopant in the range from about 0.2 sccm to about 2 sccm is equivalent to a flow of 1% dopant in a carrier gas with a flow rate in the range from about 20 sccm to about 200 sccm. Throughout the disclosure, the flow rate of dopant ignores the flow rate of the carrier gas.

In another embodiment of the invention, a silicon-containing film is epitaxially grown to produce a doped SiGe film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane or dichlorosilane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a germanium source (e.g., GeH4), a dopant (e.g., B2H6) and an etchant (e.g., HCl). The flow rate of the silicon precursor is in the range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm. The flow rate of the carrier gas is from about 10 slm to about 30 slm. The flow rate of the germanium source is from about 0.1 sccm to about 10 sccm, preferably from about 0.5 sccm to about 5 sccm. The flow rate of the dopant is from about 0.01 sccm to about 10 sccm, preferably from about 0.2 sccm to about 3 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm, preferably from about 30 sccm to about 500 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 5 Torr, for example, about 3 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 700° C. to about 900° C. The reagent mixture is thermally driven to react and epitaxially deposit a silicon-containing compound, namely a silicon germanium film. The HCl etches any deposited amorphous SiGe from features upon the surface of the substrate. The process is conducted to form the doped SiGe film with a thickness in a range from about 10 Å to about 3,000 Å, for example, from about 40 Å to about 100 Å. In another example, the deposited silicon-containing film has a thickness in a range from about 200 Å to about 600 Å. In one embodiment, the silicon-containing film has a thickness greater than 500 Å, such as about 1,000 Å. The germanium concentration and the dopant concentration may be graded within the doped SiGe film, preferably graded with a higher germanium concentration and/or dopant concentration in the lower portion of the doped SiGe film than in the upper portion of the doped SiGe film. The germanium concentration is in the range from about 1 at % to about 50 at %, preferably from about 15 at % to about 35 at % of the SiGe compound. The boron concentration is in the range from about 1×1019 atoms/cm3 to about 2.5×1021 atoms/cm3 of the SiGe compound, for example, about 1×1020 atoms/cm3.

In another embodiment of the invention, a silicon-containing film is epitaxially grown as a SiC film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane or dichlorosilane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a carbon source (e.g., CH3SiH3) and an etchant (e.g., HCl). The flow rate of the silicon precursor is in the range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm. The flow rate of the carrier gas is from about 10 slm to about 30 slm. The flow rate of the carbon source is from about 0.1 sccm to about 15 sccm, preferably from about 0.3 sccm to about 5 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm, preferably from about 30 sccm to about 500 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 5 Torr, for example, about 3 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 700° C. to about 900° C. The reagent mixture is thermally driven to react and epitaxially deposit a silicon-containing compound, namely a silicon carbon film. The HCl etches any deposited amorphous SiC compounds from dielectric features upon the surface of the substrate.

The process is conducted to form the deposited SiC film with a thickness in a range from about 10 Å to about 3,000 Å, for example, from about 40 Å to about 100 Å. In another example, the deposited silicon-containing film has a thickness in a range from about 200 Å to about 600 Å. In one embodiment, the silicon-containing film has a thickness greater than 500 Å, such as about 1,000 Å. The carbon concentration may be graded within the SiC film, preferably graded with a higher carbon concentration in the lower portion of the SiC film than in the upper portion of the SiC film. The carbon concentration of the SiC film is in the range from about 200 ppm to about 5 at %, preferably from about 1 at % to about 3 at %, for example 1.5 at %.

Carbon sources useful for depositing silicon-containing compounds containing carbon include organosilanes, alkyls, alkenes and alkynes of ethyl, propyl and butyl. Such carbon sources include methylsilane (CH3SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane (CH3CH2SiH3), methane (CH4), ethylene (C2H4), ethyne (C2H2), propane (C3H8), propene (C3H6), butyne (C4H6), as well as others. Carbon sources are often mixed with a carrier gas (e.g., H2) to dilute and therefore better control the carbon doses. For example, a carbon source with a flow rate in the range from about 0.3 sccm to about 5 sccm is equivalent to a flow of 1% carbon source in a carrier gas with a flow rate in the range from about 30 sccm to about 500 sccm. Throughout the disclosure, the flow rate of carbon source ignores the flow rate of the carrier gas.

In another embodiment of the invention, a silicon-containing film is epitaxially grown to produce a doped SiC film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane or dichlorosilane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a carbon source (e.g., CH3SiH3), a dopant (e.g., B2H6) and an etchant (e.g., HCl). The flow rate of the silicon precursor is in the range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm. The flow rate of the carrier gas is from about 10 slm to about 30 slm. The flow rate of the carbon source is from about 0.1 sccm to about 15 sccm, preferably from about 0.3 sccm to about 5 sccm. The flow rate of the dopant is from about 0.01 sccm to about 10 sccm, preferably from about 0.2 sccm to about 3 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm, preferably from about 30 sccm to about 500 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 5 Torr, for example, about 3 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 700° C. to about 900° C. The reagent mixture is thermally driven to react and epitaxially deposit a silicon-containing compound, namely a doped silicon carbon film. The HCl etches any deposited amorphous SiC from features upon the surface of the substrate.

The process is conducted to form the doped SiC film with a thickness in a range from about 10 Å to about 3,000 Å, for example, from about 40 Å to about 100 Å. In another example, the deposited silicon-containing film has a thickness in a range from about 200 Å to about 600 Å. In one embodiment, the silicon-containing film has a thickness greater than 500 Å, such as about 1,000 Å. The carbon concentration and/or the dopant concentration may be graded within the doped SiC film, preferably graded with a higher carbon concentration and/or dopant concentration in the lower portion of the doped SiC film than in the upper portion of the doped SiC film. The carbon concentration of the doped SiC film is in the range from about 200 ppm to about 5 at %, preferably from about 1 at % to about 3 at %, for example 1.5 at %. The boron concentration is in the range from about 1×1019 atoms/cm3 to about 2.5×1021 atoms/cm3 of the SiGe compound, for example, about 1×1020 atoms/cm3.

In another embodiment of the invention, a silicon-containing film is epitaxially grown as a SiGeC film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane or dichlorosilane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a germanium source (e.g., GeH4), a carbon source (e.g., CH3SiH3) and an etchant (e.g., HCl). The flow rate of the silicon precursor is in the range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm. The flow rate of the carrier gas is from about 10 slm to about 30 slm. The flow rate of the germanium source is from about 0.1 sccm to about 10 sccm, preferably from about 0.5 sccm to about 5 sccm. The flow rate of the carbon source is from about 0.1 sccm to about 50 sccm, preferably from about 0.3 sccm to about 5 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm, preferably from about 30 sccm to about 500 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 5 Torr, for example, about 3 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 500° C. to about 700° C. The reagent mixture is thermally driven to react and epitaxially deposit a silicon-containing compound, namely a silicon germanium carbon film. The HCl etches any deposited amorphous or polycrystalline SiGeC compounds from dielectric features upon the surface of the substrate.

The process is conducted to form the deposited SiGeC compound with a thickness in a range from about 10 Å to about 3,000 Å, for example, from about 40 Å to about 100 Å. In another example, the deposited silicon-containing compound has a thickness in a range from about 200 Å to about 600 Å. In one embodiment, the silicon-containing compound has a thickness greater than 500 Å, such as about 1,000 Å. The germanium concentration and/or the carbon concentration may be graded within the SiGeC film, preferably graded with a higher germanium concentration and/or carbon concentration in the lower portion of the SiGeC film than in the upper portion of the SiGeC film. The germanium is in the range from about 1 at % to about 50 at %, preferably from about 15 at % to about 35 at % of the SiGeC compound. The carbon concentration is in the range from about 200 ppm to about 5 at %, preferably from about 1 at % to about 3 at % of the SiGeC compound.

In another embodiment of the invention, a silicon-containing compound film is epitaxially grown as a doped SiGeC film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane or dichlorosilane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a germanium source (e.g., GeH4), a carbon source (e.g., CH3SiH3), a dopant (e.g., B2H6) and an etchant (e.g., HCl). The flow rate of the silicon precursor is in the range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm. The flow rate of the carrier gas is from about 10 slm to about 30 slm. The flow rate of the germanium source is from about 0.1 sccm to about 10 sccm, preferably from about 0.5 sccm to about 5 sccm. The flow rate of the carbon source is from about 0.1 sccm to about 50 sccm, preferably from about 0.3 sccm to about 5 sccm. The flow rate of the dopant is from about 0.01 sccm to about 10 sccm, preferably from about 0.2 sccm to about 3 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm, preferably from about 30 sccm to about 500 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 5 Torr, for example, about 3 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 500° C. to about 700° C. The reagent mixture is thermally driven to react and epitaxially deposit a silicon-containing compound, namely a doped silicon germanium carbon film. The HCl etches any deposited amorphous or polycrystalline SiGeC compounds from dielectric features upon the surface of the substrate.

The process is conducted to form a doped SiGeC compound with a thickness in a range from about 10 Å to about 3,000 Å, for example, from about 40 Å to about 100 Å. In another example, the deposited silicon-containing compound has a thickness in a range from about 200 Å to about 600 Å. In one embodiment, the silicon-containing compound has a thickness greater than 500 Å, such as about 1,000 Å. The germanium concentration, the carbon concentration and/or the dopant concentration may be graded within the doped SiGeC film, preferably graded with a higher germanium concentration, carbon concentration and/or dopant concentration in the lower portion of the doped SiGeC film than in the upper portion of the doped SiGeC film. The germanium concentration is in the range from about 1 at % to about 50 at %, preferably from about 15 at % to about 35 at % of the doped SiGeC compound. The carbon concentration is in the range from about 0.1 at % to about 5 at %, preferably from about 1 at % to about 3 at % of the doped SiGeC compound. The boron concentration is in the range from about 1×1019 atoms/cm3 to about 2.5×1021 atoms/cm3 of the SiGe compound, for example, about 1×1020 atoms/cm3.

In another embodiment of the invention, a second silicon-containing film is epitaxially grown by using dichlorosilane, subsequently to depositing any of the silicon-containing compounds aforementioned in the above disclosure. A substrate (e.g., 300 mm OD) containing any of the above described silicon containing compounds is placed into the process chamber. During this deposition technique, silicon precursor (e.g., Cl2SiH2) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a germanium source (e.g., GeH4) and an etchant (e.g., HCl). The flow rate of the dichlorosilane is in the range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm. The flow rate of the carrier gas is from about 10 slm to about 30 slm. The flow rate of the germanium source is from about 0.1 sccm to about 10 sccm, preferably from about 0.5 sccm to about 5 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm, preferably from about 30 sccm to about 500 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably less than about 5 Torr, for example, about 3 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 700° C. to about 900° C. The reagent mixture is thermally driven to react and epitaxially deposit a second silicon-containing compound, namely a silicon germanium film. The HCl etches any deposited amorphous or polycrystalline SiGe compounds from any dielectric features upon the surface of the substrate. The process is conducted to form the deposited SiGe compound with a thickness in a range from about 100 Å to about 3,000 Å and at a deposition rate between about 10 Å/min and about 100 Å/min, preferably at about 50 Å/min. The germanium concentration is in the range from about 1 at % to about 30 at % of the SiGe compound, preferably at about 20 at %. This embodiment describes a process to deposit a SiGe film, though substitution of silane with dichlorosilane to any of the previously described embodiments will produce a second silicon containing film. In another embodiment, a third silicon containing layer is deposited using any of the silane based process discussed above.

Therefore, in one embodiment, a silicon-containing compound laminate film may be deposited in sequential layers of silicon-containing compound by altering the silicon precursor between silane and dichlorosilane. In one example, a laminate film of about 2,000 Å is formed by depositing four silicon-containing compound layers (each of about 500 Å), such that the first and third layers are deposited using dichlorosilane and the second and fourth layers are deposited using silane. In another aspect of a laminate film, the first and third layers are deposited using silane and the second and fourth layers are deposited using dichlorosilane. The thickness of each layer is independent from each other; therefore, a laminate film may have various thicknesses of the silicon-containing compound layers.

In one embodiment, dichlorosilane is used to deposit the silicon-containing compound layer when the previous layer contains surface islands (e.g., contamination or irregularity to film). A process incorporating dichlorosilane may be less sensitive to the surface islands while depositing the silicon-containing compound layer over the previous layer. The use of dichlorosilane as the silicon source has a high horizontal or lateral growth rate relative to the use of silane. Once the surface island is covered and the silicon-containing compound layer has a consistent surface, dichlorosilane is replaced with silane and deposition of the silicon-containing compound layer is continued.

In another embodiment, the substrate surface may be exposed to ambient conditions, such as air including oxygen and/or water, between process steps. The ambient exposure is generally endured while shuffling substrates between multiple process chambers during the fabrication of devices. A first silicon-containing layer is deposited to the substrate surface, the substrate is exposed to ambient conditions, and subsequently, a second silicon-containing layer is deposited to the substrate surface. In one aspect, a cap-layer is deposited to the first silicon-containing layer before the ambient exposure. The cap-layer may be a dielectric material, such as silicon. For example, a silicon-germanium layer is deposited to the substrate surface, a silicon-cap layer is deposited to the silicon-germanium layer, the substrate is exposed to ambient conditions, and subsequently a second-silicon containing layer is deposited to the silicon-cap layer, such as a silicon layer or a silicon-carbon layer.

Embodiments of the invention teach processes to deposit silicon-containing compounds on many substrates and surfaces. Substrates on which embodiments of the invention may be useful include, but are not limited to semiconductor wafers, such as crystalline silicon (e.g., Si<100> and Si<111>), silicon oxide, silicon germanium, doped or undoped wafers and patterned or non-patterned wafers. Substrates have a variety of geometries (e.g., round, square and rectangular) and sizes (e.g., 200 mm OD, 300 mm OD). Surfaces and./or substrates include wafers, films, layers and materials with dielectric, conductive and barrier properties and include polysilicon, silicon on insulators (SOI), strained and unstrained lattices. Pretreatment of surfaces includes polishing, etching, reduction, oxidation, hydroxylation, annealing and baking. In one embodiment, wafers are dipped into a 1% HF solution, dried and baked in a hydrogen atmosphere at 800° C.

In one embodiment, silicon-containing compounds include a germanium concentration within the range from about 0 at % to about 95 at %. In another embodiment, a germanium concentration is within the range from about 1 at % to about 30 at %, preferably from about 15 at % to about 30 at %, for example, about 20 at %. Silicon-containing compounds also include a carbon concentration within the range from about 0 at % to about 5 at %. In other aspects, a carbon concentration is within the range from about 200 ppm to about 3 at %, preferably about 1.5 at %.

The silicon-containing compound films of germanium and/or carbon are produced by various processes of the invention and can have consistent, sporadic or graded elemental concentrations. Graded silicon germanium films are disclosed in United States Patent Applications 20020174826 and 20020174827 assigned to Applied Material, Inc., and are incorporated herein by reference in entirety for the purpose of describing methods of depositing graded silicon-containing compound films. In one embodiment, a silicon source and a germanium source (e.g., GeH4) are used to deposit silicon germanium containing films. In this embodiment, the ratio of silicon source and germanium source can be varied in order to provide control of the elemental concentrations, such as silicon and germanium, while growing graded films. In another embodiment, a silicon source and a carbon source (e.g., CH3SiH3) are used to deposit silicon carbon containing films. The ratio of silicon source and carbon source can be varied in order to provide control of the elemental concentration while growing homogenous or graded films. In another embodiment, a silicon source, a germanium source (e.g., GeH4) and a carbon source (e.g., CH3SiH3) are used to deposit silicon germanium carbon containing films. The ratios of silicon, germanium and carbon sources are independently varied in order to provide control of the elemental concentration while growing homogenous or graded films.

MOSFET devices formed by processes described herein may contain a PMOS component or a NMOS component. The PMOS component, with a p-type channel, has holes that are responsible for channel conduction, while the NMOS component, with a n-type channel, has electrons that are responsible channel conduction. Therefore, for example, a silicon-containing material such as SiGe may be deposited in a recessed area to form a PMOS component. In another example, a silicon-containing film such as SiC may be deposited in a recessed area to form a NMOS component. SiGe is used for PMOS application for several reasons. A SiGe material incorporates more boron than silicon alone, thus the junction resistivity may be lowered. Also, the SiGe/silicide layer interface at the substrate surface has a lower Schottky barrier than the Si/silicide interface.

Further, SiGe grown epitaxially on the top of silicon has compressive stress inside the film because the lattice constant of SiGe is larger than that of silicon. The compressive stress is transferred in the lateral dimension to create compressive strain in the PMOS channel and to increase mobility of the holes. For NMOS application, SiC can be used in the recessed areas to create tensile stress in the channel, since the lattice constant of SiC is smaller than that of silicon. The tensile stress is transferred into the channel and increases the electron mobility. Therefore, in one embodiment, a first silicon-containing layer is formed with a first lattice strain value and a second silicon-containing layer is formed with a second lattice strain value. For example, a SiC layer with a thickness from about 50 Å to about 200 Å is deposited to the substrate surface and sequentially, a SiGe layer with a thickness from about 150 Å to about 1,000 Å is deposited to the SiC layer. The SiC layer may be epitaxially grown and has less strain than the SiGe layer epitaxially grown on the SiC layer.

In processes of the invention, silicon-containing compound films are grown by chemical vapor deposition (CVD) processes, wherein CVD processes include atomic layer deposition (ALD) processes and/or atomic layer epitaxy (ALE) processes. Chemical vapor deposition includes the use of many techniques, such as plasma-assisted CVD (PA-CVD), atomic layer CVD (ALCVD), organometallic or metalorganic CVD (OMCVD or MOCVD), laser-assisted CVD (LA-CVD), ultraviolet CVD (UV-CVD), hot-wire (HWCVD), reduced-pressure CVD (RP-CVD), ultra-high vacuum CVD (UHV-CVD) and others. In one embodiment, the preferred process of the present invention is to use thermal CVD to epitaxially grow or deposit the silicon-containing compound, whereas the silicon-containing compound includes silicon, SiGe, SiC, SiGeC, doped variants thereof and combinations thereof.

The processes of the invention can be carried out in equipment known in the art of ALE, CVD and ALD. The apparatus brings the sources into contact with a heated substrate on which the silicon-containing compound films are grown. The processes can operate at a range of pressures from about 0.1 Torr to about 200 Torr, preferably from about 0.5 Torr to about 50 Torr, and more preferably from about 1 Torr to about 10 Torr. Hardware that can be used to deposit silicon-containing films includes the Epi Centura® system and the Poly Gen® system available from Applied Materials, Inc., located in Santa Clara, Calif. An ALD apparatus is disclosed in United States Patent Application 20030079686, assigned to Applied Material, Inc., and entitled “Gas Delivery Apparatus and Methods for ALD”, and is incorporated herein by reference in entirety for the purpose of describing the apparatus. Other apparatuses include batch, high-temperature furnaces, as known in the art.

EXAMPLES Example 1

SiGe/Si Stack:

A substrate, Si<100>, (e.g., 300 mm OD) was employed to investigate selective, monocrystalline film growth by CVD. A dielectric feature existed on the surface of the wafer. The wafer was prepared by subjecting to a 1% HF dip for 45 seconds. The wafer was loaded into the deposition chamber (Epi Centura® chamber) and baked in a hydrogen atmosphere at 800° C. for 60 seconds to remove native oxide. A flow of carrier gas, hydrogen, was directed towards the substrate and the source compounds were added to the carrier flow. Dichlorosilane (100 sccm) and germane (1% GeH4 in H2, 280 sccm) were added to the chamber at 3 Torr and 725° C. Also, hydrogen chloride (190 sccm) and diborane (1% in H2, 150 sccm) were delivered to the chamber. The substrate was maintained at 725° C. Deposition was conducted for about 5 minutes to form a 500 Å SiGe film with a germanium concentration of about 20 at % and the boron concentration of about 1.0×1020 cm−3. The substrate was removed from the process chamber and exposed to the ambient air. The substrate was loaded into a second deposition chamber (Epi Centura® chamber) and heated to 800° C. The substrate was exposed to a process gas containing silane (100 sccm) and hydrogen chloride (250 sccm) for about 10 minutes to selectively deposit a Si film on the SiGe film.

Example 2

Graded-SiGe/Si Stack:

A substrate, Si<100>, (e.g., 300 mm OD) was employed to investigate selective, monocrystalline film growth by CVD. A dielectric feature existed on the surface of the wafer. The wafer was prepared by subjecting to a 1% HF dip for 45 seconds. The wafer was loaded into the deposition chamber (Epi Centura® chamber) and baked in a hydrogen atmosphere at 800° C. for 60 seconds to remove native oxide. A first SiGe film was deposited by directing a hydrogen carrier gas towards the substrate and the source compounds were added to the carrier flow. Dichlorosilane (100 sccm) and germane (1% GeH4 in H2, 190 sccm) were added to the chamber at 3 Torr and 725° C. Also, hydrogen chloride (160 sccm) and diborane (1% in H2, 150 sccm) were delivered to the chamber. The substrate was maintained at 725° C. Deposition was conducted for 2 minutes to form a 100 Å SiGe film with a germanium concentration of 15 at % and the boron concentration of about 5.0×1019 cm−3. A second SiGe film was deposited to the first SiGe film to form a graded-SiGe film. Dichlorosilane (100 sccm) and germane (1% GeH4 in H2, 350 sccm) were added to the chamber at 3 Torr and 725° C. Also, hydrogen chloride (250 sccm) and diborane (1% in H2, 125 sccm) were delivered to the chamber. The substrate was maintained at 725° C. Deposition was conducted for about 5 minutes to form a 500 Å SiGe film with a germanium concentration of about 30 at % and the boron concentration of about 1.8×1020 cm−3. The substrate was removed from the process chamber and exposed to the ambient air. The substrate was loaded into a second deposition chamber (Epi Centura® chamber) and heated to 800° C. The substrate was exposed to a process gas containing silane (100 sccm) and hydrogen chloride (250 sccm) for about 10 minutes to selectively deposit a Si film on the SiGe film.

Example 3

SiC/Si Stack:

A substrate, Si<100>, (e.g., 300 mm OD) was employed to investigate selective, monocrystalline film growth by CVD. A dielectric feature existed on the surface of the wafer. The wafer was prepared by subjecting to a 1% HF dip for 45 seconds. The wafer was loaded into the deposition chamber (Epi Centura® chamber) and baked in a hydrogen atmosphere at 800° C. for 60 seconds to remove native oxide. A flow of carrier gas, hydrogen, was directed towards the substrate and the source compounds were added to the carrier flow. Dichlorosilane (100 sccm) and methylsilane (1% CH3SiH3 in H2, 100 sccm) were added to the chamber at 3 Torr and 725° C. Also, hydrogen chloride (160 sccm) and diborane (1% in H2, 150 sccm) were delivered to the chamber. The substrate was maintained at 725° C. Deposition was conducted for about 5 minutes to form a 500 Å SiC film with a carbon concentration of about 1.25 at % and the boron concentration of about 1.0×1020 cm−3. The substrate was removed from the process chamber and exposed to the ambient air. The substrate was loaded into a second deposition chamber (Epi Centura® chamber) and heated to 800° C. The substrate was exposed to a process gas containing silane (100 sccm) and hydrogen chloride (250 sccm) for about 10 minutes to selectively deposit a Si film on the SiC film.

Example 4

Graded-SiC/Si Stack:

A substrate, Si<100>, (e.g., 300 mm OD) was employed to investigate selective, monocrystalline film growth by CVD. A dielectric feature existed on the surface of the wafer. The wafer was prepared by subjecting to a 1% HF dip for 45 seconds. The wafer was loaded into the deposition chamber (Epi Centura® chamber) and baked in a hydrogen atmosphere at 800° C. for 60 seconds to remove native oxide. A first SiC film was deposited by directing a hydrogen carrier gas towards the substrate and the source compounds were added to the carrier flow. Dichlorosilane (100 sccm) and methylsilane (1% CH3SiH3 in H2, 80 sccm) were added to the chamber at 3 Torr and 725° C. Also, hydrogen chloride (160 sccm) and diborane (1% in H2, 100 sccm) were delivered to the chamber. The substrate was maintained at 725° C. Deposition was conducted for about 2 minutes to form a 100 Å SiGe film with a carbon concentration of 1.25 at % and the boron concentration of about 5×1019 cm−3. A second SiC film was deposited to the first SiC film to form a graded-SiC film. Dichlorosilane (100 sccm) and methylsilane (1% CH3SiH3 in H2, 350 sccm) were added to the chamber at 3 Torr and 725° C. Also, hydrogen chloride (250 sccm) and diborane (1% in H2, 150 sccm) were delivered to the chamber. The substrate was maintained at 725° C. Deposition was conducted for 5 minutes to form a 500 Å SiC film with a carbon concentration of 1.75 at % and the boron concentration of about 1.8×1020 cm−3. The substrate was removed from the process chamber and exposed to the ambient air. The substrate was loaded into a second deposition chamber (Epi Centura® chamber) and heated to 800° C. The substrate was exposed to a process gas containing silane (100 sccm) and hydrogen chloride (250 sccm) for about 10 minutes to selectively deposit a Si film on the SiC film.

Example 5

SiGeC/Si Stack:

A substrate, Si<100>, (e.g., 300 mm OD) was employed to investigate selective, monocrystalline film growth by CVD. A dielectric feature existed on the surface of the wafer. The wafer was prepared by subjecting to a 1% HF dip for 45 seconds. The wafer was loaded into the deposition chamber (Epi Centura® chamber) and baked in a hydrogen atmosphere at 800° C. for 60 seconds to remove native oxide. A flow of carrier gas, hydrogen, was directed towards the substrate and the source compounds were added to the carrier flow. Dichlorosilane (100 sccm), germane (1% GeH4 in H2, 190 sccm) and methylsilane (1% CH3SiH3 in H2, 100 sccm) were added to the chamber at 3 Torr and 725° C. Also, hydrogen chloride (220 sccm) and diborane (1% in H2, 150 sccm) were delivered to the chamber. The substrate was maintained at 725° C. Deposition was conducted for about 5 minutes to form a 500 Å SiGeC film with a germanium concentration of about 20 at % a carbon concentration of about 1.5 at % and the boron concentration of about 1.0×1020 cm−3. The substrate was removed from the process chamber and exposed to the ambient air. The substrate was loaded into a second deposition chamber (Epi Centura® chamber) and heated to 800° C. The substrate was exposed to a process gas containing silane (100 sccm) and hydrogen chloride (250 sccm) for about 10 minutes to selectively deposit a Si film on the SiGeC film.

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (21)

1. A method for forming a silicon-based material on a substrate having dielectric materials and source and drains regions thereon within a process chamber, comprising:
exposing the substrate to a first process gas comprising dichlorosilane, a germanium source, a first etchant and a carrier gas to deposit a first silicon-containing layer thereon, wherein the first silicon-containing layer is selectively deposited on the source and drain regions of the substrate while the first silicon-containing layer is etched away on the surface of the dielectric materials of the substrate; and then
exposing the substrate to a second process gas comprising silane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate.
2. The method of claim 1, wherein the first process gas comprises:
the dichlorosilane at a flow rate within a range from about 50 sccm to about 200 sccm;
germane at a flow rate within a range from about 0.5 sccm to about 5 sccm;
hydrogen chloride at a flow rate within a range from about 30 sccm to about 500 sccm; and
hydrogen at a flow rate within a range from about 10 slm to about 30 slm.
3. The method of claim 2, wherein the process chamber is pressurized to a pressure within a range from about 1 Torr to about 10 Torr.
4. The method of claim 1, wherein the first silicon-containing layer is a recessed layer and the second silicon-containing layer is an elevated layer within a source/drain feature.
5. The method of claim 2, wherein the first silicon-containing layer comprises a graded germanium concentration.
6. The method of claim 2, wherein the first and second process gases each comprise a dopant precursor independently selected from the group consisting of diborane, arsine, phosphine and derivatives thereof.
7. The method of claim 6, wherein the first and second silicon-containing layers each have a boron concentration independently within a range from about 5×1019 atoms/cm3 to about 2×1020 atoms/cm3.
8. The method of claim 6, wherein the first and second silicon-containing layers each comprise independently a graded dopant concentration.
9. The method of claim 1, wherein the second process gas comprises:
the silane at a flow rate within a range from about 50 sccm to about 200 sccm; and
hydrogen chloride at a flow rate within a range from about 30 sccm to about 500 sccm.
10. The method of claim 9, wherein the second process gas comprises a second germanium source.
11. The method of claim 10, wherein the second silicon-containing layer has a germanium concentration greater than the first silicon-containing layer.
12. The method of claim 6, wherein the second silicon-containing layer has a dopant concentration greater than the first silicon-containing layer.
13. A method for forming a silicon-based material on a substrate having dielectric materials and source and drains regions thereon within a process chamber, comprising:
exposing the substrate to a first process gas comprising dichlorosilane, a germanium source, a carbon source, a first etchant and a carrier gas to deposit a first silicon-containing layer thereon, wherein the first silicon-containing layer is selectively deposited on the source and drain regions of the substrate while the first silicon-containing layer is etched away on the surface of the dielectric materials of the substrate; and then
exposing the substrate to a second process gas comprising silane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate.
14. The method of claim 13, wherein the first silicon-containing layer has interstitial sites within a crystalline lattice and contains about 3 at % or less of carbon within the interstitial sites.
15. The method of claim 14, further comprising annealing the first silicon-containing layer to incorporate at least a portion of the carbon within substitutional sites of the crystalline lattice.
16. The method of claim 15, wherein the carbon source is methylsilane.
17. The method of claim 14, wherein the first silicon-containing layer has a boron concentration greater than 1×1020 atoms/cm3.
18. The method of claim 17, wherein the boron concentration is about 2×1020 atoms/cm3 or higher.
19. The method of claim 14, wherein the second silicon-containing layer has a boron concentration greater than 1×1020 atoms/cm3.
20. The method of claim 19, wherein the boron concentration is about 2×1020 atoms/cm3 or higher.
21. A method for forming a silicon-based material on a substrate having dielectric materials and source and drains regions thereon within a process chamber, comprising:
exposing the substrate to a first process gas comprising dichlorosilane, a germanium source, a carbon source, a first etchant and a carrier gas to deposit a first silicon-containing layer containing interstitial sites within a crystalline lattice and about 3 at % or less of carbon within the interstitial sites, wherein the first silicon-containing layer is selectively deposited on the source and drain regions of the substrate while the first silicon-containing layer is etched away on the surface of the dielectric materials of the substrate;
exposing the substrate to a second process gas comprising silane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate; and then
annealing the first silicon-containing layer to incorporate at least a portion of the carbon within substitutional sites of the crystalline lattice.
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Cited By (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050170594A1 (en) * 2003-03-04 2005-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof
US20060046440A1 (en) * 2004-09-01 2006-03-02 Nirmal Ramaswamy Methods of forming layers comprising epitaxial silicon
US20060046394A1 (en) * 2004-09-01 2006-03-02 Nirmal Ramaswamy Forming a vertical transistor
US20060051941A1 (en) * 2004-09-01 2006-03-09 Micron Technology, Inc. Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors
US20060105559A1 (en) * 2004-11-15 2006-05-18 International Business Machines Corporation Ultrathin buried insulators in Si or Si-containing material
US20060258131A1 (en) * 2004-09-01 2006-11-16 Nirmal Ramaswamy Integrated circuitry
US20070066023A1 (en) * 2005-09-20 2007-03-22 Randhir Thakur Method to form a device on a soi substrate
US20070082451A1 (en) * 2003-10-10 2007-04-12 Samoilov Arkadii V Methods to fabricate mosfet devices using a selective deposition process
US20070170148A1 (en) * 2006-01-20 2007-07-26 Applied Materials, Inc. Methods for in-situ generation of reactive etch and growth specie in film formation processes
US20070190731A1 (en) * 2006-02-14 2007-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Diffusion layer for semiconductor devices
US20070190704A1 (en) * 2004-02-19 2007-08-16 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20070238242A1 (en) * 2006-04-06 2007-10-11 Shyh-Fann Ting Semiconductor structure and fabrication thereof
US20070256627A1 (en) * 2006-05-01 2007-11-08 Yihwan Kim Method of ultra-shallow junction formation using si film alloyed with carbon
US20080131619A1 (en) * 2006-12-01 2008-06-05 Yonah Cho Formation and treatment of epitaxial layer containing silicon and carbon
US20080132039A1 (en) * 2006-12-01 2008-06-05 Yonah Cho Formation and treatment of epitaxial layer containing silicon and carbon
US20080132018A1 (en) * 2006-12-01 2008-06-05 Applied Materials, Inc. Formation and treatment of epitaxial layer containing silicon and carbon
US20080138939A1 (en) * 2006-12-12 2008-06-12 Yihwan Kim Formation of in-situ phosphorus doped epitaxial layer containing silicon and carbon
US20080138955A1 (en) * 2006-12-12 2008-06-12 Zhiyuan Ye Formation of epitaxial layer containing silicon
US20080138964A1 (en) * 2006-12-12 2008-06-12 Zhiyuan Ye Formation of Epitaxial Layer Containing Silicon and Carbon
US20080182397A1 (en) * 2007-01-31 2008-07-31 Applied Materials, Inc. Selective Epitaxy Process Control
US20080182075A1 (en) * 2006-12-12 2008-07-31 Saurabh Chopra Phosphorus Containing Si Epitaxial Layers in N-Type Source/Drain Junctions
US20080179752A1 (en) * 2007-01-26 2008-07-31 Takashi Yamauchi Method of making semiconductor device and semiconductor device
US20080237732A1 (en) * 2007-03-29 2008-10-02 Shinji Mori Semiconductor device and manufacturing method thereof
US20080274626A1 (en) * 2007-05-04 2008-11-06 Frederique Glowacki Method for depositing a high quality silicon dielectric film on a germanium substrate with high quality interface
US20090087967A1 (en) * 2005-11-14 2009-04-02 Todd Michael A Precursors and processes for low temperature selective epitaxial growth
US7517775B2 (en) 2003-10-10 2009-04-14 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US20090117717A1 (en) * 2007-11-05 2009-05-07 Asm America, Inc. Methods of selectively depositing silicon-containing films
US20090152590A1 (en) * 2007-12-13 2009-06-18 International Business Machines Corporation Method and structure for semiconductor devices with silicon-germanium deposits
US20090305474A1 (en) * 2004-06-24 2009-12-10 International Business Machines Corporation Strained-silicon cmos device and method
US20100006024A1 (en) * 2003-03-13 2010-01-14 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US7655543B2 (en) 2007-12-21 2010-02-02 Asm America, Inc. Separate injection of reactive species in selective formation of films
US20100120235A1 (en) * 2008-11-13 2010-05-13 Applied Materials, Inc. Methods for forming silicon germanium layers
US7776698B2 (en) 2007-10-05 2010-08-17 Applied Materials, Inc. Selective formation of silicon carbon epitaxial layer
US20100264470A1 (en) * 2009-04-21 2010-10-21 Applied Materials, Inc. Nmos transistor devices and methods for fabricating same
US20100301350A1 (en) * 2008-01-25 2010-12-02 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
US20100317177A1 (en) * 2003-10-10 2010-12-16 Applied Materials, Inc. Methods for forming silicon germanium layers
US7893433B2 (en) 2001-02-12 2011-02-22 Asm America, Inc. Thin films and methods of making them
US20110062497A1 (en) * 2007-02-27 2011-03-17 Samsung Electronics Co., Ltd. Semiconductor device structure with strain layer and method of fabricating the semiconductor device structure
US7939447B2 (en) 2007-10-26 2011-05-10 Asm America, Inc. Inhibitors for selective deposition of silicon containing films
US20110175140A1 (en) * 2009-12-17 2011-07-21 Applied Materials, Inc. Methods for forming nmos epi layers
US8012859B1 (en) 2010-03-31 2011-09-06 Tokyo Electron Limited Atomic layer deposition of silicon and silicon-containing films
US8013424B2 (en) 2007-08-20 2011-09-06 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US20120003799A1 (en) * 2008-11-20 2012-01-05 Jin-Bum Kim Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers
US8324059B2 (en) 2011-04-25 2012-12-04 United Microelectronics Corp. Method of fabricating a semiconductor structure
US20130011983A1 (en) * 2011-07-07 2013-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. In-Situ Doping of Arsenic for Source and Drain Epitaxy
US8426284B2 (en) 2011-05-11 2013-04-23 United Microelectronics Corp. Manufacturing method for semiconductor structure
US8431460B2 (en) 2011-05-27 2013-04-30 United Microelectronics Corp. Method for fabricating semiconductor device
US8445363B2 (en) 2011-04-21 2013-05-21 United Microelectronics Corp. Method of fabricating an epitaxial layer
US8466502B2 (en) 2011-03-24 2013-06-18 United Microelectronics Corp. Metal-gate CMOS device
US8476169B2 (en) 2011-10-17 2013-07-02 United Microelectronics Corp. Method of making strained silicon channel semiconductor structure
US8481391B2 (en) 2011-05-18 2013-07-09 United Microelectronics Corp. Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure
US8486191B2 (en) 2009-04-07 2013-07-16 Asm America, Inc. Substrate reactor with adjustable injectors for mixing gases within reaction chamber
US20130277685A1 (en) * 2012-04-20 2013-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Soi transistors with improved source/drain structures with enhanced strain
US8575043B2 (en) 2011-07-26 2013-11-05 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8647941B2 (en) 2011-08-17 2014-02-11 United Microelectronics Corp. Method of forming semiconductor device
US8647953B2 (en) 2011-11-17 2014-02-11 United Microelectronics Corp. Method for fabricating first and second epitaxial cap layers
US8664069B2 (en) 2012-04-05 2014-03-04 United Microelectronics Corp. Semiconductor structure and process thereof
US8674433B2 (en) 2011-08-24 2014-03-18 United Microelectronics Corp. Semiconductor process
US8691659B2 (en) 2011-10-26 2014-04-08 United Microelectronics Corp. Method for forming void-free dielectric layer
US8709930B2 (en) 2011-11-25 2014-04-29 United Microelectronics Corp. Semiconductor process
US8710632B2 (en) 2012-09-07 2014-04-29 United Microelectronics Corp. Compound semiconductor epitaxial structure and method for fabricating the same
US8716750B2 (en) 2011-07-25 2014-05-06 United Microelectronics Corp. Semiconductor device having epitaxial structures
US8754448B2 (en) 2011-11-01 2014-06-17 United Microelectronics Corp. Semiconductor device having epitaxial layer
US8753902B1 (en) 2013-03-13 2014-06-17 United Microelectronics Corp. Method of controlling etching process for forming epitaxial structure
US8765546B1 (en) 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8796695B2 (en) 2012-06-22 2014-08-05 United Microelectronics Corp. Multi-gate field-effect transistor and process thereof
US8835243B2 (en) 2012-05-04 2014-09-16 United Microelectronics Corp. Semiconductor process
US8853060B1 (en) 2013-05-27 2014-10-07 United Microelectronics Corp. Epitaxial process
US8866230B2 (en) 2012-04-26 2014-10-21 United Microelectronics Corp. Semiconductor devices
US8895396B1 (en) 2013-07-11 2014-11-25 United Microelectronics Corp. Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures
US8951876B2 (en) 2012-06-20 2015-02-10 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8981487B2 (en) 2013-07-31 2015-03-17 United Microelectronics Corp. Fin-shaped field-effect transistor (FinFET)
US9034705B2 (en) 2013-03-26 2015-05-19 United Microelectronics Corp. Method of forming semiconductor device
US9064893B2 (en) 2013-05-13 2015-06-23 United Microelectronics Corp. Gradient dopant of strained substrate manufacturing method of semiconductor device
US9076652B2 (en) 2013-05-27 2015-07-07 United Microelectronics Corp. Semiconductor process for modifying shape of recess
US9117925B2 (en) 2013-01-31 2015-08-25 United Microelectronics Corp. Epitaxial process
US9127345B2 (en) 2012-03-06 2015-09-08 Asm America, Inc. Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent
US9136348B2 (en) 2012-03-12 2015-09-15 United Microelectronics Corp. Semiconductor structure and fabrication method thereof
US9202914B2 (en) 2012-03-14 2015-12-01 United Microelectronics Corporation Semiconductor device and method for fabricating the same
US9218963B2 (en) 2013-12-19 2015-12-22 Asm Ip Holding B.V. Cyclical deposition of germanium
US9218962B2 (en) * 2011-05-19 2015-12-22 Globalfoundries Inc. Low temperature epitaxy of a semiconductor alloy including silicon and germanium employing a high order silane precursor
US9660049B2 (en) 2011-11-03 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor transistor device with dopant profile
US9923081B1 (en) 2017-04-04 2018-03-20 Applied Materials, Inc. Selective process for source and drain formation

Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7601225B2 (en) * 2002-06-17 2009-10-13 Asm International N.V. System for controlling the sublimation of reactants
US7297641B2 (en) * 2002-07-19 2007-11-20 Asm America, Inc. Method to form ultra high quality silicon-containing compound layers
US7294582B2 (en) * 2002-07-19 2007-11-13 Asm International, N.V. Low temperature silicon compound deposition
US7186630B2 (en) * 2002-08-14 2007-03-06 Asm America, Inc. Deposition of amorphous silicon-containing films
JP5288707B2 (en) * 2003-03-12 2013-09-11 エーエスエム アメリカ インコーポレイテッド Method of reducing the silicon germanium, a planarization and defect density
US7238595B2 (en) * 2003-03-13 2007-07-03 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US7208362B2 (en) * 2003-06-25 2007-04-24 Texas Instruments Incorporated Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel
KR20060056331A (en) * 2003-07-23 2006-05-24 에이에스엠 아메리카, 인코포레이티드 Deposition of sige on silicon-on-insulator structures and bulk substrates
EP1649495A2 (en) * 2003-07-30 2006-04-26 ASM America, Inc. Epitaxial growth of relaxed silicon germanium layers
WO2005017963A3 (en) * 2003-08-04 2005-11-10 Asm Inc Surface preparation prior to deposition on germanium
US7354815B2 (en) * 2003-11-18 2008-04-08 Silicon Genesis Corporation Method for fabricating semiconductor devices using strained silicon bearing material
EP1763893A2 (en) 2004-02-27 2007-03-21 ASM America, Inc. Germanium deposition
JP4874527B2 (en) * 2004-04-01 2012-02-15 トヨタ自動車株式会社 Silicon carbide semiconductor substrate and a manufacturing method thereof
EP1738001A2 (en) * 2004-04-23 2007-01-03 ASM America, Inc. In situ doped epitaxial films
US20050275018A1 (en) * 2004-06-10 2005-12-15 Suresh Venkatesan Semiconductor device with multiple semiconductor layers
US7172933B2 (en) * 2004-06-10 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed polysilicon gate structure for a strained silicon MOSFET device
DE102004031743B4 (en) * 2004-06-30 2006-10-05 Advanced Micro Devices, Inc., Sunnyvale A process for producing an epitaxial layer for increased drain and source regions by removing surface defects of the initial crystal surface
US7629270B2 (en) * 2004-08-27 2009-12-08 Asm America, Inc. Remote plasma activated nitridation
US7253084B2 (en) 2004-09-03 2007-08-07 Asm America, Inc. Deposition from liquid sources
US7179696B2 (en) * 2004-09-17 2007-02-20 Texas Instruments Incorporated Phosphorus activated NMOS using SiC process
US7966969B2 (en) * 2004-09-22 2011-06-28 Asm International N.V. Deposition of TiN films in a batch reactor
US7247535B2 (en) * 2004-09-30 2007-07-24 Texas Instruments Incorporated Source/drain extensions having highly activated and extremely abrupt junctions
US7312128B2 (en) * 2004-12-01 2007-12-25 Applied Materials, Inc. Selective epitaxy process with alternating gas supply
US7479431B2 (en) 2004-12-17 2009-01-20 Intel Corporation Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain
US7704896B2 (en) * 2005-01-21 2010-04-27 Asm International, N.V. Atomic layer deposition of thin films on germanium
US7235492B2 (en) * 2005-01-31 2007-06-26 Applied Materials, Inc. Low temperature etchant for treatment of silicon-containing surfaces
US7438760B2 (en) 2005-02-04 2008-10-21 Asm America, Inc. Methods of making substitutionally carbon-doped crystalline Si-containing materials by chemical vapor deposition
US7348232B2 (en) * 2005-03-01 2008-03-25 Texas Instruments Incorporated Highly activated carbon selective epitaxial process for CMOS
US7629267B2 (en) * 2005-03-07 2009-12-08 Asm International N.V. High stress nitride film and method for formation thereof
KR100663010B1 (en) * 2005-09-23 2006-12-21 동부일렉트로닉스 주식회사 Mos transistor and manufacturing method thereof
US7439558B2 (en) * 2005-11-04 2008-10-21 Atmel Corporation Method and system for controlled oxygen incorporation in compound semiconductor films for device performance enhancement
US7939413B2 (en) * 2005-12-08 2011-05-10 Samsung Electronics Co., Ltd. Embedded stressor structure and process
US7422950B2 (en) * 2005-12-14 2008-09-09 Intel Corporation Strained silicon MOS device with box layer between the source and drain regions
US7718500B2 (en) * 2005-12-16 2010-05-18 Chartered Semiconductor Manufacturing, Ltd Formation of raised source/drain structures in NFET with embedded SiGe in PFET
WO2007075369B1 (en) * 2005-12-16 2007-08-23 Asm Inc Low temperature doped silicon layer formation
WO2007078802A3 (en) * 2005-12-22 2008-01-24 Asm Inc Epitaxial deposition of doped semiconductor materials
US7525160B2 (en) * 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
US8900980B2 (en) * 2006-01-20 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Defect-free SiGe source/drain formation by epitaxy-free process
DE102006009225B4 (en) * 2006-02-28 2009-07-16 Advanced Micro Devices, Inc., Sunnyvale Production of Silizidoberflächen for silicon / carbon source / drain regions
US7901968B2 (en) * 2006-03-23 2011-03-08 Asm America, Inc. Heteroepitaxial deposition over an oxidized surface
US20070286956A1 (en) * 2006-04-07 2007-12-13 Applied Materials, Inc. Cluster tool for epitaxial film formation
FR2900277B1 (en) 2006-04-19 2008-07-11 St Microelectronics Sa A method of forming a monocrystalline silicon portion has
FR2900275A1 (en) * 2006-04-19 2007-10-26 St Microelectronics Sa Forming a silicon based monocrystalline portion on a first zone surface of a substrate in which a silicon based monocrystalline material belonging to the substrate is initially exposed and on outside of a second zone of the substrate
JP4345774B2 (en) * 2006-04-26 2009-10-14 ソニー株式会社 A method of manufacturing a semiconductor device
JP5130648B2 (en) * 2006-04-27 2013-01-30 ソニー株式会社 Method of manufacturing a semiconductor device
US8278176B2 (en) * 2006-06-07 2012-10-02 Asm America, Inc. Selective epitaxial formation of semiconductor films
US7691757B2 (en) 2006-06-22 2010-04-06 Asm International N.V. Deposition of complex nitride films
US7648853B2 (en) 2006-07-11 2010-01-19 Asm America, Inc. Dual channel heterostructure
JP5076388B2 (en) 2006-07-28 2012-11-21 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
US7494884B2 (en) * 2006-10-05 2009-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. SiGe selective growth without a hard mask
JP5181466B2 (en) * 2006-11-16 2013-04-10 ソニー株式会社 Method of manufacturing a semiconductor device
US8217423B2 (en) 2007-01-04 2012-07-10 International Business Machines Corporation Structure and method for mobility enhanced MOSFETs with unalloyed silicide
US7544997B2 (en) * 2007-02-16 2009-06-09 Freescale Semiconductor, Inc. Multi-layer source/drain stressor
US20080233722A1 (en) * 2007-03-23 2008-09-25 United Microelectronics Corp. Method of forming selective area compound semiconductor epitaxial layer
US7629256B2 (en) * 2007-05-14 2009-12-08 Asm International N.V. In situ silicon and titanium nitride deposition
JP5380794B2 (en) 2007-06-22 2014-01-08 富士通セミコンダクター株式会社 Method of forming a manufacturing method and a semiconductor layer of a semiconductor device
JP2009043938A (en) * 2007-08-09 2009-02-26 Renesas Technology Corp Semiconductor apparatus and manufacturing method therefor
US7759199B2 (en) * 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel
KR101409374B1 (en) 2008-04-10 2014-06-19 삼성전자 주식회사 Fabricating method of a semiconductor integrated circuit device and a semiconductor integrated circuit device fabricated by the same
US8293592B2 (en) * 2008-04-16 2012-10-23 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device and substrate processing apparatus
US20100001317A1 (en) * 2008-07-03 2010-01-07 Yi-Wei Chen Cmos transistor and the method for manufacturing the same
US8343583B2 (en) 2008-07-10 2013-01-01 Asm International N.V. Method for vaporizing non-gaseous precursor in a fluidized bed
US8012876B2 (en) * 2008-12-02 2011-09-06 Asm International N.V. Delivery of vapor precursor from solid source
US7833906B2 (en) 2008-12-11 2010-11-16 Asm International N.V. Titanium silicon nitride deposition
JP5697849B2 (en) * 2009-01-28 2015-04-08 株式会社日立国際電気 Manufacturing method and a substrate processing apparatus of a semiconductor device
JP5287621B2 (en) * 2009-09-10 2013-09-11 富士通セミコンダクター株式会社 Semiconductor device
US8367528B2 (en) * 2009-11-17 2013-02-05 Asm America, Inc. Cyclical epitaxial deposition and etch
US9117905B2 (en) * 2009-12-22 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method for incorporating impurity element in EPI silicon process
CN102468326B (en) * 2010-10-29 2015-01-07 中国科学院微电子研究所 Contact electrode manufacture method and semiconductor device
EP2641264A4 (en) * 2010-11-19 2015-02-18 Commissariat L Énergie Atomique Et Aux Énergies Alternatives Shallow heavily doped semiconductor layer by cyclic selective epitaxial deposition process
EP2461352B1 (en) * 2010-12-06 2013-07-10 Imec Method of manufacturing low resistivity contacts on n-type germanium
US8809170B2 (en) 2011-05-19 2014-08-19 Asm America Inc. High throughput cyclical epitaxial deposition and etch process
CN103177962B (en) * 2011-12-20 2015-12-09 中芯国际集成电路制造(上海)有限公司 The method of forming a transistor
CN103187299B (en) * 2011-12-31 2015-08-05 中芯国际集成电路制造(上海)有限公司 The method of forming a transistor
US20130344688A1 (en) * 2012-06-20 2013-12-26 Zhiyuan Ye Atomic Layer Deposition with Rapid Thermal Treatment
CN103531472B (en) * 2012-07-03 2016-05-11 中芯国际集成电路制造(上海)有限公司 Device and method for preparing one kind of mosfet
JP5488675B2 (en) * 2012-11-14 2014-05-14 ソニー株式会社 A method of manufacturing a semiconductor device
US9224657B2 (en) * 2013-08-06 2015-12-29 Texas Instruments Incorporated Hard mask for source/drain epitaxy control
CN104347512B (en) * 2013-08-07 2017-07-14 中芯国际集成电路制造(上海)有限公司 The method of forming a transistor Cmos
CN105097694A (en) * 2014-05-21 2015-11-25 中芯国际集成电路制造(上海)有限公司 Preparation method of semiconductor device
KR20160011742A (en) 2014-07-22 2016-02-02 삼성전자주식회사 Semiconductor device
CN105448991A (en) * 2014-09-01 2016-03-30 中芯国际集成电路制造(上海)有限公司 Transistor and method of forming same
CN105590852A (en) * 2014-10-21 2016-05-18 上海华力微电子有限公司 Method for decreasing dislocation defects of embedded silicon-germanium epitaxial growth
US9722045B2 (en) * 2015-10-23 2017-08-01 Globalfoundries Inc. Buffer layer for modulating Vt across devices

Citations (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5898917A (en) 1981-12-09 1983-06-13 Seiko Epson Corp Atomic layer epitaxial device
JPS62171999A (en) 1986-01-27 1987-07-28 Nippon Telegr & Teleph Corp <Ntt> Epitaxy of iii-v compound semiconductor
JPS6362313A (en) 1986-09-03 1988-03-18 Fujitsu Ltd Manufacture of semiconductor device
US4834831A (en) 1986-09-08 1989-05-30 Research Development Corporation Of Japan Method for growing single crystal thin films of element semiconductor
JPH01270593A (en) 1988-04-21 1989-10-27 Fujitsu Ltd Method for forming compound semiconductor layer
JPH02172895A (en) 1988-12-22 1990-07-04 Nec Corp Method for growing semiconductor crystal
JPH03286522A (en) 1990-04-03 1991-12-17 Nec Corp Growth method of si crystal
US5112439A (en) 1988-11-30 1992-05-12 Mcnc Method for selectively depositing material on substrates
JPH0547665A (en) 1991-08-12 1993-02-26 Fujitsu Ltd Vapor growth method
JPH05102189A (en) 1991-08-13 1993-04-23 Fujitsu Ltd Formation method of thin film, silicon thin film and formation method of silicon thin-film transistor
US5273930A (en) 1992-09-03 1993-12-28 Motorola, Inc. Method of forming a non-selective silicon-germanium epitaxial film
US5294286A (en) 1984-07-26 1994-03-15 Research Development Corporation Of Japan Process for forming a thin film of silicon
US5372860A (en) 1993-07-06 1994-12-13 Corning Incorporated Silicon device production
US5374570A (en) 1989-03-17 1994-12-20 Fujitsu Limited Method of manufacturing active matrix display device using insulation layer formed by the ale method
US5469806A (en) 1992-08-21 1995-11-28 Nec Corporation Method for epitaxial growth of semiconductor crystal by using halogenide
US5480818A (en) 1992-02-10 1996-01-02 Fujitsu Limited Method for forming a film and method for manufacturing a thin film transistor
US5527733A (en) 1989-07-27 1996-06-18 Seiko Instruments Inc. Impurity doping method with adsorbed diffusion source
US5674304A (en) 1993-10-12 1997-10-07 Semiconductor Energy Laboratory Co., Ltd. Method of heat-treating a glass substrate
US5693139A (en) 1984-07-26 1997-12-02 Research Development Corporation Of Japan Growth of doped semiconductor monolayers
WO1998020524A1 (en) 1996-11-06 1998-05-14 Pacific Solar Pty. Limited Forming a crystalline semiconductor film on a glass substrate
US5796116A (en) 1994-07-27 1998-08-18 Sharp Kabushiki Kaisha Thin-film semiconductor device including a semiconductor film with high field-effect mobility
US5807792A (en) 1996-12-18 1998-09-15 Siemens Aktiengesellschaft Uniform distribution of reactants in a device layer
US5846867A (en) * 1995-12-20 1998-12-08 Sony Corporation Method of producing Si-Ge base heterojunction bipolar device
US5906680A (en) 1986-09-12 1999-05-25 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US6025627A (en) 1998-05-29 2000-02-15 Micron Technology, Inc. Alternate method and structure for improved floating gate tunneling devices
US6042654A (en) 1998-01-13 2000-03-28 Applied Materials, Inc. Method of cleaning CVD cold-wall chamber and exhaust lines
US6159852A (en) 1998-02-13 2000-12-12 Micron Technology, Inc. Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor
JP2001111000A (en) 1999-08-14 2001-04-20 Samsung Electronics Co Ltd Semiconductor element and manufacturing method thereof
US6232196B1 (en) 1998-03-06 2001-05-15 Asm America, Inc. Method of depositing silicon with high step coverage
US6235568B1 (en) * 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication
WO2001041544A2 (en) 1999-12-11 2001-06-14 Asm America, Inc. Deposition of gate stacks including silicon germanium layers
JP2001189312A (en) 1999-10-25 2001-07-10 Motorola Inc Method of manufacturing semiconductor structure having metal oxide interface with silicon
US6284686B1 (en) 1997-06-02 2001-09-04 Osram Sylvania Inc. Lead and arsenic free borosilicate glass and lamp containing same
US6291319B1 (en) 1999-12-17 2001-09-18 Motorola, Inc. Method for fabricating a semiconductor structure having a stable crystalline interface with silicon
US20010024871A1 (en) 1998-04-24 2001-09-27 Fuji Xerox Co. Semiconductor device and method and apparatus for manufacturing semiconductor device
EP1150345A2 (en) 2000-04-28 2001-10-31 Asm Japan K.K. Fluorine-containing materials and processes
US20010045604A1 (en) * 2000-05-25 2001-11-29 Hitachi, Ltd. Semiconductor device and manufacturing method
US20010046567A1 (en) 1998-02-05 2001-11-29 Nobuo Matsuki Siloxan polymer film on semiconductor substrate and method for forming same
US20010055672A1 (en) 2000-02-08 2001-12-27 Todd Michael A. Low dielectric constant materials and processes
US6335280B1 (en) 1997-01-13 2002-01-01 Asm America, Inc. Tungsten silicide deposition process
US6348420B1 (en) 1999-12-23 2002-02-19 Asm America, Inc. Situ dielectric stacks
US6352945B1 (en) 1998-02-05 2002-03-05 Asm Japan K.K. Silicone polymer insulation film on semiconductor substrate and method for forming the film
US6358829B2 (en) 1998-09-17 2002-03-19 Samsung Electronics Company., Ltd. Semiconductor device fabrication method using an interface control layer to improve a metal interconnection layer
US6383955B1 (en) 1998-02-05 2002-05-07 Asm Japan K.K. Silicone polymer insulation film on semiconductor substrate and method for forming the film
US20020090818A1 (en) 1999-09-17 2002-07-11 Anna Lena Thilderkvist Apparatus and method for surface finishing a silicon film
US20020093042A1 (en) 2001-01-15 2002-07-18 Sang-Jeong Oh Integrated circuit devices that utilize doped Poly-Si1-xGex conductive plugs as interconnects and methods of fabricating the same
WO2002065525A1 (en) 2001-02-12 2002-08-22 Asm America, Inc. Integration of high k gate dielectric
WO2002065516A2 (en) 2001-02-12 2002-08-22 Asm America, Inc. Improved process for deposition of semiconductor films
US6451119B2 (en) 1999-03-11 2002-09-17 Genus, Inc. Apparatus and concept for minimizing parasitic chemical vapor deposition during atomic layer deposition
US20020145168A1 (en) 2001-02-05 2002-10-10 International Business Machines Corporation Method for forming dielectric stack without interfacial layer
WO2002097864A2 (en) 2001-05-30 2002-12-05 Asm America, Inc Low temperature load and bake
US6492711B1 (en) * 1999-06-22 2002-12-10 Matsushita Electric Industrial Co., Ltd. Heterojunction bipolar transistor and method for fabricating the same
US20030189208A1 (en) 2002-04-05 2003-10-09 Kam Law Deposition of silicon layers for active matrix liquid crystal display (AMLCD) applications
US20040033674A1 (en) 2002-08-14 2004-02-19 Todd Michael A. Deposition of amorphous silicon-containing films
US6797558B2 (en) 2001-04-24 2004-09-28 Micron Technology, Inc. Methods of forming a capacitor with substantially selective deposite of polysilicon on a substantially crystalline capacitor dielectric layer
US20040226911A1 (en) 2003-04-24 2004-11-18 David Dutton Low-temperature etching environment
US20040253776A1 (en) 2003-06-12 2004-12-16 Thomas Hoffmann Gate-induced strain for MOS performance improvement
US20050079691A1 (en) 2003-10-10 2005-04-14 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3761918B2 (en) * 1994-09-13 2006-03-29 株式会社東芝 A method of manufacturing a semiconductor device
EP0799495A4 (en) * 1994-11-10 1999-11-03 Lawrence Semiconductor Researc Silicon-germanium-carbon compositions and processes thereof
JPH10189459A (en) * 1996-12-27 1998-07-21 Sony Corp Forming method for boron-doped silicon-germanium mixed crystal
WO1999041742A1 (en) * 1998-02-13 1999-08-19 Samsung Advanced Institute Of Technology Optical recording medium based on thin recording layers
JP3809035B2 (en) * 1998-06-29 2006-08-16 株式会社東芝 Mis-type transistor and a method of manufacturing the same
DE19845427A1 (en) * 1998-10-02 2000-04-06 Basf Ag Fluid applicator, for applying a polymer or adhesive dispersion onto a moving surface, has a separation element between initial and main fluid supply chambers for defining a separation gap with the surface
EP1147552A1 (en) * 1998-11-12 2001-10-24 Intel Corporation Field effect transistor structure with abrupt source/drain junctions
JP2001024194A (en) * 1999-05-06 2001-01-26 Toshiba Corp Semiconductor device and manufacture thereof
WO2001071787A1 (en) 2000-03-17 2001-09-27 Varian Semiconductor Equipment Associates, Inc. Method of forming ultrashallow junctions by laser annealing and rapid thermal annealing
JP4882141B2 (en) * 2000-08-16 2012-02-22 富士通株式会社 Heterojunction bipolar transistor
JP2002198525A (en) 2000-12-27 2002-07-12 Toshiba Corp Semiconductor device and its manufacturing method
JP3890202B2 (en) 2001-03-28 2007-03-07 株式会社日立製作所 A method of manufacturing a semiconductor device
US6905542B2 (en) 2001-05-24 2005-06-14 Arkadii V. Samoilov Waveguides such as SiGeC waveguides and method of fabricating the same
JP4277467B2 (en) * 2001-10-29 2009-06-10 株式会社Sumco Semiconductor substrate and a field effect transistor and a method for their preparation
JP2004095639A (en) * 2002-08-29 2004-03-25 Fujitsu Ltd Semiconductor device and its manufacturing method
US7005372B2 (en) * 2003-01-21 2006-02-28 Novellus Systems, Inc. Deposition of tungsten nitride
US6998305B2 (en) 2003-01-24 2006-02-14 Asm America, Inc. Enhanced selectivity for epitaxial deposition
US20050007692A1 (en) * 2003-06-26 2005-01-13 Spectra Logic Corporation Magazine-Based Data Cartridge Library
US6855963B1 (en) 2003-08-29 2005-02-15 International Business Machines Corporation Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate
US7132338B2 (en) 2003-10-10 2006-11-07 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process
US7045432B2 (en) 2004-02-04 2006-05-16 Freescale Semiconductor, Inc. Method for forming a semiconductor device with local semiconductor-on-insulator (SOI)

Patent Citations (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5898917A (en) 1981-12-09 1983-06-13 Seiko Epson Corp Atomic layer epitaxial device
US5693139A (en) 1984-07-26 1997-12-02 Research Development Corporation Of Japan Growth of doped semiconductor monolayers
US5294286A (en) 1984-07-26 1994-03-15 Research Development Corporation Of Japan Process for forming a thin film of silicon
JPS62171999A (en) 1986-01-27 1987-07-28 Nippon Telegr & Teleph Corp <Ntt> Epitaxy of iii-v compound semiconductor
JPS6362313A (en) 1986-09-03 1988-03-18 Fujitsu Ltd Manufacture of semiconductor device
US4834831A (en) 1986-09-08 1989-05-30 Research Development Corporation Of Japan Method for growing single crystal thin films of element semiconductor
US5906680A (en) 1986-09-12 1999-05-25 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
JPH01270593A (en) 1988-04-21 1989-10-27 Fujitsu Ltd Method for forming compound semiconductor layer
US5112439A (en) 1988-11-30 1992-05-12 Mcnc Method for selectively depositing material on substrates
JPH02172895A (en) 1988-12-22 1990-07-04 Nec Corp Method for growing semiconductor crystal
US5374570A (en) 1989-03-17 1994-12-20 Fujitsu Limited Method of manufacturing active matrix display device using insulation layer formed by the ale method
US5527733A (en) 1989-07-27 1996-06-18 Seiko Instruments Inc. Impurity doping method with adsorbed diffusion source
JPH03286522A (en) 1990-04-03 1991-12-17 Nec Corp Growth method of si crystal
JPH0547665A (en) 1991-08-12 1993-02-26 Fujitsu Ltd Vapor growth method
JPH05102189A (en) 1991-08-13 1993-04-23 Fujitsu Ltd Formation method of thin film, silicon thin film and formation method of silicon thin-film transistor
US5480818A (en) 1992-02-10 1996-01-02 Fujitsu Limited Method for forming a film and method for manufacturing a thin film transistor
US5469806A (en) 1992-08-21 1995-11-28 Nec Corporation Method for epitaxial growth of semiconductor crystal by using halogenide
US5273930A (en) 1992-09-03 1993-12-28 Motorola, Inc. Method of forming a non-selective silicon-germanium epitaxial film
US5372860A (en) 1993-07-06 1994-12-13 Corning Incorporated Silicon device production
US5674304A (en) 1993-10-12 1997-10-07 Semiconductor Energy Laboratory Co., Ltd. Method of heat-treating a glass substrate
US5796116A (en) 1994-07-27 1998-08-18 Sharp Kabushiki Kaisha Thin-film semiconductor device including a semiconductor film with high field-effect mobility
US5846867A (en) * 1995-12-20 1998-12-08 Sony Corporation Method of producing Si-Ge base heterojunction bipolar device
WO1998020524A1 (en) 1996-11-06 1998-05-14 Pacific Solar Pty. Limited Forming a crystalline semiconductor film on a glass substrate
US5807792A (en) 1996-12-18 1998-09-15 Siemens Aktiengesellschaft Uniform distribution of reactants in a device layer
US6335280B1 (en) 1997-01-13 2002-01-01 Asm America, Inc. Tungsten silicide deposition process
US6284686B1 (en) 1997-06-02 2001-09-04 Osram Sylvania Inc. Lead and arsenic free borosilicate glass and lamp containing same
US6042654A (en) 1998-01-13 2000-03-28 Applied Materials, Inc. Method of cleaning CVD cold-wall chamber and exhaust lines
US20010046567A1 (en) 1998-02-05 2001-11-29 Nobuo Matsuki Siloxan polymer film on semiconductor substrate and method for forming same
US6352945B1 (en) 1998-02-05 2002-03-05 Asm Japan K.K. Silicone polymer insulation film on semiconductor substrate and method for forming the film
US6410463B1 (en) 1998-02-05 2002-06-25 Asm Japan K.K. Method for forming film with low dielectric constant on semiconductor substrate
US6383955B1 (en) 1998-02-05 2002-05-07 Asm Japan K.K. Silicone polymer insulation film on semiconductor substrate and method for forming the film
US6559520B2 (en) 1998-02-05 2003-05-06 Asm Japan K.K. Siloxan polymer film on semiconductor substrate
US6159852A (en) 1998-02-13 2000-12-12 Micron Technology, Inc. Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor
US20010020712A1 (en) 1998-03-06 2001-09-13 Ivo Raaijmakers Method of depositing silicon with high step coverage
US6232196B1 (en) 1998-03-06 2001-05-15 Asm America, Inc. Method of depositing silicon with high step coverage
US20010024871A1 (en) 1998-04-24 2001-09-27 Fuji Xerox Co. Semiconductor device and method and apparatus for manufacturing semiconductor device
US6025627A (en) 1998-05-29 2000-02-15 Micron Technology, Inc. Alternate method and structure for improved floating gate tunneling devices
US6358829B2 (en) 1998-09-17 2002-03-19 Samsung Electronics Company., Ltd. Semiconductor device fabrication method using an interface control layer to improve a metal interconnection layer
US6235568B1 (en) * 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication
US6451119B2 (en) 1999-03-11 2002-09-17 Genus, Inc. Apparatus and concept for minimizing parasitic chemical vapor deposition during atomic layer deposition
US6492711B1 (en) * 1999-06-22 2002-12-10 Matsushita Electric Industrial Co., Ltd. Heterojunction bipolar transistor and method for fabricating the same
JP2001111000A (en) 1999-08-14 2001-04-20 Samsung Electronics Co Ltd Semiconductor element and manufacturing method thereof
US6489241B1 (en) 1999-09-17 2002-12-03 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film
US6562720B2 (en) 1999-09-17 2003-05-13 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film
US20020090818A1 (en) 1999-09-17 2002-07-11 Anna Lena Thilderkvist Apparatus and method for surface finishing a silicon film
JP2001189312A (en) 1999-10-25 2001-07-10 Motorola Inc Method of manufacturing semiconductor structure having metal oxide interface with silicon
WO2001041544A2 (en) 1999-12-11 2001-06-14 Asm America, Inc. Deposition of gate stacks including silicon germanium layers
US6291319B1 (en) 1999-12-17 2001-09-18 Motorola, Inc. Method for fabricating a semiconductor structure having a stable crystalline interface with silicon
US6348420B1 (en) 1999-12-23 2002-02-19 Asm America, Inc. Situ dielectric stacks
US6544900B2 (en) 1999-12-23 2003-04-08 Asm America, Inc. In situ dielectric stacks
US20010055672A1 (en) 2000-02-08 2001-12-27 Todd Michael A. Low dielectric constant materials and processes
EP1150345A2 (en) 2000-04-28 2001-10-31 Asm Japan K.K. Fluorine-containing materials and processes
US6458718B1 (en) 2000-04-28 2002-10-01 Asm Japan K.K. Fluorine-containing materials and processes
US20010045604A1 (en) * 2000-05-25 2001-11-29 Hitachi, Ltd. Semiconductor device and manufacturing method
US20020093042A1 (en) 2001-01-15 2002-07-18 Sang-Jeong Oh Integrated circuit devices that utilize doped Poly-Si1-xGex conductive plugs as interconnects and methods of fabricating the same
US20020145168A1 (en) 2001-02-05 2002-10-10 International Business Machines Corporation Method for forming dielectric stack without interfacial layer
US6821825B2 (en) 2001-02-12 2004-11-23 Asm America, Inc. Process for deposition of semiconductor films
US20020168868A1 (en) 2001-02-12 2002-11-14 Todd Michael A. Deposition Over Mixed Substrates
US20020173113A1 (en) 2001-02-12 2002-11-21 Todd Michael A. Dopant Precursors and Processes
WO2002080244A2 (en) 2001-02-12 2002-10-10 Asm America, Inc. Improved process for deposition of semiconductor films
WO2002065516A2 (en) 2001-02-12 2002-08-22 Asm America, Inc. Improved process for deposition of semiconductor films
WO2002065508A2 (en) 2001-02-12 2002-08-22 Asm America, Inc. Dopant precursors and processes
WO2002065525A1 (en) 2001-02-12 2002-08-22 Asm America, Inc. Integration of high k gate dielectric
US20020197831A1 (en) 2001-02-12 2002-12-26 Todd Michael A. Thin Films and Methods of Making Them
US20030022528A1 (en) 2001-02-12 2003-01-30 Todd Michael A. Improved Process for Deposition of Semiconductor Films
WO2002064853A2 (en) 2001-02-12 2002-08-22 Asm America, Inc. Thin films and methods of making them using trisilane
US20030082300A1 (en) 2001-02-12 2003-05-01 Todd Michael A. Improved Process for Deposition of Semiconductor Films
WO2002065517A2 (en) 2001-02-12 2002-08-22 Asm America, Inc. Deposition method over mixed substrates using trisilane
US20020173130A1 (en) 2001-02-12 2002-11-21 Pomerede Christophe F. Integration of High K Gate Dielectric
US6797558B2 (en) 2001-04-24 2004-09-28 Micron Technology, Inc. Methods of forming a capacitor with substantially selective deposite of polysilicon on a substantially crystalline capacitor dielectric layer
US20030036268A1 (en) 2001-05-30 2003-02-20 Brabant Paul D. Low temperature load and bake
WO2002097864A2 (en) 2001-05-30 2002-12-05 Asm America, Inc Low temperature load and bake
US20030189208A1 (en) 2002-04-05 2003-10-09 Kam Law Deposition of silicon layers for active matrix liquid crystal display (AMLCD) applications
US20040033674A1 (en) 2002-08-14 2004-02-19 Todd Michael A. Deposition of amorphous silicon-containing films
US20040226911A1 (en) 2003-04-24 2004-11-18 David Dutton Low-temperature etching environment
US20040253776A1 (en) 2003-06-12 2004-12-16 Thomas Hoffmann Gate-induced strain for MOS performance improvement
WO2005038890A1 (en) 2003-10-10 2005-04-28 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial sige
US20050079691A1 (en) 2003-10-10 2005-04-14 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe

Non-Patent Citations (13)

* Cited by examiner, † Cited by third party
Title
Article by Kamins et al., entitled "Kinetics of Selective epitaxial deposition Si<SUB>1-x</SUB>Ge<SUB>x</SUB>", American Institute of Physics, Aug. 1992, No. 6, pp. 669-671.
Article by Menon et al., entitled "Loading effect in SiGe layers grown by dichlorosilane-and silane-based epitaxy", American Institute of Physics, Nov. 2001, vol. 90, No. 9, pp. 4805-4809.
Article by Sedgwick et al., entitled "Selective SiGe and heavily as doped Si deposited at low temperature by atmospheric pressure chemical vapor deposition", Journal of Vacuum Science & Technology, May/Jun. 1993, No. 3, pp. 1124-1128.
Article by Uchino et al., entitled "A Raised Source/Drain Technology Using In-situ P-doped SiGe and B-doped Si for 0.1- mum CMOS ULSIs", IEDM, Dec. 1997, Technical Digest, pp. 479-482.
Choi, et al. "Stability of TiB<SUB>2 </SUB>as a Diffusion Barrier on Silicon," J. Electrochem. Soc., vol. 138, No. 10, Oct. 1991.
International Search Report dated Mar. 30, 2006 for International Application No. PCT/US2005/016160 (APPM/008539PC02).
International Search Report mailed Feb. 22, 2005 for PCT/US2004/030872 (AMAT/8539-PCT).
Invitation to Pay Additional Fees and Partial International Search Report for PCT/US2005/016160.
Jeong, et al. "Growth and Characterization of Aluminum Oxide Al<SUB>2</SUB>O<SUB>3 </SUB>Thin Films by Plasma-assisted Atomic Layer Controlled Deposition," J. Korean Inst. Met. Mater., vol. 38, No. 10, Oct. 2000.
Jeong, et al. "Plasma-assisted Atomic Layer Growth of High-Quality Aluminum Oxide Thin Films," Jpn. J. Appl. Phys. 1, Regul. Pap. Short Notes, vol. 40, No. 1, Jan. 2001.
Lee, et al. "Cyclic Technique for the Enhancement of Highly Oriented Diamond Film Growth," Thin Solid Films 303 (1997) 264-269.
Paranjpe, et al. "Atomic Layer Deposition of AlO<SUB>x </SUB>for Thin Film Head Gap Applications," J. Electrochem. Soc., vol. 148, No. 9, Sep. 2001.
Written Opinion of the International Searching Authority dated Mar. 30, 2006 for International Application No. PCT/US2005/016160 (APPM/008539PC02).

Cited By (139)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7893433B2 (en) 2001-02-12 2011-02-22 Asm America, Inc. Thin films and methods of making them
US8062946B2 (en) * 2003-03-04 2011-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Strained channel transistor structure with lattice-mismatched zone and fabrication method thereof
US20050170594A1 (en) * 2003-03-04 2005-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof
US20100006024A1 (en) * 2003-03-13 2010-01-14 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US8530340B2 (en) 2003-03-13 2013-09-10 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US20100317177A1 (en) * 2003-10-10 2010-12-16 Applied Materials, Inc. Methods for forming silicon germanium layers
US8501594B2 (en) * 2003-10-10 2013-08-06 Applied Materials, Inc. Methods for forming silicon germanium layers
US20070082451A1 (en) * 2003-10-10 2007-04-12 Samoilov Arkadii V Methods to fabricate mosfet devices using a selective deposition process
US7737007B2 (en) 2003-10-10 2010-06-15 Applied Materials, Inc. Methods to fabricate MOSFET devices using a selective deposition process
US7517775B2 (en) 2003-10-10 2009-04-14 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US7439142B2 (en) 2003-10-10 2008-10-21 Applied Materials, Inc. Methods to fabricate MOSFET devices using a selective deposition process
US20070190704A1 (en) * 2004-02-19 2007-08-16 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US7435655B2 (en) * 2004-02-19 2008-10-14 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20090305474A1 (en) * 2004-06-24 2009-12-10 International Business Machines Corporation Strained-silicon cmos device and method
US20060046394A1 (en) * 2004-09-01 2006-03-02 Nirmal Ramaswamy Forming a vertical transistor
US7807535B2 (en) 2004-09-01 2010-10-05 Micron Technology, Inc. Methods of forming layers comprising epitaxial silicon
US7768036B2 (en) * 2004-09-01 2010-08-03 Micron Technology, Inc. Integrated circuitry
US20060051941A1 (en) * 2004-09-01 2006-03-09 Micron Technology, Inc. Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors
US8673706B2 (en) 2004-09-01 2014-03-18 Micron Technology, Inc. Methods of forming layers comprising epitaxial silicon
US7709326B2 (en) 2004-09-01 2010-05-04 Micron Technology, Inc. Methods of forming layers comprising epitaxial silicon
US20060046440A1 (en) * 2004-09-01 2006-03-02 Nirmal Ramaswamy Methods of forming layers comprising epitaxial silicon
US20060258131A1 (en) * 2004-09-01 2006-11-16 Nirmal Ramaswamy Integrated circuitry
US20090179231A1 (en) * 2004-09-01 2009-07-16 Nirmal Ramaswamy Integrated Circuitry
US7528424B2 (en) * 2004-09-01 2009-05-05 Micron Technology, Inc. Integrated circuitry
US7517758B2 (en) 2004-09-01 2009-04-14 Micron Technology, Inc. Method of forming a vertical transistor
US20070166962A1 (en) * 2004-09-01 2007-07-19 Nirmal Ramaswamy Methods of forming layers comprising epitaxial silicon
US20100258857A1 (en) * 2004-09-01 2010-10-14 Nirmal Ramaswamy Method of Forming a Layer Comprising Epitaxial Silicon, and a Field Effect Transistor
US7531395B2 (en) 2004-09-01 2009-05-12 Micron Technology, Inc. Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors
US20060105559A1 (en) * 2004-11-15 2006-05-18 International Business Machines Corporation Ultrathin buried insulators in Si or Si-containing material
US20070066023A1 (en) * 2005-09-20 2007-03-22 Randhir Thakur Method to form a device on a soi substrate
US20090087967A1 (en) * 2005-11-14 2009-04-02 Todd Michael A Precursors and processes for low temperature selective epitaxial growth
US20070170148A1 (en) * 2006-01-20 2007-07-26 Applied Materials, Inc. Methods for in-situ generation of reactive etch and growth specie in film formation processes
US7709391B2 (en) 2006-01-20 2010-05-04 Applied Materials, Inc. Methods for in-situ generation of reactive etch and growth specie in film formation processes
US7608515B2 (en) * 2006-02-14 2009-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Diffusion layer for stressed semiconductor devices
US20070190731A1 (en) * 2006-02-14 2007-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Diffusion layer for semiconductor devices
US7410875B2 (en) * 2006-04-06 2008-08-12 United Microelectronics Corp. Semiconductor structure and fabrication thereof
US7453120B2 (en) * 2006-04-06 2008-11-18 Unitd Microelectronics Corp. Semiconductor structure
US20070238242A1 (en) * 2006-04-06 2007-10-11 Shyh-Fann Ting Semiconductor structure and fabrication thereof
US20070256627A1 (en) * 2006-05-01 2007-11-08 Yihwan Kim Method of ultra-shallow junction formation using si film alloyed with carbon
US7732269B2 (en) 2006-05-01 2010-06-08 Applied Materials, Inc. Method of ultra-shallow junction formation using Si film alloyed with carbon
US20080131619A1 (en) * 2006-12-01 2008-06-05 Yonah Cho Formation and treatment of epitaxial layer containing silicon and carbon
US7741200B2 (en) 2006-12-01 2010-06-22 Applied Materials, Inc. Formation and treatment of epitaxial layer containing silicon and carbon
US20080132018A1 (en) * 2006-12-01 2008-06-05 Applied Materials, Inc. Formation and treatment of epitaxial layer containing silicon and carbon
US7837790B2 (en) 2006-12-01 2010-11-23 Applied Materials, Inc. Formation and treatment of epitaxial layer containing silicon and carbon
US20080132039A1 (en) * 2006-12-01 2008-06-05 Yonah Cho Formation and treatment of epitaxial layer containing silicon and carbon
US20080138955A1 (en) * 2006-12-12 2008-06-12 Zhiyuan Ye Formation of epitaxial layer containing silicon
US20080182075A1 (en) * 2006-12-12 2008-07-31 Saurabh Chopra Phosphorus Containing Si Epitaxial Layers in N-Type Source/Drain Junctions
US20080138964A1 (en) * 2006-12-12 2008-06-12 Zhiyuan Ye Formation of Epitaxial Layer Containing Silicon and Carbon
US20080138939A1 (en) * 2006-12-12 2008-06-12 Yihwan Kim Formation of in-situ phosphorus doped epitaxial layer containing silicon and carbon
US7897495B2 (en) 2006-12-12 2011-03-01 Applied Materials, Inc. Formation of epitaxial layer containing silicon and carbon
US8394196B2 (en) * 2006-12-12 2013-03-12 Applied Materials, Inc. Formation of in-situ phosphorus doped epitaxial layer containing silicon and carbon
US7960236B2 (en) 2006-12-12 2011-06-14 Applied Materials, Inc. Phosphorus containing Si epitaxial layers in N-type source/drain junctions
US7807538B2 (en) * 2007-01-26 2010-10-05 Kabushiki Kaisha Toshiba Method of forming a silicide layer while applying a compressive or tensile strain to impurity layers
US20080179752A1 (en) * 2007-01-26 2008-07-31 Takashi Yamauchi Method of making semiconductor device and semiconductor device
US20080182397A1 (en) * 2007-01-31 2008-07-31 Applied Materials, Inc. Selective Epitaxy Process Control
US9064960B2 (en) 2007-01-31 2015-06-23 Applied Materials, Inc. Selective epitaxy process control
US20110062497A1 (en) * 2007-02-27 2011-03-17 Samsung Electronics Co., Ltd. Semiconductor device structure with strain layer and method of fabricating the semiconductor device structure
US8350354B2 (en) * 2007-02-27 2013-01-08 Samsung Electronics Co., Ltd. Semiconductor device structure with strain layer
USRE45462E1 (en) 2007-03-29 2015-04-14 Kabushiki Kaisha Toshiba Semiconductor device
US20080237732A1 (en) * 2007-03-29 2008-10-02 Shinji Mori Semiconductor device and manufacturing method thereof
US8013398B2 (en) 2007-03-29 2011-09-06 Kabushiki Kaisha Toshiba Semiconductor device
US8124472B2 (en) 2007-03-29 2012-02-28 Kabushiki Kaisha Toshiba Manufacturing method of a semiconductor device
US20080274626A1 (en) * 2007-05-04 2008-11-06 Frederique Glowacki Method for depositing a high quality silicon dielectric film on a germanium substrate with high quality interface
US8013424B2 (en) 2007-08-20 2011-09-06 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US7776698B2 (en) 2007-10-05 2010-08-17 Applied Materials, Inc. Selective formation of silicon carbon epitaxial layer
US7939447B2 (en) 2007-10-26 2011-05-10 Asm America, Inc. Inhibitors for selective deposition of silicon containing films
US20090117717A1 (en) * 2007-11-05 2009-05-07 Asm America, Inc. Methods of selectively depositing silicon-containing films
US7772097B2 (en) * 2007-11-05 2010-08-10 Asm America, Inc. Methods of selectively depositing silicon-containing films
US20090152590A1 (en) * 2007-12-13 2009-06-18 International Business Machines Corporation Method and structure for semiconductor devices with silicon-germanium deposits
US7897491B2 (en) 2007-12-21 2011-03-01 Asm America, Inc. Separate injection of reactive species in selective formation of films
US7655543B2 (en) 2007-12-21 2010-02-02 Asm America, Inc. Separate injection of reactive species in selective formation of films
US8338831B2 (en) 2008-01-25 2012-12-25 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
US8586438B2 (en) 2008-01-25 2013-11-19 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
US20100301350A1 (en) * 2008-01-25 2010-12-02 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
US20100120235A1 (en) * 2008-11-13 2010-05-13 Applied Materials, Inc. Methods for forming silicon germanium layers
US20120003799A1 (en) * 2008-11-20 2012-01-05 Jin-Bum Kim Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers
US8324043B2 (en) * 2008-11-20 2012-12-04 Samsung Electronics Co., Ltd. Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers
US8486191B2 (en) 2009-04-07 2013-07-16 Asm America, Inc. Substrate reactor with adjustable injectors for mixing gases within reaction chamber
US8330225B2 (en) 2009-04-21 2012-12-11 Applied Materials, Inc. NMOS transistor devices and methods for fabricating same
US7994015B2 (en) 2009-04-21 2011-08-09 Applied Materials, Inc. NMOS transistor devices and methods for fabricating same
US20100264470A1 (en) * 2009-04-21 2010-10-21 Applied Materials, Inc. Nmos transistor devices and methods for fabricating same
US20110175140A1 (en) * 2009-12-17 2011-07-21 Applied Materials, Inc. Methods for forming nmos epi layers
US8999798B2 (en) 2009-12-17 2015-04-07 Applied Materials, Inc. Methods for forming NMOS EPI layers
US8012859B1 (en) 2010-03-31 2011-09-06 Tokyo Electron Limited Atomic layer deposition of silicon and silicon-containing films
US8592271B2 (en) 2011-03-24 2013-11-26 United Microelectronics Corp. Metal-gate CMOS device and fabrication method thereof
US8466502B2 (en) 2011-03-24 2013-06-18 United Microelectronics Corp. Metal-gate CMOS device
US8445363B2 (en) 2011-04-21 2013-05-21 United Microelectronics Corp. Method of fabricating an epitaxial layer
US8324059B2 (en) 2011-04-25 2012-12-04 United Microelectronics Corp. Method of fabricating a semiconductor structure
US8426284B2 (en) 2011-05-11 2013-04-23 United Microelectronics Corp. Manufacturing method for semiconductor structure
US8481391B2 (en) 2011-05-18 2013-07-09 United Microelectronics Corp. Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure
US9218962B2 (en) * 2011-05-19 2015-12-22 Globalfoundries Inc. Low temperature epitaxy of a semiconductor alloy including silicon and germanium employing a high order silane precursor
US8431460B2 (en) 2011-05-27 2013-04-30 United Microelectronics Corp. Method for fabricating semiconductor device
US9887290B2 (en) 2011-07-07 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon germanium source/drain regions
US20130011983A1 (en) * 2011-07-07 2013-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. In-Situ Doping of Arsenic for Source and Drain Epitaxy
US8962400B2 (en) * 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US8716750B2 (en) 2011-07-25 2014-05-06 United Microelectronics Corp. Semiconductor device having epitaxial structures
US8575043B2 (en) 2011-07-26 2013-11-05 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8647941B2 (en) 2011-08-17 2014-02-11 United Microelectronics Corp. Method of forming semiconductor device
US8674433B2 (en) 2011-08-24 2014-03-18 United Microelectronics Corp. Semiconductor process
US8853740B2 (en) 2011-10-17 2014-10-07 United Microelectronics Corp. Strained silicon channel semiconductor structure
US8476169B2 (en) 2011-10-17 2013-07-02 United Microelectronics Corp. Method of making strained silicon channel semiconductor structure
US8691659B2 (en) 2011-10-26 2014-04-08 United Microelectronics Corp. Method for forming void-free dielectric layer
US8927376B2 (en) 2011-11-01 2015-01-06 United Microelectronics Corp. Semiconductor device and method of forming epitaxial layer
US8754448B2 (en) 2011-11-01 2014-06-17 United Microelectronics Corp. Semiconductor device having epitaxial layer
US9660049B2 (en) 2011-11-03 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor transistor device with dopant profile
US8647953B2 (en) 2011-11-17 2014-02-11 United Microelectronics Corp. Method for fabricating first and second epitaxial cap layers
US8709930B2 (en) 2011-11-25 2014-04-29 United Microelectronics Corp. Semiconductor process
US9127345B2 (en) 2012-03-06 2015-09-08 Asm America, Inc. Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8866188B1 (en) 2012-03-08 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US9312359B2 (en) 2012-03-12 2016-04-12 United Microelectronics Corp. Semiconductor structure and fabrication method thereof
US9136348B2 (en) 2012-03-12 2015-09-15 United Microelectronics Corp. Semiconductor structure and fabrication method thereof
US9443970B2 (en) 2012-03-14 2016-09-13 United Microelectronics Corporation Semiconductor device with epitaxial structures and method for fabricating the same
US9202914B2 (en) 2012-03-14 2015-12-01 United Microelectronics Corporation Semiconductor device and method for fabricating the same
US8884346B2 (en) 2012-04-05 2014-11-11 United Microelectronics Corp. Semiconductor structure
US8664069B2 (en) 2012-04-05 2014-03-04 United Microelectronics Corp. Semiconductor structure and process thereof
US9263345B2 (en) * 2012-04-20 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. SOI transistors with improved source/drain structures with enhanced strain
US20130277685A1 (en) * 2012-04-20 2013-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Soi transistors with improved source/drain structures with enhanced strain
US8866230B2 (en) 2012-04-26 2014-10-21 United Microelectronics Corp. Semiconductor devices
US8835243B2 (en) 2012-05-04 2014-09-16 United Microelectronics Corp. Semiconductor process
US8951876B2 (en) 2012-06-20 2015-02-10 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US9269811B2 (en) 2012-06-20 2016-02-23 United Microelectronics Corp. Spacer scheme for semiconductor device
US8999793B2 (en) 2012-06-22 2015-04-07 United Microelectronics Corp. Multi-gate field-effect transistor process
US8796695B2 (en) 2012-06-22 2014-08-05 United Microelectronics Corp. Multi-gate field-effect transistor and process thereof
US8710632B2 (en) 2012-09-07 2014-04-29 United Microelectronics Corp. Compound semiconductor epitaxial structure and method for fabricating the same
US9117925B2 (en) 2013-01-31 2015-08-25 United Microelectronics Corp. Epitaxial process
US8753902B1 (en) 2013-03-13 2014-06-17 United Microelectronics Corp. Method of controlling etching process for forming epitaxial structure
US9034705B2 (en) 2013-03-26 2015-05-19 United Microelectronics Corp. Method of forming semiconductor device
US9064893B2 (en) 2013-05-13 2015-06-23 United Microelectronics Corp. Gradient dopant of strained substrate manufacturing method of semiconductor device
US9076652B2 (en) 2013-05-27 2015-07-07 United Microelectronics Corp. Semiconductor process for modifying shape of recess
US8853060B1 (en) 2013-05-27 2014-10-07 United Microelectronics Corp. Epitaxial process
US9263579B2 (en) 2013-05-27 2016-02-16 United Microelectronics Corp. Semiconductor process for modifying shape of recess
US8765546B1 (en) 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor
US8895396B1 (en) 2013-07-11 2014-11-25 United Microelectronics Corp. Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures
US8981487B2 (en) 2013-07-31 2015-03-17 United Microelectronics Corp. Fin-shaped field-effect transistor (FinFET)
US9218963B2 (en) 2013-12-19 2015-12-22 Asm Ip Holding B.V. Cyclical deposition of germanium
US9576794B2 (en) 2013-12-19 2017-02-21 Asm Ip Holding B.V. Cyclical deposition of germanium
US9929009B2 (en) 2013-12-19 2018-03-27 Asm Ip Holding B.V. Cyclical deposition of germanium
US9923081B1 (en) 2017-04-04 2018-03-20 Applied Materials, Inc. Selective process for source and drain formation

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