JP2003110112A - Device simulation method and semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a polycrystalline semiconductor element of an optimized device structure by determining a device parameter on the basis of a device simulation which accurately processes scattering effects of carriers in a grain boundary. SOLUTION: In a device simulation for the semiconductor element using a polycrystalline semiconductor as an active layer, a polycrystalline semiconductor element of two-dimensional or three-dimensional structure is dividedly formed into a mesh, and in each division of the mesh, the grain boundary (12) that exists between crystal grains in the active layer is processed as a plane region (14) in solving a physical equation, such as an electric potential equation or a carrier continuity equation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a polycrystalline semiconductor in its active layer.

[0002]

2. Description of the Related Art A polycrystalline thin film transistor is a semiconductor element using a polycrystalline semiconductor in an active layer, and is used to realize a light and thin display device represented by a liquid crystal display or an electroluminescence display, and a device such as a scanner. Widely used as a device.

In general, prior to the manufacture of a semiconductor device, a device simulation is performed in which the device characteristics are predicted using the device structure and the physical properties of the materials used as parameters, and the operation of the device is analyzed. Based on this, the final device structure, manufacturing conditions, etc. are determined.

Therefore, even if it is possible to predict the device characteristics in the development stage with high accuracy even for a polycrystalline thin film transistor, it is expected that it can be a useful tool for optimizing the device structure. No effective device simulation method has been proposed for a crystalline thin film transistor, and as a result, there has been a problem that it is difficult to determine the structure and manufacturing conditions of a polycrystalline thin film transistor having desired device characteristics.

[0005]

DISCLOSURE OF THE INVENTION The inventors of the present invention have made a detailed study on the problems in applying the conventional device design method to a polycrystalline thin film transistor, and as a result, determined the device structure of the polycrystalline thin film transistor. For this reason, it is extremely important to properly determine the carrier transport phenomenon in the crystal in consideration of the carrier scattering phenomenon at the crystal grain boundaries existing at high density in the active layer before determining the device structure. It has been found.

Therefore, an object of the present invention is to calculate the carrier flow density flowing in the active layer and the electric potential in the active layer based on a device simulation that accurately handles the carrier scattering effect at the crystal grain boundaries, and based on this, An object of the present invention is to provide a polycrystalline thin film transistor designed by determining device parameters.

[0007]

To achieve the above object, a device simulation method for a polycrystalline semiconductor device according to the present invention is a two-dimensional or three-dimensional structure for a polycrystalline semiconductor device using a polycrystalline semiconductor in an active layer. In the device simulation method of the polycrystalline semiconductor device, the polycrystal semiconductor device is divided into meshes, and the physical equations such as the potential equation and the carrier continuity equation are solved in each mesh. The feature is that the grain boundary is treated as a surface region.

According to this structure, the crystal grain boundaries are treated as the surface regions in accordance with the actual conditions, so that the calculation error can be reduced and a highly accurate simulation can be realized. In addition, when handling a crystal grain boundary by approximating it in a minute volume region, it is necessary to use a fine mesh not only at the grain boundary but also around the grain boundary, which takes time to calculate and requires a huge memory. Becomes In this respect, by treating the crystal grain boundary as a surface region, it is possible to avoid the problem that the simulator requires such a high calculation speed and a huge amount of memory.

Preferably, the defect levels existing in the crystal grain boundaries are treated as being distributed in the plane region. Therefore, by treating the defect levels existing in the crystal grain boundaries as being faithfully distributed in the surface region, the error in the calculation result is reduced, and a highly accurate simulation can be realized. In addition, when the crystal grain boundary is treated by approximating it in a minute volume region, not only the crystal grain boundary but also
Even around it, you have to use a small mesh,
Although the calculation speed becomes slow and a huge amount of memory is required, by treating the defect levels existing at the grain boundaries as being distributed in the plane region, these problems are avoided and high calculation is performed. The speed and required memory can be reduced.

Preferably, the equation for calculating the electric potential at the crystal grain boundary is represented by the following equation.

Ε ₁ (∂ψ / ∂n ₁ ) + ε ₂ (∂ψ / ∂n ₂ ) = − σ where ψ: potential, σ: charge surface density, ε ₁ : dielectric on one side of grain boundary , Ε ₂ : dielectric constant on the other side of the crystal grain boundary, n ₁ : component of a normal vector on one side of the crystal grain boundary, and n ₂ : component of a normal vector on the other side of the crystal grain boundary.

According to this structure, in the device simulation method for a polycrystalline semiconductor device, even when the crystal grain boundary is treated as a plane region, in the Poisson equation, ρ on the right side is a singular point at the crystal grain boundary, that is, ρ = ∞. It is possible to solve the potential equation by avoiding the phenomenon that ψ cannot be calculated.

It is preferable that the carrier scattering effect (Thermionic Emission effect) at the crystal grain boundary is taken into consideration. Thereby, in the device simulation method of the polycrystalline semiconductor element, even when the crystal grain boundary is treated as a surface region, in the carrier continuity equation of electrons and holes, the phenomenon that E calculated from ψ cannot be calculated, It is possible to solve the carrier transport equation.

Preferably, the carrier flow density passing through the crystal grain boundary is represented by the following equation.

J _t = (1-c / 2) v (n ₁ -n ₂ ) / 4 (1-c / 2) v / 4 = A ^* T ² / (qN _e ), where J _t : carrier Flow density, c: ratio of carrier flow trapped in grain boundaries, v: electron average thermal velocity,
n ₁ : carrier density on one side of the crystal grain boundary, n ₂ : carrier density on the other side of the crystal grain boundary, A ^* : effective Richardson constant,
T: absolute temperature, q: elementary charge, N _e : effective density of states.

As a result, specifically, Thermionic Emissio
A method for expressing the n-effect is provided, and it becomes possible to actually perform a device simulation of a polycrystalline semiconductor device.

Preferably, the polycrystalline semiconductor element is a polycrystalline silicon thin film transistor which is a thin film transistor using polycrystalline silicon for an active layer. As a result, in the device simulation of the polycrystalline silicon thin film transistor, it is possible to improve the accuracy of the simulation, increase the calculation speed, reduce the amount of memory required for the simulation, and the like.

Preferably, the polycrystalline semiconductor element is a laser-crystallized polycrystalline silicon thin film transistor in which polycrystalline silicon is used for an active layer and polycrystalline silicon is crystallized by a laser crystallization process. And

With such a structure, it is possible to perform optimum device simulation in a laser-crystallized polycrystalline thin film transistor in which the carrier transport mechanism of crystal grain boundaries is particularly dominant for transistor characteristics. Further, it is possible to improve the accuracy of simulation, increase the calculation speed, and reduce the required memory.

Further, in the semiconductor device of the present invention, the carrier flow density (J _t ) and the potential (ψ) are taken into consideration in consideration of the scattering effect of free carriers at the crystal grain boundaries in the semiconductor device using the polycrystalline semiconductor in the active layer. Is calculated by the following equation, and the parameters governing the device characteristics are determined based on this.

J _t = (1−c / 2) · v · (n ₁ −n ₂ ) / 4, where c is the ratio of the carrier flow trapped in the grain boundaries, v is the average electron thermal velocity, and n is ₁ : carrier density on one side of the crystal grain boundary, n ₂ : carrier density on the other side of the crystal grain boundary.

Further, ε ₁ (∂ψ / ∂n ₁ ) + ε ₂ (∂ψ / ∂n ₂ ) = − σ σ: charge surface density ε ₁ : dielectric constant on one side of the crystal grain boundary ε ₂ : crystal grain boundary Dielectric constant n ₁ on the other side: component of a normal vector on one side of the crystal grain boundary n ₂ : component of a normal vector on the other side of the crystal grain boundary Preferably, the semiconductor element uses polycrystalline silicon for the active layer. It is a polycrystalline thin film transistor, and more preferably, it is a polycrystalline thin film transistor manufactured by performing the polycrystallization of the active layer by the process of laser crystallization. With such a structure, the carrier transport mechanism of the grain boundary is a transistor. In the laser crystallized polycrystalline thin film transistor, which is particularly dominant in characteristics, a polycrystalline semiconductor element having an optimized device structure can be obtained.

[0023]

DETAILED DESCRIPTION OF THE INVENTION The semiconductor device of the present invention will be described in detail below with reference to the drawings. (Calculation of Carrier Density Flow and Potential) FIG. 5 is a structural cross-sectional view of a polycrystalline silicon thin film transistor configured by using polycrystalline silicon for the active layer.

In the polycrystalline silicon thin film transistor, a gate region, a source region 5 and a drain region 6 are formed in a polycrystalline silicon film grown on a substrate 1 by a CVD method or the like, and a heat treatment is performed on the polycrystalline silicon film. The gate insulating film 3 is formed of a silicon oxide film grown by an oxidation method or the like. Then, the gate electrode 4 is formed on the gate oxide film, and the polycrystalline silicon film under the gate electrode 4 is operated as a gate region.

In FIG. 5, straight lines obliquely penetrating through the polycrystalline silicon film from the interface between the substrate 1 and the polycrystalline silicon film toward the gate insulating film 3 have different crystal orientations constituting the polycrystalline silicon film. It is a crystal grain boundary 12 formed by a silicon crystal. The characteristic of the polycrystalline thin film transistor when compared with the single crystal thin film transistor is that since the semiconductor film forming the transistor is composed of polycrystalline, there are crystal grains with different crystal orientations in the semiconductor film, and as a result, This means that there is a crystal grain boundary 12 between each crystal grain.

As described above, in determining the device parameters of the semiconductor element in which the active layer is made of polycrystal, it is necessary to sufficiently consider the effect of the crystal grain boundaries on the carrier transport phenomenon. It is extremely important to consider what kind of model the area should be treated as.

FIG. 1B is a "plane area model" for device simulation adopted in designing the semiconductor device of the present invention.

Generally, in order to execute a device simulation, a physical system to be handled is divided into a large number of meshes, and an operation is executed so that a boundary condition defined for each mesh is satisfied. Therefore, the accuracy of the simulation result is determined by how the mesh is set. In other words, the effectiveness as a device design method is determined by what kind of mesh is set in the crystal grain boundaries in the polycrystalline semiconductor and in the vicinity thereof.

In the surface area model adopted for designing the semiconductor device of the present invention, the crystal grain boundary 12 contained in the polycrystal 11 is treated as the surface area 14. As a result, a large mesh is set even in the polycrystalline region 11 adjacent to the surface region 14.

On the other hand, in the conventional device simulation method, the "small volume region model" is adopted and the crystal grain boundary 12 is approximated by the small volume region 13. When such a model is adopted, since it is necessary to make the simulation result highly accurate and to continuously change the mesh size in order to ensure the high convergence, as shown in FIG. It is necessary to set the mesh size small not only in the volume region 13 but also in the polycrystalline region 11 in the vicinity thereof.

As described above, in the surface area model used for designing the semiconductor device of the present invention and the minute volume area model used in the conventional simulation method, the mesh setting method for executing the simulation is set. There is a big difference.

Using the meshes set as shown in FIGS. 1 (a) and 1 (b), what kind of calculation is actually used to execute the device simulation will be described below.

First, in the device simulation method employing the surface area model, the defect levels existing in the crystal grain boundaries are treated as being distributed in the surface area.

Here, the calculation of the electric potential (ψ) at the crystal grain boundary is executed based on Gauss's law represented by the following equation.

Ε ₁ (∂ψ / ∂n ₁ ) + ε ₂ (∂ψ / ∂n ₂ ) = − σ (σ is the charge surface density, ε ₁ is the dielectric constant on one side of the grain boundary, and ε ₂
Is the dielectric constant on the other side of the crystal grain boundary, n ₁ is the component of the normal vector on one side of the crystal grain boundary, and n ₂ is the component of the normal vector on the other side of the crystal grain boundary. In the design, the carrier scattering effect at the grain boundaries, which was ignored in the conventional device simulation method, is considered. More specifically, thermionic E at grain boundaries
It is handled in consideration of the mission effect.

According to this handling, the carrier flow density (J _t ) passing through the grain boundaries is J _t = (1-c / 2) ·
given by v · (n ₁ −n ₂ ) / 4.

Here, c is the rate at which the carrier flow is trapped in the grain boundaries, v is the average heat velocity of electrons, and n ₁ and n ₂
Is the carrier density on one side and the other side of the grain boundary.

The above relational expression is converted into the effective Richard.
Using the son constant A ^* and the effective density of states N _e , (1
^{-C / 2) · v / 4} = A * · T 2 / ( based on the q · _{N e)} of the _{equation, J t = (n 1 -n} 2) · A * · T 2 /
It may be expressed as (q · N _e ). Here, T is absolute temperature and q is elementary charge.

The above-mentioned effective Richardson constant A ^*
Is a constant that depends on the quality of the crystal grain boundary, and is large when the crystal orientations are aligned or when adjacent crystal grains are normally connected. In that case, the carrier flow density J _t has a large value. On the other hand, when the crystal orientations are not uniform or when an oxide film exists at the crystal grain boundaries, the effective Richards
The on constant A ^* is small and the carrier flow density J _t is a small value. Note that the effective Richardson constant A ^* of carefully manufactured high-quality polycrystalline silicon is 11 A / c.
It is known to be m ² / K ² .

On the other hand, in the conventional device simulation method, the Poisson equation Δψ is used as the potential equation.
= −ρ / ε (ψ is the potential, ρ is the charge volume density, and ε is the dielectric constant), and the carrier continuity equation for electrons and holes is ∇ · {(− n _n · μ _n · _{E) - (D n · ∇n} n)} - G = 0 ∇ · {(-n p · μ p · E) - (D p · ∇n p)} - G = 0 (n n or _{n p} is Electron or hole carrier density, μ
_n or μ _p is electron or hole mobility, E is electric field strength, D _n or D _p is electron or hole diffusion coefficient, and G is carrier generation / annihilation ratio.

In the conventional simulation method based on the Poisson equation, when the grain boundary is treated as a surface region, ρ included in the right side of the Poisson equation is used.
Becomes ρ = ∞ at the grain boundary, and the potential (ψ)
Cannot be obtained analytically. Therefore, it becomes impossible to calculate E that should be calculated from ψ by the electron or hole carrier continuity equation. Therefore, in the conventional device simulation method for a polycrystalline semiconductor device based on the Poisson equation, it is impossible to treat the crystal grain boundary as a plane region.

On the other hand, according to the device simulation method based on Gauss's law, since the crystal grain boundaries are treated as plane regions, the problem that the solution corresponding to the desired physical quantity diverges is solved. .

As described above, according to the device simulation method employed in the design of the semiconductor device of the present invention, the polycrystalline semiconductor is based on the Gauss' law and considering the carrier scattering effect at the grain boundary. It becomes possible to execute the device simulation of the above with high accuracy.

In order to confirm the effectiveness of the device simulation method adopted in the semiconductor device design of the present invention for a polycrystalline semiconductor, a grain boundary existing in a polycrystalline silicon film doped with a small amount of a dopant is assumed, The potential distributions near the grain boundaries were obtained and compared between the small volume region model and the surface region model.

FIG. 2 is a diagram showing the potential in the vicinity of the crystal grain boundaries thus obtained. The simulation using the minute volume region model is performed with the minute region volume width set to 1 nm and the mesh width adjacent to it set to 1 nm.

In general, it is known that the crystal grain boundary acts as a trapping center for carriers, and carrier traps are present at a high density in the vicinity of the crystal grain boundary. Once the carriers are trapped by the traps, they are trapped. A so-called potential barrier is formed by locally accumulating electric charges corresponding to the electric charges of the carriers. When a potential barrier is formed at the crystal grain boundary by capturing carriers, free carriers having lower thermal excitation energy than this potential barrier cannot pass through the crystal grain boundary and the trapping center of the crystal grain boundary. The process of being trapped in and contributing to the formation of a new potential barrier is repeated. In FIG. 2, the potential has a large value at the position 0 nm corresponding to the crystal grain boundary because the defect level existing in the crystal grain boundary traps carriers and charges them to form a potential barrier. .

As is clear from FIG. 2, the potential distribution obtained by the simulation is different between the minute volume region model and the surface region model, and in particular, the potential shape at the grain boundary is greatly different. This difference also affects the simulation results of the free carrier density distribution and the electrical conductivity of the polycrystalline silicon film.

The results of the free carrier density distribution calculated based on the above surface area model and the electric conductivity of the polycrystalline silicon film are compared with the actual measurement values obtained by measuring the polycrystalline silicon film, showing good agreement. Was confirmed, and the validity and effectiveness of the device simulation method adopted in the design of the semiconductor device of the present invention could be confirmed.

In the present embodiment, the simulation is performed assuming electrons as free carriers and acceptor-like traps as carrier traps, but holes are assumed as free carriers and donor-like traps as carrier traps. Needless to say, a similar analysis can be performed.

According to the device simulation method based on the above-mentioned surface area model, in addition to the effectiveness as the simulation method, there is another advantage that it is not necessary to consider the influence of the mesh width on the simulation result. .

For example, FIG. 3 shows the results of obtaining the potential distribution in the vicinity of the crystal grain boundaries when the mesh width adjacent to the minute volume region is changed in the minute volume region model. Here, the mesh width adjacent to the minute volume region is 1 to
The distance is changed to 1 nm at intervals of 3 nm. As is clear from FIG. 3, it can be read that the potential distribution greatly changes depending on the mesh width in the minute volume region model.

On the other hand, the above phenomenon does not occur in the surface area model. In the surface area model, since the mesh of the polycrystalline area adjacent to the surface area is set to have a large mesh width, it is not necessary to consider the influence of the mesh width on the simulation result. (Design Procedure of Semiconductor Element of the Present Invention) Next, the procedure for optimizing the device parameters of the semiconductor element to be designed by the above-described device simulation method will be described below.

FIG. 6 is a block diagram showing a device simulator for simulating the device characteristics of the semiconductor device of the present invention.

The device simulator 31 includes the control means 3
2, input means 33, calculation means 34, output means 35
The control means 32 is a means for controlling the entire device simulator 31.

The input means 33 includes a simulation condition input means 36 for inputting a simulation condition such as a gate voltage to be applied, a structure / shape of a semiconductor element, a grain size of a polycrystal operating as an active layer, and the like. Device structure input means 3 for inputting crystallinity parameters
7, the calculation means 34 is a carrier flow density / potential calculation means 38 for calculating the density of the carrier flow flowing in the device based on the above-mentioned theory, and the result and the seed species input by the input means 33. The device characteristic calculation means 39 for calculating a desired device characteristic based on the condition

FIG. 7 shows a processing procedure when the device simulator 31 executes the device simulation.

First, the simulation data such as the gate voltage condition of the semiconductor element is input by the simulation condition input means 36 of the input means 33 (S46).

Data concerning the device structure, such as the structure and shape of the semiconductor element, is stored in the device structure input means 37.
Is input from (S47). Here, the device structure data is, for example, the gate oxide film thickness, the source / drain spacing, the crystallinity of the active layer, the contact hole shape, the wiring shape, the dopant concentration, etc., and the contents thereof depend on the device to be designed. Can be freely set. The device structure data may be directly input by a user of the device simulator 31, or may be data input by a process simulator provided separately from the device simulator 31. Is also good.

The carrier flow density / potential calculation means 38 receives the device structure data from the device structure input means 37 and calculates the carrier flow density and the potential based on the above relational expression.

The device characteristic calculation means 39 receives the simulation data and the calculated carrier flow density / potential values and calculates device characteristics such as CV characteristics (S49), and the result is output means 35. Is output by.

The user of the device simulator 31 repeats the procedure shown in FIG. 7 while comparing the output device characteristics with the design characteristics, to thereby obtain the gate oxide film thickness, the source / drain spacing, and the crystal of the active layer. Device parameters such as the conductivity, contact hole shape, wiring shape, dopant concentration, etc. are optimized to optimize the device structure capable of obtaining desired characteristics. (Polycrystalline thin film transistor in consideration of grain boundaries) Next,
A manufacturing process of the thin film transistor of the present invention having a device structure determined by the above device simulation will be described with reference to the drawings.

FIG. 4 is a diagram showing a manufacturing process of the polycrystalline thin film transistor of the present invention. In this embodiment, a case where a silicon thin film is formed as a semiconductor layer for forming a transistor on an insulating substrate such as glass will be described as an example. The polycrystalline silicon thin film transistor of this example is a laser crystallized polycrystalline silicon thin film transistor in which the carrier transport mechanism of crystal grain boundaries is particularly dominant for transistor characteristics.

First, a silane-based reactive gas is used as a silicon atom supply source on the insulating substrate 1, for example, low pressure CVD using disilane (Si ₂ H ₆ ) gas.
(LPCVD) method or plasma enhancement CVD (PECV) using, for example, monosilane (SiH ₄ ) gas
The amorphous silicon film 2 is formed by the method D). Here, the silicon film 2 is formed so that the film thickness thereof is a film thickness calculated in advance as an optimum film thickness by the device simulation described above.

Subsequently, the formed amorphous silicon film 2 is re-crystallized by supplying the energy necessary for crystallization of amorphous silicon atoms from the outside to form a polycrystalline silicon film 2. (Fig. 4
(A)). Here, the crystallinity such as the grain size and crystal orientation of the polycrystal is set in advance so that various characteristics such as the required carrier mobility can be obtained by the above device simulation. Further, in the recrystallization method, an optimum method and conditions are selected in order to realize such crystallinity. For example, as shown in FIG. 4A, a laser crystal for light irradiation using an excimer laser or the like is used. A chemical treatment method or a method of performing solid phase growth by performing heat treatment in a heat treatment furnace is selected.

The polycrystalline silicon film 2 thus formed is subjected to desired patterning by using a photolithography technique, and further a dielectric film 3 which will be used as a gate oxide film later is formed. It This dielectric film is, for example, a silicon oxide film (SiO _x ) formed by a thermal CVD method, and is deposited on the entire surface of the substrate (FIG. 4).
(B)).

Next, impurity doping is performed on the active layer to adjust the threshold value, but an ion implantation method is employed which allows easy and accurate doping level control with high accuracy.
The type of element to be doped is determined by the design of the thin film transistor, but in the case of the present embodiment, the case of an n-type thin film transistor is shown, and the group III impurity boron (B) that acts as an acceptor in the silicon crystal is shown. ) Is injected (FIG. 4 (b)). The doping amount to be ion-implanted is set to a value calculated in advance by simulation.

Subsequent to the doping process into the active layer, a thin film for forming the gate electrode 4 is formed. After depositing a thin film of metal or polysilicon selected as a gate electrode material on the entire surface of the substrate by a CVD method or a sputtering method, patterning is performed by photolithography so as to have a desired gate electrode shape (FIG. 4).
(C)).

Further, in order to make the conductivity type of the source region 5 and the drain region 6 n ⁺ type, for example, phosphorus (P) is ion-implanted (FIG. 4C). In this step, the already patterned gate electrode 4 is used as a mask to implant phosphorus (P) in a self-aligned manner. That is, there is no phosphorus implantation into the polycrystalline silicon film region immediately below the gate electrode, and the state in which boron ions are implanted in the step of FIG. 4B is maintained.

After the implantation of boron into the active layer region and the implantation of phosphorus into the source region 5 and the drain region 6, the crystal lattice state disturbed by these ion implantations is restored, and boron and phosphorus are used as dopants. Processing for activating the image is performed.

Various methods are known as the method for activating the above-mentioned dopants. For example, if a thermal activation method for holding the substrate at a high temperature for a long time is selected, the dopant activation can be executed with a simple apparatus. There is an advantage that a thin film transistor can be manufactured at low cost. Further, the dopant activation is not limited to the above thermal activation method, and may be, for example, a laser activation method. When the dopant activation is performed by the laser activation method, the same laser light source as the laser used in the crystallization process of the amorphous silicon thin film shown in FIG. 4A may be used. A laser light source having another different wavelength may be provided and used.

Subsequent to the above dopant activation, an interlayer insulating film 7 for electrically insulating the individual transistors formed on the substrate from each other is formed (FIG. 4 (d)).
The dielectric film 3 and the interlayer insulating film 7 formed on the source region 5 and the drain region 6 are removed by photolithography to open contact holes, and then thin films for the source electrode 8 and the drain electrode 9 are deposited. After that, the source electrode 8 and the drain electrode 9 are patterned. In this way, a polycrystalline thin film transistor is completed (FIG. 4).
(D)).

In this embodiment, the conductivity type of the active layer is p.
Mold and select boron as the implanted dopant,
Although the gate voltage-drain current characteristic is shifted to the voltage plus side, it goes without saying that another acceptor impurity such as aluminum (Al) may be selected as the dopant. Further, the active layer may have an n-type conductivity type depending on the design requirements of the transistor. In this case, a donor impurity such as phosphorus (P) may be selected as the dopant.

In the above-mentioned embodiment, an example in which the ion implantation method with mass spectrometry of the dopant is selected as the doping method for the active layer is shown, but the doping method is not limited to this. That is, another doping method may be used in which doping is performed without mass spectrometry of the dopant. In particular, when adopting the ion doping method without mass spectrometry, structural defects such as dislocations existing at the active layer, the gate insulating film, the substrate insulating film, or their interfaces due to the ion doping, and electrical charges such as fixed electric charges. There is an advantage that it is possible to reduce the physical defects. On the other hand, when the ion implantation method accompanied by mass spectrometry is adopted, structural defects such as dislocations or fixed charges induced in the active layer, the gate insulating film, the substrate insulating film, or their interfaces due to excessive ion bombardment are used. It is possible to suppress electrical defects such as. Therefore, an optimum method may be appropriately selected to obtain desired characteristics of the thin film transistor.

Furthermore, the doping of the active layer does not have to be performed after the step of polycrystallizing the amorphous silicon layer, but may be performed simultaneously with the film formation of the amorphous silicon. For example, in the case of performing doping by an ion doping method, an amorphous silicon film is formed by using a gas containing a silicon element, which is a base material of a transistor, and a gas containing a dopant element at the same time, so as to contain impurities serving as a dopant. An amorphous silicon film is obtained.

Needless to say, the impurity doping process for the active layer region, the source region, and the drain region may be set in any manufacturing process order as long as the doping of these layers is realized. It is not always necessary to dope the active layer region.

In this example, the device simulation method of the present invention was applied to a polycrystalline silicon thin film transistor using polycrystalline silicon for the active layer.
It can also be applied to a polycrystalline semiconductor device using other polycrystal such as GaAs in the active layer.

[0077]

According to the present invention, in designing a semiconductor device using a polycrystalline semiconductor in the active layer, the grain boundary of the active layer is regarded as a surface area model, and the carrier scattering effect in the grain boundary is accurately measured. Since the carrier flow density and the potential are calculated based on the device simulation to be handled, and the device parameters are determined based on these, it is possible to provide a polycrystalline semiconductor element having an optimized device structure.

[Brief description of drawings]

FIG. 1A is a diagram showing a model of a minute volume region of a grain boundary. FIG. 1B is a diagram showing a surface area model of a crystal grain boundary.

FIG. 2 is a result of simulating a potential in the vicinity of a crystal grain boundary using a minute volume region model and a surface region model of the crystal grain boundary.

FIG. 3 is a result of a potential distribution calculated by changing a mesh width when simulating a potential in the vicinity of a crystal grain boundary by a minute volume region model.

FIG. 4 is a diagram illustrating a manufacturing process of a polycrystalline silicon thin film transistor.

FIG. 5 is a structural cross-sectional view of a polycrystalline silicon thin film transistor.

FIG. 6 is a block diagram of a device simulator for manufacturing a semiconductor device of the present invention.

FIG. 7 is a flow chart for explaining the operation of the device simulator for manufacturing the semiconductor device of the present invention.

[Explanation of symbols]

1 substrate 2 Polycrystalline silicon film 3 Gate insulation film 4 gate electrode 5 Source area 6 drain region 11 Polycrystalline semiconductor 12 grain boundaries 13 Micro volume region 14-sided area

Continued front page    F term (reference) 5F052 AA02 AA11 DA02 DB02 DB03                       JA01                 5F110 AA25 BB01 BB10 CC02 EE02                       EE09 EE44 EE45 FF02 FF29                       GG02 GG04 GG13 GG32 GG45                       GG47 GG51 GG52 HJ01 HJ13                       HJ23 NN02 PP01 PP03 QQ11

Claims (10)

[Claims] 1. A polycrystalline semiconductor device having a two-dimensional or three-dimensional structure is divided into meshes for a polycrystalline semiconductor device using a polycrystalline semiconductor in an active layer, and each mesh has a potential equation.
In a device simulation method of a polycrystalline semiconductor device for solving a physical equation such as a carrier continuity equation, a device of a polycrystalline semiconductor device characterized in that a crystal grain boundary existing between crystal grains of the active layer is treated as a plane region. Simulation method. 2. The polycrystalline semiconductor device device simulation method according to claim 1, wherein the defect levels existing in the crystal grain boundaries are treated as being distributed in the plane region. Device simulation method. 3. The method for simulating a polycrystalline semiconductor device according to claim 1, wherein the equation for calculating the potential at the crystal grain boundary is represented by the following equation: Device simulation method. ε ₁ (∂ψ / ∂n ₁ ) + ε ₂ (∂ψ / ∂n ₂ ) ＝ − σ ψ: Electric potential σ: Charge surface density ε ₁ : Dielectric constant on one side of the grain boundary ε ₂ : Grain boundary Dielectric constant of other side n ₁ : Component of normal vector on one side of grain boundary n ₂ : Component of normal vector on other side of grain boundary 4. The device simulation method for a polycrystalline semiconductor device according to claim 1, wherein the scattering effect of carriers at the crystal grain boundaries is taken into consideration. Method. 5. The device simulation method for a polycrystalline semiconductor device according to claim 4, wherein the carrier flow density passing through the crystal grain boundaries is represented by the following equation. Method. _{J t = (1-c /} 2) v (n 1 -n 2) / 4 (1-c / 2) v / 4 = A * T 2 / (qN e) J t: carrier flow density c: carrier flow Trapped in the crystal grain boundary v: average electron thermal velocity n ₁ : carrier density on one side of the crystal grain boundary n ₂ : carrier density on the other side of the crystal grain boundary A ^* : effective Richardson constant T: absolute temperature q: Elementary charge N _e : effective density of states 6. The method for simulating a polycrystalline semiconductor device according to claim 1, wherein the polycrystalline semiconductor device is a thin film transistor using polycrystalline silicon for an active layer. 2. A device simulation method for a polycrystalline semiconductor device, comprising: 7. The method of simulating a polycrystalline semiconductor device according to claim 6, wherein the polycrystalline semiconductor device uses polycrystalline silicon for an active layer, and the polycrystalline silicon is crystallized by a laser crystallization process. A method for simulating a polycrystalline semiconductor device, which is characterized by being a laser crystallized polycrystalline silicon thin film transistor. 8. A semiconductor device using a polycrystalline semiconductor in an active layer, wherein a carrier flow density (J) passing through a crystal grain boundary in the active layer is used.
The _{t) J t = (1-} c / 2) · v · (n 1 -n 2) / 4 c: ratio carrier flow are trapped in the crystal grain boundaries v: electron mean thermal velocity n _1: crystal grain boundary Carrier density n ₂ on one side of: is calculated from the carrier density on the other side of the crystal grain boundary, and the potential (ψ) in the active layer is ε ₁ (∂ψ / ∂n ₁ ) + ε ₂ (∂ψ / ∂n ₂ ) = − Σ σ: charge surface density ε ₁ : dielectric constant on one side of the crystal grain boundary ε ₂ : dielectric constant on the other side of the crystal grain boundary n ₁ : component of normal vector on one side of the crystal grain boundary n ₂ : crystal A semiconductor element designed by calculating with a component of a normal vector on the other side of a grain boundary, and determining device parameters based on the calculated carrier flow density and potential. 9. The semiconductor device according to claim 8, wherein the semiconductor device is a polycrystalline thin film transistor using polycrystalline silicon for an active layer. 10. The semiconductor device is produced by polycrystallizing an active layer by a laser crystallization process,
The semiconductor device according to claim 8 or 9, characterized in that.