JP2004119636A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device using a large and inexpensive substrate showing the stable characteristics, which also includes a single crystal Si thin film and not generating any variations and fluctuations in the junction strength of the single crystal Si thin film and in the stress working on the junction interface, and also to provide a method of manufacturing the semiconductor device. <P>SOLUTION: A polycrystal Si thin film 4 and a single crystal Si thin film 5 are formed on a SiO<SB>2</SB>film 2 deposited on the insulated substrate 1. Difference in the specified linear expansion between the insulated substrate 1 and the single crystal Si thin film 5 is about 250ppm or less within the temperature range from the room temperature or higher to 600°C or less. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device used for an active matrix drive liquid crystal display device and the like, which improves the circuit performance of a device in which a peripheral drive circuit and a control circuit are integrated, and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, thin film transistors (hereinafter, referred to as TFTs) of a-Si (amorphous Si) or p-Si (polycrystalline Si) are formed on a glass substrate to form a liquid crystal display panel or an organic EL panel. A so-called active matrix drive for driving has been performed. Further, peripheral drivers have been integrated using p-Si which has high mobility and operates at high speed. Alternatively, studies have been made to form higher performance Si devices for integration of systems such as image processors and timing controllers that require higher performance.
[0003]
This is because, in polycrystalline Si, the mobility is lowered or the S coefficient (sub-level) is increased due to the presence of localized levels in the gap due to imperfect crystallinity, defects near the grain boundaries, and localized levels in the gap. This is because there is a problem that the performance of the transistor is insufficient to form a high-performance Si device because the threshold coefficient increases.
[0004]
Therefore, in order to form a Si device with higher performance, in addition to laser crystallization, for example, techniques for improving crystallinity such as SLS (Sequential Lateral Solidification) and the like (for example, see Patent Document 1), and CLC (CW Laser Lateral Crystallization) (for example, see Non-Patent Document 1). These are aimed at depositing an a-Si film on a glass substrate and crystallizing the film with good controllability or approaching a single crystal.
[0005]
However, the technique using these lasers grows the crystal by heating only the Si film to a high temperature while keeping the temperature of an insulating substrate having low heat resistance such as glass at a low temperature. For this reason, 10 ⁹ A strong tensile stress of about Pa is applied, which causes problems such as cracks in the film, poor reproducibility in TFT characteristics, and large variations.
[0006]
On the other hand, there is a technique in which single-crystal Si is attached to an insulating substrate and is thinned (for example, see Patent Document 2). According to this technique, an oxide film can be formed on a single crystal Si substrate, and a single crystal Si thin film can be formed thereon. However, when an attempt is made to bond to an insulating substrate other than Si, for example, a glass substrate or a quartz substrate, there is a problem that Si is peeled or broken due to a difference in thermal expansion coefficient with an insulating substrate such as a quartz substrate.
[0007]
On the other hand, there is a method of changing the composition of crystallized glass in order to prevent the destruction in the step of improving the heat bonding strength due to the difference in thermal expansion coefficient from the quartz substrate (for example, see Patent Document 3).
[0008]
[Patent Document 1]
US Pat. No. 6,300,175 (October 9, 2001)
[0009]
[Patent Document 2]
JP-A-5-211128 (published on August 20, 1993)
[0010]
[Patent Document 3]
JP-A-11-163363 (published on June 18, 1999)
[0011]
[Non-patent document 1]
A. Hara et. al. , "Ultra-high Performance Poly-Si TFTs on a Glass by a Stable Scanning CW Laser Lateral Crystallization", 2001 International Workshop on Active matrix Liquid Crystal Displays --TFT Technologies and Related materials - (AM-LCD2001), Digest of Technical Papers, p. 227-230, July 11-13, 2001, Japan
Society of Applied Physics (Japan Society of Applied Physics)
[0012]
[Problems to be solved by the invention]
However, crystallized glass generally contains an alkali atom, and has properties that conflict with obtaining a transistor with stable characteristics. Further, in the above technology, the shape of the single-crystal Si substrate is a 6, 8, or 12-inch disk, so that the insulating substrate to be bonded is limited to a 6, 8, or 12-inch disk. It was impossible to manufacture a panel or an organic EL panel, and even if the panel was small, the manufacturing cost was high, and practical use was difficult.
[0013]
Furthermore, when a substrate containing no alkali atom is used, when a single crystal Si substrate and an insulating substrate are bonded, the bonding strength is reduced due to a difference in thermal expansion coefficient. Further, when stress acts on the joined interface, the characteristics of the TFT to be formed are deteriorated due to unevenness and variation of the stress acting on the interface.
[0014]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a large-sized and inexpensive substrate having a stable characteristic having a single-crystal Si thin film, and having a bonding strength and a bonding interface of the single-crystal Si thin film. An object of the present invention is to provide a semiconductor device free from unevenness and variation in working stress and a method for manufacturing the same.
[0015]
[Means for Solving the Problems]
According to another aspect of the present invention, there is provided a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed in different regions on an insulating substrate. It is characterized in that a standardized difference in linear expansion from a single-crystal Si thin film is approximately 250 ppm or less in a temperature range of approximately room temperature to 600 ° C.
[0016]
Usually, localized levels in the gap, defects near the crystal grain boundaries, and localization in the gap due to the imperfectness of crystallinity peculiar to polycrystalline Si, which hinder the formation of high-performance devices Problems such as a decrease in mobility and an increase in S coefficient (subthreshold coefficient) due to the presence of a level can be solved by using single crystal Si as the semiconductor thin film used as the active layer.
[0017]
Thus, according to the above configuration, the polycrystalline Si thin film and the single-crystal Si thin film are formed in different regions on an insulating substrate such as a large glass substrate. Therefore, devices requiring higher performance, such as a timing controller and a microprocessor, can be formed in the single crystal Si thin film formation region, and the remaining devices can be formed in the polycrystalline Si thin film formation region.
[0018]
That is, even if the size of the single-crystal Si thin film is limited, high-speed logic that requires single-crystal Si, high-speed logic that requires power consumption, and variations, a timing generator, a high-speed DAC (current buffer), and the like are formed. Any size that is large enough to do so is acceptable. Therefore, a high-performance and high-performance circuit system that can be realized only with single-crystal Si can be integrated on a substrate. For example, for a display device such as a liquid crystal panel or an organic EL panel in which a high-performance system is integrated. Can be manufactured at a very low cost as compared with the case where all devices are formed of single crystal Si.
[0019]
In addition, the shape of the single crystal Si substrate is limited to a disk of 6, 8, or 12 inches, which is the wafer size of an LSI manufacturing apparatus. However, since a polycrystalline Si thin film is also formed on the substrate, It is also possible to manufacture liquid crystal display panels and organic EL panels.
[0020]
Further, it is not necessary to use crystallized glass whose composition is adjusted in order to prevent breakage in a step of improving the heat bonding strength due to a difference in thermal expansion coefficient from a quartz substrate as described in Patent Document 3. Thus, the problem of alkali metal contamination caused by crystallized glass is eliminated, and destruction in the step of improving the heat bonding strength due to a difference in thermal expansion coefficient can be prevented.
[0021]
Further, the difference between the normalized linear expansion of the insulating substrate and the single-crystal Si thin film is approximately 250 ppm or less in a temperature range of approximately room temperature or higher and 600 ° C. or lower. The difference between the expansion coefficients becomes smaller. Therefore, in the process for forming a single-crystal Si thin film on an insulating substrate, it is necessary to surely prevent destruction, bonding interface separation, or generation of defects in the crystal in the cleavage separation process from the hydrogen implantation position due to the difference in thermal expansion coefficient. In addition, the heat bonding strength can be improved. Here, the thermal expansion is a change in length due to a change in temperature.
[0022]
The semiconductor device of the present invention is a semiconductor device in which a polycrystalline Si thin film and a single crystal Si thin film are formed in different regions on an insulating substrate, and the shift amount of the Raman peak in the single crystal Si thin film is 519. .5cm ^-1 Above and 521.5cm ^-1 It is characterized as follows.
[0023]
According to the above configuration, the polycrystalline Si thin film and the single crystal Si thin film are formed in different regions. Therefore, devices requiring higher performance, such as a timing controller and a microprocessor, can be formed in the single crystal Si thin film formation region, and the remaining devices can be formed in the polycrystalline Si thin film formation region.
[0024]
Normally, when crystallization or crystal growth is performed using a laser, a large stress remains in the Si thin film.
[0025]
However, according to the above configuration, the shift amount of the Raman peak in the single-crystal Si thin film is 519.5 cm. ^-1 Above and 521.5cm ^-1 By the following, the stress acting on the Si interface in the single crystal Si thin film can be made substantially zero. Therefore, when a TFT is formed, a decrease or variation in mobility due to strain of the Si crystal due to unevenness or variation in stress acting on the Si interface, or a defect at the interface, an associated fixed charge, and a localized level at the interface. , The threshold shift and the variation, the characteristic stability decrease, and the like can be reliably prevented.
[0026]
In the above semiconductor device, the insulating substrate may be formed by forming SiO2 on at least the surface of the region where single crystal Si exists. ₂ It is preferable that the layer is formed of a high strain point glass made of an alkaline earth-aluminoborosilicate glass having a layer formed thereon.
[0027]
According to the above configuration, it is not necessary to use crystallized glass of which composition is adjusted, so that the insulating substrate is made of a high strain point glass generally used for a liquid crystal display panel or the like by active matrix driving, thereby reducing cost. Can manufacture a semiconductor device.
[0028]
In the above semiconductor device, the insulating substrate is made of barium-aluminoborosilicate glass, alkaline earth-aluminoborosilicate glass, borosilicate glass, alkaline earth-zinc-lead-aluminoborosilicate glass, alkaline earth-zinc-alumino Preferably, it is made of any one of borosilicate glass.
[0029]
According to the above configuration, the insulating substrate is made of the glass described above, which is a high strain point glass generally used for a liquid crystal display panel or the like by active matrix driving, so that it is suitable for an active matrix substrate at low cost. Semiconductor device can be manufactured.
[0030]
The semiconductor device is preferably an active matrix substrate including an integrated circuit including a plurality of MOSFETs, bipolar transistors, or SITs on an insulating substrate.
[0031]
According to the above configuration, the semiconductor device is an active matrix substrate in which an integrated circuit composed of a plurality of MOS (Metal Oxide Semiconductor) FETs (TFTs) is formed on an insulating substrate. Can be obtained.
[0032]
In the above semiconductor device, it is preferable that a region of the single-crystal Si thin film and a region of the polycrystalline Si thin film formed on the insulating substrate are separated by 0.3 μm or more. In the above-described semiconductor device, it is more preferable that the region of the single-crystal Si thin film and the region of the polycrystalline Si thin film formed on the insulating substrate are separated by 0.5 μm or more.
[0033]
According to the above configuration, it is possible to prevent, for example, Ni, Pt, Sn, Pd, and the like from diffusing from polycrystalline Si to single-crystal Si, and to stabilize the characteristics of the semiconductor device.
[0034]
In the above-described semiconductor device, it is preferable that at least one of mobility, a subthreshold coefficient, and a threshold value be different for each of the regions in transistors of the same conductivity type formed in different regions.
[0035]
According to the above configuration, at least one of the mobility, the sub-threshold coefficient, and the threshold is different among the transistors of one conductivity type formed in different regions, so that the transistor is suitable for required characteristics. Region.
[0036]
In the above-described semiconductor device, it is preferable that at least one of a gate length, a thickness of a gate oxide film, a power supply voltage, and a logic level differs in each of the integrated circuits formed in different regions.
[0037]
According to the above configuration, furthermore, in the integrated circuits formed in the different regions, at least one of the gate length, the thickness of the gate oxide film, the power supply voltage, and the logic level is different. In addition, the integrated circuit can be formed in a suitable region.
[0038]
In the above-described semiconductor device, it is preferable that, in an integrated circuit formed in a different region, a processing rule is different for each of the regions.
[0039]
According to the above configuration, since the integrated circuits formed in different regions have different processing rules, the integrated circuits can be formed in appropriate regions in accordance with the processing rules.
[0040]
In the above semiconductor device, the thickness d of the single-crystal Si thin film is a small value including a variation margin with respect to the maximum depletion length Wm determined by the impurity Ni, that is, the impurity density is a practical lower limit. ^Fifteen cm ^-3 However, the upper limit of d is preferably about 600 nm or less.
[0041]
Here, Wm = [4ε _s kTln (Ni / ni) q ² Ni] ^1/2 Where ni is the intrinsic carrier density, k is the Boltzmann constant, T is the absolute temperature, ε _s Is the dielectric constant of Si, q is the electron charge, and Ni is the impurity density.
[0042]
According to the above configuration, since the thickness of the single-crystal Si thin film is approximately 600 nm or less, the S value of the semiconductor device decreases, and the off-state current decreases.
[0043]
In the above semiconductor device, the thickness of the single-crystal Si thin film is preferably 100 nm or less.
[0044]
According to the above configuration, the S value (sub-threshold coefficient) of the semiconductor device is further reduced, and the off-state current is further reduced.
[0045]
In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention includes a method of manufacturing a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed on an insulating substrate. ₂ A step of sequentially depositing a film and an amorphous Si film; a step of heating the amorphous Si film to grow a polycrystalline Si layer to form a polycrystalline Si thin film; A step of etching and removing a region, and a step of oxidizing the surface or depositing an oxide film in advance to form a SiO 2 ₂ A single crystal Si substrate having a hydrogen ion implanted portion formed with a film and implanted with a predetermined concentration of hydrogen ions at a predetermined depth has a predetermined shape covering a part or substantially the entire region of the region removed by etching. A cutting step, a step of cleaning the insulating substrate and the single-crystal Si substrate and activating the surfaces of the two substrates, and a step of etching and removing the cut single-crystal Si substrate on the side where hydrogen ions are implanted. Bonding the two substrates by bringing them into close contact with each other at room temperature, and forming a single-crystal Si thin film on the insulating substrate by subjecting the substrates to cleavage by the heat treatment, thereby separating the hydrogen ion implanted portions. It is characterized by including.
[0046]
According to the above method, the bonding strength can be increased by heating the single-crystal Si substrate into which the hydrogen ions of the predetermined concentration have been implanted at the predetermined depth, and the single-crystal Si substrate can be provided with the hydrogen ion implanted portion. By separating at the boundary, a single crystal Si thin film can be obtained. Therefore, localized levels in the gap, defects near the crystal grain boundaries, and localization in the gap due to crystal imperfections peculiar to polycrystalline Si, which are obstacles to forming a high-performance device Problems such as a decrease in mobility and an increase in S coefficient due to the presence of a level can be solved by single crystal Si. Therefore, a single-crystal Si thin film and a polycrystalline Si thin film can be formed on an insulating substrate, and the subsequent steps are formed by a common processing process. The device can be formed of polycrystalline Si. Accordingly, a semiconductor device such as a display device such as a liquid crystal panel or an organic EL panel in which a high-performance system is integrated can be manufactured at low cost.
[0047]
In addition, SiO ₂ Since a single-crystal Si substrate is bonded to an insulating substrate such as a glass substrate through the formation of a film in advance, a decrease in mobility due to strain of the Si crystal due to stress applied to the bonded Si interface, or defects at the interface, This can prevent the fixed charges at the interface, the threshold shift due to the localized level of the interface, the deterioration of the characteristic stability, and the like. This eliminates the need to use crystallized glass whose composition has been adjusted in order to improve the heat bonding strength due to the difference in thermal expansion coefficient from the quartz substrate and prevent destruction in the peeling step, and it is possible to use glass with a high strain point. Therefore, the problem of contamination by alkali metal due to crystallized glass is eliminated, and it is possible to improve the heat bonding strength due to the difference in thermal expansion coefficient and prevent breakage in the peeling step.
[0048]
Further, for example, a polycrystalline Si film is formed on a large-area high-strain-point glass substrate, and the polycrystalline Si thin film is etched and removed in advance so as to cover a region where a single-crystal Si substrate processed to an appropriate size is to be bonded. Then, a single crystal Si substrate is bonded to this region, and the single crystal Si thin film and SiO ₂ By leaving the film and exfoliating and removing the other single crystal Si, it is possible to eliminate the bias of the stress over the entire glass substrate. As a result, it is possible to obtain a substrate in which a partial region of the substrate is formed of a single-crystal Si thin film and the remaining region is formed of a polycrystalline Si thin film without peeling, cracking, or destruction of Si.
[0049]
Further, the shape of the single-crystal Si substrate is limited to a disk of 6, 8, or 12 inches, which is the wafer size of the LSI manufacturing apparatus. However, since a polycrystalline Si thin film is also formed on the insulating substrate, for example, Semiconductor devices such as large liquid crystal display panels and organic EL panels can be manufactured.
[0050]
The single-crystal Si substrate is made of SiO ₂ Since the substrate is bonded to the insulating substrate 1 at room temperature through the film, the stress acting on the bonded Si interface can be made substantially zero. Therefore, the mobility is reduced or varied due to the strain of the Si crystal due to the unevenness or variation of the stress applied to the interface, or the threshold shift or the variation due to the interface defect, the interface fixed charge, the localized level of the interface, and the characteristic. A decrease in stability or the like can be more reliably prevented.
[0051]
In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention includes a method of manufacturing a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed on an insulating substrate. ₂ A step of sequentially depositing a film and an amorphous Si film; a step of heating the amorphous Si film to grow a polycrystalline Si layer to form a polycrystalline Si thin film; The thin film is etched away and the SiO 2 in the same region is removed. ₂ A step of etching and removing a part of the film in the thickness direction; ₂ A single crystal Si substrate having a hydrogen ion implanted portion formed with a film and implanted with a predetermined concentration of hydrogen ions at a predetermined depth has a predetermined shape covering a part or substantially the entire region of the region removed by etching. A cutting step, a step of cleaning the insulating substrate and the single-crystal Si substrate and activating the surfaces of the two substrates, and a step of etching and removing the cut single-crystal Si substrate on the side where hydrogen ions are implanted. Bonding the two substrates by bringing them into close contact with each other at room temperature, and forming a single-crystal Si thin film on the insulating substrate by subjecting the substrates to cleavage by the heat treatment, thereby separating the hydrogen ion implanted portions. It is characterized by including.
[0052]
According to the above-described method, in addition to the advantages of the above-described manufacturing method, the polycrystalline Si layer in a predetermined region is removed by etching, and the SiO 2 in the same region is removed. ₂ Since a part of the film in the thickness direction is removed by etching, the SiO 2 on the attachment surface side of the single crystal Si substrate is removed. ₂ The influence of the thickness of the film is cancelled, and a substrate can be obtained in which the regions of the single-crystal Si thin film and the polycrystalline Si thin film on the insulating substrate have substantially the same height. As a result, most of the subsequent steps including the island etching can be simultaneously performed. Thus, a transistor or a circuit having a small step is formed. Therefore, for example, in the case of a liquid crystal panel, it is advantageous in controlling the cell thickness.
[0053]
In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention includes a method of manufacturing a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed on an insulating substrate. ₂ A step of depositing a film and oxidizing the surface in advance or depositing an oxide film on the ₂ Forming a film, and cutting a single crystal Si substrate having a hydrogen ion implanted portion into which a predetermined concentration of hydrogen ions are implanted at a predetermined depth into a predetermined shape; and Cleaning the two substrates, and activating the surfaces of the cut single-crystal Si substrates with the hydrogen ion-implanted surface of the insulating substrate. ₂ Forming a single-crystal Si thin film on the insulated substrate by cleaving and separating at the hydrogen ion implanted portion by heat treatment, A step of sequentially depositing an insulating film and an amorphous Si film on an insulating substrate; and a step of heating the amorphous Si film, growing a polycrystalline Si layer, and forming a polycrystalline Si thin film. Features.
[0054]
According to the above-described method, the same advantages as those of the above-described respective manufacturing methods can be obtained.
[0055]
In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention includes a method of manufacturing a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed on an insulating substrate. ₂ A step of depositing a film; ₂ A step of etching and removing a part of the film in the thickness direction; ₂ A single crystal Si substrate having a hydrogen ion implanted portion formed with a film and implanted with a predetermined concentration of hydrogen ions at a predetermined depth has a predetermined shape covering a part or substantially the entire region of the region removed by etching. A cutting step, a step of cleaning the insulating substrate and the single-crystal Si substrate and activating the surfaces of the two substrates, and a step of etching and removing the surface of the cut single-crystal Si substrate on which hydrogen ions have been implanted. A step of forming a single-crystal Si thin film by cleaving and separating at the hydrogen ion implanted portion by heat treatment, and a step of forming a single crystal Si thin film on the insulating substrate by heat treatment. The method is characterized by including a step of sequentially depositing a Si film and a step of heating the amorphous Si film, growing a polycrystalline Si layer, and forming a polycrystalline Si thin film.
[0056]
According to the above-described method, the same advantages as those of the above-described respective manufacturing methods can be obtained.
[0057]
In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention includes a method of manufacturing a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed on an insulating substrate. ₂ Film, amorphous Si film, and second SiO ₂ A step of sequentially depositing a film; ₂ Exposing a part of the amorphous Si film by etching a predetermined region of the film, and oxidizing the exposed amorphous Si film thinly (a few nm) to form an oxide film; A step of spin-coating an aqueous solution of Ni acetate on the oxide film, and a step of heating the amorphous Si film to grow a polycrystalline Si layer whose crystal growth direction is promoted by metal assist to form a polycrystalline Si thin film And the second SiO ₂ Removing the film and the oxide film, etching and removing a predetermined region of the polycrystalline Si layer, and oxidizing the surface or previously depositing an oxide film to form a SiO ₂ A single crystal Si substrate having a hydrogen ion implanted portion formed with a film and implanted with a predetermined concentration of hydrogen ions at a predetermined depth has a predetermined shape covering a part or substantially the entire region of the region removed by etching. A cutting step, a step of cleaning the insulating substrate and the single-crystal Si substrate and activating the surfaces of the two substrates, and a step of etching and removing the cut single-crystal Si substrate on the side where hydrogen ions are implanted. Bonding the two substrates by bringing them into close contact with each other at room temperature, and forming a single-crystal Si thin film on the insulating substrate by subjecting the substrates to cleavage by the heat treatment, thereby separating the hydrogen ion implanted portions. It is characterized by including.
[0058]
According to the above-described method, the same advantages as those of the above-described respective manufacturing methods can be obtained.
[0059]
In the above method for manufacturing a semiconductor device, it is preferable that the heat treatment be performed in one or multiple temperature steps of 300 ° C. or more and 650 ° C. or less.
[0060]
According to the above method, the heat treatment can be performed in one temperature step, that is, in one process.
[0061]
In the method of manufacturing a semiconductor device described above, it is preferable that at least one of Ni, Pt, Sn, and Pd is added to the amorphous Si film when growing the polycrystalline Si layer.
[0062]
According to the above method, at the time of growing the polycrystalline Si layer, at least one of Ni, Pt, Sn, and Pd is added to the amorphous Si film, and then the polycrystalline Si layer is heated. Crystal growth can be promoted. Therefore, the mobility of the polycrystalline Si layer can be increased, which is advantageous in forming a driving circuit.
[0063]
In the method for manufacturing a semiconductor device, the temperature of the hydrogen ion implanted portion of the single crystal Si substrate is increased by laser irradiation to a temperature equal to or higher than the temperature at which hydrogen is released from Si, so that the single crystal Si substrate is heated by the hydrogen ion implanted portion. It is preferable to perform a step of cleaving at the boundary.
[0064]
According to the above method, since the temperature of the hydrogen ion implanted portion of the single crystal Si substrate is increased by laser irradiation, it is possible to increase the temperature only in a narrow range, thereby suppressing damage to the single crystal Si. Wear.
[0065]
In the above semiconductor device, it is preferable that the single crystal Si substrate be separated from the hydrogen ion implanted portion by performing lamp annealing including a peak temperature of approximately 700 ° C. or higher.
[0066]
According to the above-described method, lamp annealing, which is rapid thermal annealing including a peak temperature of approximately 700 ° C. or more, is performed, and the single crystal Si substrate is separated from the hydrogen ion implanted portion, so that the bonding strength is further increased. And the characteristics of the transistor can be improved by recovering from damage caused by hydrogen ion implantation inside the peeling interface and inside the single crystal Si thin film. Note that the higher the peak temperature of the lamp annealing, the higher the characteristics of the transistor, but the larger the warpage and expansion / contraction of the substrate. Therefore, an appropriate temperature and holding time may be selected depending on the substrate size and the type of device to be formed.
[0067]
In the method of manufacturing a semiconductor device described above, after a polycrystalline Si thin film and a single-crystal Si thin film are formed on an insulating substrate, a damaged layer on the surface of the single-crystal Si thin film is removed by isotropic plasma etching or wet etching. A step of patterning the polycrystalline Si thin film and the single-crystal Si thin film in an island shape by etching; ₂ After depositing the film, anisotropic etching is performed to etch back SiO ₂ Etching back all or part of the film while leaving a part of the film; ₂ A step of forming a gate insulating film by depositing a film.
[0068]
According to the above method, a general polysilicon TFT forming step is performed, so that a TFT having the above characteristics can be manufactured using a conventional step.
[0069]
In the method of manufacturing a semiconductor device, after the polycrystalline Si thin film and the single crystal Si thin film are formed on an insulating substrate, the damaged layer on the surface of the single crystal Si thin film is removed by isotropic plasma etching or wet etching. A step of etching and removing, a step of patterning the polycrystalline Si thin film and the single crystal Si thin film in an island shape by etching, and a step of etching back SiO2 on the entire surface of the polycrystalline Si thin film and the single crystal Si thin film. ₂ After depositing the film, a step of further applying a resin flattening film on the entire surface, and anisotropic etching to completely cover the resin flattening film and the SiO for etching back ₂ Etching back a part of the film; ₂ A step of forming a gate insulating film by depositing a film.
[0070]
According to the above method, the oxide film (SiO 2) is formed in the valley between the patterns of the polycrystalline Si thin film and the single crystal Si thin film. ₂ Film), and the entire substrate can be flattened.
[0071]
In the method of manufacturing a semiconductor device, the single crystal Si thin film and the polycrystalline Si thin film formed on an insulating substrate are patterned into an island shape by etching to form a MOS transistor, and an N-type MOS transistor and a P-type MOS transistor At least a portion of the source and drain regions of ^Fifteen / Cm ² 5 × 10 or more ^Fifteen / Cm ² The following P ⁺ Preferably, the method further includes a step of implanting ions.
[0072]
According to the above method, at least part of the source and drain regions of the N-type MOS transistor and the P-type MOS transistor ^Fifteen / Cm ² 5 × 10 or more ^Fifteen / Cm ² The following P ⁺ Implant ions. Therefore, after that, a heat treatment is performed by RTA, a laser, a furnace, or the like, and the metal atoms are simultaneously gettered not only in the polycrystalline Si thin film region but also in the single crystal Si thin film region, so that a TFT having a smaller characteristic variation and a stable characteristic is obtained. Can be obtained.
[0073]
In the method of manufacturing a semiconductor device described above, it is preferable that the thickness of the single-crystal Si thin film is approximately equal to the thickness of the polycrystalline Si thin film.
[0074]
According to the above method, most of the subsequent steps including the etching for forming an island pattern can be simultaneously performed, and a transistor or a circuit having a small step can be formed. Therefore, for example, in the case of a liquid crystal panel, it is advantageous in controlling the cell thickness.
[0075]
The above-described method for manufacturing a semiconductor device includes a method of forming a SiO 2 layer on a surface of a single-crystal Si substrate, ₂ The thickness of the film is preferably 200 nm or more, more preferably 300 nm or more.
[0076]
Usually SiO ₂ As the thickness of the film increases, the variation in the threshold value decreases. ₂ An appropriate value is approximately 200 nm to 400 nm due to the trade-off between the efficiency (time required for oxidation) of the film forming process and the step. An appropriate value is about 400 nm or more when variation is important, and about 200 nm to 400 nm, more preferably 250 nm to 350 nm when importance is placed on steps and efficiency. SiO ₂ When the thickness of the film is large, the stability of operation particularly at a low voltage is improved. This is because the influence of the fixed charge caused by the contamination of the interface between the bonded single crystal Si substrate and the insulating substrate such as a glass substrate or the lattice distortion or imperfection is reduced.
[0077]
Therefore, according to the above method, the variation in the threshold value and the variation in SiO 2 ₂ A semiconductor substrate that is appropriate for the efficiency of the film forming process and the balance with the step can be obtained.
[0078]
In the above method for manufacturing a semiconductor device, the maximum size of the single-crystal Si thin film is preferably 10 cm or less.
[0079]
According to the above method, if the maximum size of the single-crystal Si thin film is 10 cm or less, the difference in the thermal expansion coefficient between the single-crystal Si and the single-crystal Si is larger than that of the quartz substrate. Even when the high strain point glass is used, breakage such as cracks and peeling of Si can be prevented. The maximum dimension of the single-crystal Si thin film means the largest dimension among the respective dimensions in the surface shape of the single-crystal Si thin film having a small thickness. For example, when the single-crystal Si thin film is circular, it means the diameter, and when the single-crystal Si thin film is thin, rectangular, it means the diagonal length of the upper surface square shape.
[0080]
In the above method for manufacturing a semiconductor device, it is preferable that the maximum size of the single crystal Si thin film is 5 cm or less.
[0081]
According to the above method, if the maximum size of the single-crystal Si thin film is 5 cm or less, the difference in the thermal expansion coefficient between the single-crystal Si and the single-crystal Si is larger than that of the quartz substrate. Even if the high strain point glass used for the above is used, it is possible to further prevent breakage such as cracks and peeling of Si.
[0082]
In the method of manufacturing a semiconductor device described above, it is preferable that the standardized linear expansion difference between the single crystal Si thin film and the insulating substrate is approximately 250 ppm or less in a temperature range of approximately room temperature to 600 ° C.
[0083]
According to the above method, the difference in linear expansion coefficient between the insulating substrate and the single-crystal Si thin film is reduced. Therefore, in the process for forming a single-crystal Si thin film on an insulating substrate, it is necessary to surely prevent destruction, bonding interface separation, or generation of defects in the crystal in the cleavage separation process from the hydrogen implantation position due to the difference in thermal expansion coefficient. In addition, the heat bonding strength can be improved.
[0084]
In the above method for manufacturing a semiconductor device, the dose of hydrogen ions implanted into the hydrogen ion implanted portion is 10 ¹⁶ / Cm ² Above, furthermore, approximately 3 × 10 ¹⁶ / Cm ² It is preferable that
[0085]
According to the above method, characteristics such as mobility of the TFT formed in the region of the single crystal Si thin film can be improved.
[0086]
BEST MODE FOR CARRYING OUT THE INVENTION
[Embodiment 1]
One embodiment of the present invention will be described below with reference to FIGS.
[0087]
FIG. 1 shows an example of a manufacturing process of the active matrix substrate 20 (semiconductor device) according to the present embodiment. As shown in FIG. 1H, the present active matrix substrate 20 includes an insulating substrate 1, SiO ₂ (Silicon oxide) films 2 and 11, a polycrystalline Si thin film 4, a single crystal Si thin film 5, a gate oxide film 6, a gate electrode 21, an interlayer insulating film 22, and a metal wiring 24 are provided. The active matrix substrate 20 includes a thin film transistor (TFT) that is a switching element. The active matrix substrate 20 is used for, for example, a liquid crystal display device.
[0088]
The insulating substrate 1 is made of high strain point glass. Here, as the insulating substrate 1, a code 1737 (manufactured by Corning) made of alkaline earth-aluminoborosilicate glass is used.
[0089]
The material of the insulating substrate 1 is not particularly limited, and barium-aluminoborosilicate glass, borosilicate glass, alkaline earth-zinc-lead-aluminoborosilicate glass, which is a high strain point glass, alkaline earth Class-zinc-aluminoborosilicate glass or the like.
[0090]
On almost the entire surface of the insulating substrate 1, SiO ₂ SiO consisting of ₂ A film 2 is formed. SiO ₂ The thickness of the film 2 is about 100 nm.
[0091]
SiO ₂ On the film 2, a polycrystalline Si thin film 4 and SiO ₂ A film 11 is formed. The polycrystalline Si thin film 4 is formed to have an island pattern, and has a thickness of about 50 nm. SiO ₂ The film 11 is made of SiO ₂ It is formed on the film 2 in a region different from the polycrystalline Si thin film 4 so as to form an island pattern, and its film thickness is about 200 nm. SiO ₂ On the film 11, a single-crystal Si thin film 5 having the same shape is further formed so as to form an island pattern. The thickness of the single-crystal Si thin film 5 is about 50 nm.
[0092]
The region of the adjacent polycrystalline Si thin film 4 and the region of the single crystal Si thin film 5 are separated by at least 0.3 μm, preferably 0.5 μm or more.
[0093]
This prevents metal atoms such as Ni, Pt, Sn, and Pd used in a later-described manufacturing process of the polycrystalline Si thin film 4 from diffusing into the single-crystal Si region, thereby stabilizing characteristics. it can.
[0094]
SiO ₂ Over the entire surface of the film 2, the polycrystalline Si thin film 4, and the single-crystal Si thin film 5, ₂ A gate oxide film 6 is formed. The thickness of the gate oxide film 6 is about 60 nm.
[0095]
A gate electrode 21 is formed on the gate oxide film 6 on the upper surface of each island pattern region in the polycrystalline Si thin film 4 and the single crystal Si thin film 5. Gate electrode 21 is made of polycrystalline Si and W silicide. The material of the gate electrode 21 is not particularly limited, and may be, for example, polycrystalline Si, another silicide, polycide, a high melting point metal, or the like.
[0096]
The entire surface of the gate oxide film 6 on which the gate electrode 21 is formed is SiO 2 ₂ Is formed. However, the interlayer insulating film 22 has a contact hole 23 (see FIG. 1 (g)) as an opening, and a metal wiring 24 made of a metal such as AlSi is formed in the contact hole 23. The metal wiring 24 is formed from the upper surface of each island pattern region in the polycrystalline Si thin film 4 and the single crystal Si thin film 5.
[0097]
Further, the active matrix substrate 20 is formed with a not-shown SiNx (silicon nitride), a resin flattening film, a via hole, a transparent electrode, and the like for a liquid crystal display. In the polycrystalline Si thin film region, a driver and a TFT for a display portion are formed, and in the single crystal Si thin film region, a timing controller, a microprocessor, and the like for controlling each timing of driving by the driver are formed. Of course, the driver may be formed of single crystal Si. In this case, the performance is further improved, the device area is smaller, the uniformity is excellent, the operation is performed at a lower voltage, but the cost is increased.
[0098]
Hereinafter, a method for manufacturing the active matrix substrate 20 will be described with reference to FIGS. 1 (a) to 1 (h).
[0099]
First, TEOS (Tetra Ethoxy Silane, that is, Si (OC) is formed on the entire surface of the insulating substrate 1 made of the code 1737 (manufactured by Corning). ₂ H ₅ ) ₄ ) And O ₂ (Oxygen) and a 100-nm-thick SiO 2 film by a plasma chemical vapor deposition (P-CVD) method. ₂ The film 2 is deposited.
[0100]
Subsequently, the SiO ₂ SiH on the film 2 ₄ An amorphous Si film 3 having a thickness of about 50 nm is deposited by a P-CVD method using a gas (FIG. 1A).
[0101]
Then, the amorphous Si film 3 is irradiated with an excimer laser and heated to crystallize the amorphous Si, and a polycrystalline Si layer is grown to form a polycrystalline Si thin film 4.
[0102]
The heating of the amorphous Si film 3 for forming the polycrystalline Si thin film 4 is not limited to irradiation heating with an excimer laser. For example, irradiation heating with another laser may be performed by heating using a furnace. There may be. Further, in order to promote crystal growth, at least one of Ni, Pt, Sn, and Pd may be added to the amorphous Si film 3.
[0103]
Next, a predetermined region of the polycrystalline Si thin film 4 is removed by etching (FIG. 1B).
[0104]
On the other hand, a single crystal Si substrate 10 is prepared. The single crystal Si substrate 10 has its surface oxidized in advance or an oxide film (SiO 2 ₂ Film) to form a SiO 2 film having a thickness of about 200 nm. ₂ A film 11 is formed. In addition, the single-crystal Si substrate 10 ¹⁶ / Cm ² Above, here 5 × 10 ¹⁶ / Cm ² Of hydrogen ions at a predetermined energy (here, about 24 keV). ^Fifteen cm ^-3 Doped. The threshold of the N-channel TFT is set to an appropriate value by the boron-concentration impurity.
[0105]
Then, the polycrystalline Si thin film 4 is formed into a shape at least 0.3 μm, preferably at least 0.5 μm smaller than the shape of the predetermined region by etching, by dicing or anisotropic etching with KOH or the like to form the single crystal Si The substrate 10 is cut.
[0106]
Subsequently, both the substrate on which the polycrystalline Si thin film 4 is formed and the single-crystal Si substrate 10 are washed and activated with SC-1 for particle removal and surface activation, and then the cut single-crystal Si substrate is cut. The surface of the substrate 10 on the side close to the hydrogen ion implanted portion 12 is brought into close contact with the region removed by etching (FIG. 1B) at room temperature and joined (FIG. 1C). Here, SC-1 cleaning is one of the cleaning methods generally called RCA cleaning, and is performed using a cleaning liquid including ammonia, hydrogen peroxide, and pure water.
[0107]
Thereafter, heat treatment is performed at a temperature of 300 ° C. to 600 ° C., about 550 ° C. in this case, and the temperature of the hydrogen ion implanted portion 12 of the single crystal Si substrate 10 is raised to a temperature at which hydrogen is released from Si or higher. As a result, the single crystal Si substrate 10 is cleaved off at the hydrogen ion implanted portion 12.
[0108]
The heat treatment is not particularly limited. For example, by using laser irradiation or lamp annealing including a peak temperature of about 700 ° C. or more, the temperature of the hydrogen ion The temperature may be raised to a temperature higher than the temperature at which hydrogen desorbs from.
[0109]
Then, the damaged layer on the surface of the single crystal Si substrate that has been peeled off and remains on the insulating substrate 1 is lightly etched by about 20 nm by isotropic plasma etching or wet etching, here, isotropic plasma etching using buffered hydrofluoric acid. To remove. Thus, a polycrystalline Si thin film 4 and a single-crystal Si thin film 5 each having a thickness of about 50 nm are obtained on the insulating substrate 1. (FIG. 1 (d)).
[0110]
Note that, in the above bonding step (see FIG. 1C), after bonding the single-crystal Si substrate 10 at room temperature, heat-treating it at 300 to 350 ° C. for about 30 minutes, and then heat-treating it at about 550 ° C. to cleave it. Peeling due to cleavage peeling was reduced.
[0111]
At this point, sufficient bonding strength between the Si and the substrate is already obtained. To further improve the bonding strength, for example, lamp annealing may be performed at about 800 ° C. for 1 minute. This may also serve as activation of the source / drain implanted impurities.
[0112]
Next, an island-like pattern is obtained by removing unnecessary portions of the Si thin films 4 and 5 by etching while leaving a portion to be an active region of the device (FIG. 1E).
[0113]
Then, TEOS and O ₂ Using a mixed gas of (oxygen) and a P-CVD method, a SiO ₂ Film (SiO for etch back) ₂ A film is deposited and etched back by about 400 nm by RIE (reactive ion etching) which is anisotropic etching. Then, SiH ₄ And N ₂ A 60-nm-thick gate oxide film 6 (SiO 2) is formed by a P-CVD method using a mixed gas with O. ₂ (FIG. 1F).
[0114]
At this time, when the space between the formed patterns of the polycrystalline Si thin film 4 and the single-crystal Si thin film 5 is small, the step is filled, and when it is large, the side wall is formed.
[0115]
Thereafter, it may be formed by the same process as the process of forming a well-known p-Si (polycrystalline silicon) type TFT matrix substrate. That is, after forming a gate electrode 21 made of polycrystalline Si, silicide, polycide or the like, ⁺ And B ⁺ Is ion-implanted to form an interlayer insulating film (SiO 2). ₂ A film 22 is deposited, and a contact hole 23 is opened (FIG. 1G). Thereafter, a metal (AlSi) wiring 24 is formed in the contact hole 23 (FIG. 1H).
[0116]
The MOS transistor is formed by etching the single crystal Si thin film 5 and the polycrystalline Si thin film 4 formed on the insulating substrate 1 into an island shape, and the source and drain regions of the N-type MOS transistor and the P-type MOS transistor are formed. About 10 for at least part of ^Fifteen / Cm ² Above P ⁺ Implant ions. Thereby, after that, heat treatment is performed by an instantaneous thermal annealing (Rapid Thermal Anneal, hereinafter referred to as RTA), a laser, a furnace, or the like, so that not only the polycrystalline Si thin film 4 regions but also the single crystal Si thin film 5 regions are simultaneously formed with metal atoms. By performing gettering, it is possible to obtain a TFT having small characteristic variations and stable characteristics.
[0117]
Subsequently, SiNx (silicon nitride), a resin flattening film, a via hole, and a transparent electrode are sequentially formed for a liquid crystal display. Then, a driver and a TFT for a display section are formed in the polycrystalline Si thin film 4 region, and a timing controller, a microprocessor and the like are formed in the single crystal Si thin film 5 region.
[0118]
By the way, after the above-mentioned single-crystal Si substrate 10 is brought into close contact with and bonded to the insulating substrate 1, when the single-crystal Si substrate 10 is cleaved from the insulating substrate 1 by heat treatment (see FIGS. 1C and 1D), the bonding is performed. Whether the cleavage separation is good depends on the material of the insulating substrate 1.
[0119]
Here, based on FIG. 6, the material of the single crystal Si substrate 10 (Si: Silicon), the material of the insulating substrate 1 (code 1737 (manufactured by Corning Incorporated)), and the code 7059 made of barium-borosilicate glass (Corning Incorporated) ) Standardized linear expansion (ΔL / L) will be described. Note that the normalized linear expansion (hereinafter, referred to as linear expansion) is a change in length (ppm) caused by a temperature change. That is, L is the original length, and ΔL is the extended (changed) length.
[0120]
Thus, code 1737 has a linear expansion coefficient (° C.) up to about 600 ° C. ^-1 ) Is substantially constant, there is almost no difference in linear expansion between code 1737 and Si, and within a range from room temperature (about 25 ° C. (about 100 ° C. or more in FIG. 6)) to about 600 ° C. The difference in expansion is within about 250 ppm.
[0121]
On the other hand, the coefficient of linear expansion of code 7059 increases rapidly at about 600 ° C., and the difference in linear expansion between code 7059 and Si increases to about 800 ppm at about 600 ° C.
[0122]
For this reason, when code 7059 is used for the insulating substrate 1, the success rate of cleavage and peeling is much lower even if bonding can be performed in the same manner as when code 1737 is used. That is, when cleaved and separated, the single crystal Si substrate 10 may be broken, the bonding interface may be separated, or a defect may occur in the crystal.
[0123]
As described above, as a material of the insulating substrate 1, a difference in linear expansion from a material to be joined, here, the material (Si) of the single crystal Si substrate 10, in a temperature range of about room temperature or more and about 600 ° C. or less. Is about 250 ppm or less. Here, the linear expansion is standardized.
[0124]
Further, the stress acting on the bonding interface of the single-crystal Si thin film 5 will be considered. Here, the Raman shift of the single-crystal Si thin film 5 was measured by a microscopic Raman measuring device (for example, NR-1800U manufactured by JASCO Corporation). In this case, the shift amount of the Raman peak is 520.52 cm ^-1 (Kaiser), σ = 0.12cm ^-1 It became. Therefore, it is understood that no stress is acting on the single crystal Si thin film 5.
[0125]
Usually, when a crystal is grown using a laser, the shift amount of the Raman peak is 3 to 5 cm. ^-1 Degree (10 ⁹ (Corresponding to Pa).
[0126]
On the other hand, the single-crystal Si substrate 10 ₂ Since it is bonded to the insulating substrate 1 such as a glass substrate at room temperature through the film, the stress acting on the bonded Si interface can be substantially reduced to zero. That is, the shift amount of the Raman peak is set to 520.5 ± 1 (519.5 to 521.5) cm. ^-1 , The stress acting on the bonded Si interface becomes substantially zero.
[0127]
As a result, compared with a TFT in which a Si film is crystal-grown by using a laser, a decrease in mobility or a variation due to strain of the Si crystal due to unevenness or variation in stress acting on the interface, or a defect at the interface. It is possible to more reliably prevent a threshold shift and variation due to an interface fixed charge and a localized level of the interface, a decrease in characteristic stability, and the like.
[0128]
In the present embodiment, when the implantation energy of hydrogen ions is increased to increase the peak position of hydrogen atoms and increase the thickness of the single-crystal Si thin film 5, there is no significant change from 50 nm to 100 nm, but from 300 nm to 600 nm. When the channel width is increased, the channel portion is not completely depleted, so that the S value (sub-threshold coefficient) of the TFT gradually increases, and the off-state current significantly decreases.
[0129]
Accordingly, the thickness of the single-crystal Si thin film 5 depends on the doping density of impurities in the channel portion, but is required to be approximately 600 nm or less, preferably approximately 500 nm or less, and more preferably 100 nm or less in consideration of a margin for variation. There is.
[0130]
The mobility (carrier mobility) of a TFT formed in a conventional polycrystalline Si region is about 100 cm. ² / V · sec (N channel), whereas in the liquid crystal display active matrix substrate 20, the TFT formed in the single crystal Si region is about 550 cm. ² / V · sec (N channel) mobility was obtained.
[0131]
Further, in the active matrix substrate 20 for liquid crystal display, the device formed in the region of the polycrystalline Si thin film 4 as well as the driver requires a signal of 7 to 8 V and a power supply voltage, while the device of the single crystal Si thin film 5 The devices such as the timing controller and the microprocessor formed in the region operated stably at 3.3V.
[0132]
In the liquid crystal display active matrix substrate 20, the transistors are formed in the region of the polycrystalline Si thin film 4 and the region of the single crystal Si thin film 5, so that the transistors of the same conductivity type formed in the respective regions are formed. , At least one of the mobility, the sub-threshold coefficient, and the threshold is different for each region. Therefore, a transistor can be formed in a region appropriate for required characteristics.
[0133]
In the liquid crystal display active matrix substrate 20, the integrated circuit is formed in the region of the polycrystalline Si thin film 4 and the region of the single crystal Si thin film 5, so that the integrated circuit can be adapted to the required configuration and characteristics. Can be formed in suitable regions, and in the integrated circuits formed in the respective regions, naturally, integrated circuits having different performances such as operating speed and operating power supply voltage can be produced. That is, at least one of the gate length, the thickness of the gate oxide film, the power supply voltage, and the logic level can be designed differently for each region.
[0134]
In the liquid crystal display active matrix substrate 20, the integrated circuit is formed in the region of the polycrystalline Si thin film 4 and the region of the single crystal Si thin film 5, so that the integrated circuit formed in each region is Can be applied with different processing rules. This is because, for example, especially in the case of a short channel length, the variation in TFT characteristics hardly increases because there is no crystal grain boundary in the single crystal portion, whereas the variation rapidly increases in the polycrystal portion due to the influence of the crystal grain boundary. This is because it is necessary to change the processing rule in each part in order to increase. Therefore, the integrated circuit can be formed in an appropriate region according to the processing rule.
[0135]
In the present invention, the size of the obtained single-crystal Si region is limited by the wafer size of the LSI manufacturing apparatus, but is limited. However, high-speed logic and timing generators which require the high-speed, power consumption, and variation that require the single-crystal Si region are required. , A high speed DAC (current buffer), etc.
[0136]
Further, the thickness of the single-crystal Si thin film 5 and the thickness of the polycrystalline Si thin film 4 are substantially equal.
[0137]
This makes it possible to simultaneously perform most of the subsequent steps including the island pattern etching, and to form a transistor or a circuit having a small step. Therefore, for example, in the case of a liquid crystal panel, it is advantageous in controlling the cell thickness.
[0138]
By the way, in the active matrix substrate 20, the gate lengths of the TFTs formed in the polycrystalline Si region (on the polycrystalline Si thin film 4) and the single crystal Si region (the single crystal Si thin film 5) are 5 μm, 0.8 μm, When the oxide film thickness was set to 80 nm and 50 nm, and the power supply voltage was operated at 8 V and 3 V, respectively, the operation was stable.
[0139]
On the other hand, when a TFT having a gate length of 0.8 μm was formed in a polycrystalline Si region and operated at 3 V, the characteristics of the TFT fluctuated, and the withstand voltage between the source and the drain was insufficient and the TFT could not be used. There were many.
[0140]
Further, when a TFT having a gate length of 1.5 μm was formed in a polycrystalline Si region and operated at 3 V, the threshold voltage and its variation were large, and there was a practical problem.
[0141]
[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIG. Note that, in the present embodiment, components having the same functions as the components in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
[0142]
FIG. 2 shows an example of a manufacturing process of the active matrix substrate 30 (semiconductor device) according to the present embodiment. As shown in FIG. 2H, the present active matrix substrate 30 is composed of an insulating substrate 1, SiO 2 ₂ (Silicon oxide) films 32, 11 and 35, polycrystalline Si thin film 37, single crystal Si thin film 34, gate oxide film 38, gate electrode 21, interlayer insulating film 22, and metal wiring 24 are provided. Further, the active matrix substrate 30 includes a thin film transistor (TFT) that is a switching element.
[0143]
On the surface of the insulating substrate 1 similar to that of the first embodiment, SiO ₂ SiO consisting of ₂ Film (first SiO) ₂ A film 32 is formed. SiO ₂ The thickness of the film 32 is about 350 nm.
[0144]
SiO ₂ On the film 32, SiO ₂ Film (insulating film) 35 and SiO ₂ A film 11 is formed. SiO ₂ The thickness of the film 35 is about 100 nm. SiO ₂ The film 11 is made of SiO ₂ SiO 2 on the film 32 ₂ It is formed so as to form an island pattern in a region different from the film 35, and its film thickness is about 200 nm.
[0145]
SiO ₂ On the film 35, a polycrystalline Si thin film 37 is further formed so as to have an island pattern. The thickness of the polycrystalline Si thin film 37 is about 50 nm.
[0146]
SiO ₂ The film 32 has a concave portion 33 (see FIG. 2A) having a depth of about 150 nm in a region different from the region of the polycrystalline Si thin film 37. The recess 33 has the above SiO ₂ The film 11 and further thereon SiO 2 ₂ A single-crystal Si thin film 34 having the same shape as the film 11 is formed to have an island pattern.
[0147]
The region of the polycrystalline Si thin film 37 and the region of the single crystal Si thin film 34 are separated by at least 0.3 μm, preferably 0.5 μm or more. This can prevent metal atoms such as Ni, Pt, Sn, and Pd from diffusing into the single crystal Si region and stabilize characteristics.
[0148]
SiO ₂ A gate oxide film 36 is formed over the entire surface of the film 32, the polycrystalline Si thin film 37, and the single crystal Si thin film 34. The thickness of the gate oxide film 36 is about 60 nm.
[0149]
A gate electrode 21 is formed on the gate oxide film 36 on the upper surface of each island pattern region in the polycrystalline Si thin film 37 and the single crystal Si thin film 34.
[0150]
Similarly to the active matrix substrate 20, an interlayer insulating film 22, a contact hole 23 (see FIG. 2G), and a metal wiring 24 are formed. Further, similarly, the active matrix substrate 20 is formed with SiNx (silicon nitride), a resin flattening film, a via hole, and a transparent electrode for liquid crystal display, and a polycrystalline Si region for a driver and a display unit. A TFT is formed, and a timing controller, a microprocessor, and the like are formed in a single crystal Si region.
[0151]
Hereinafter, a method for manufacturing the active matrix substrate 30 will be described with reference to FIGS.
[0152]
First, TEOS (Tetra Ethoxy Silane, that is, Si (OC) is formed on the entire surface of the insulating substrate 1 made of code 1737 (manufactured by Corning). ₂ H ₅ ) ₄ ) And O ₂ (Oxygen) and a P-CVD method using a mixed gas consisting of ₂ A film 32 is deposited. And SiO ₂ A predetermined region of the film 32 is etched by about 150 nm to form a concave portion 33 (FIG. 2A).
[0153]
On the other hand, a single crystal Si substrate 10 is prepared. The single crystal Si substrate 10 has its surface oxidized in advance or an oxide film (SiO 2 ₂ Film) to form a SiO 2 film having a thickness of about 200 nm. ₂ A film 11 is formed. The single-crystal Si substrate 10 has a size of 5 × 10 ¹⁶ / Cm ² And a hydrogen ion implanted portion 12 in which hydrogen ions of a dose of about 3 × 10 ^Fifteen cm ^-3 Doped.
[0154]
Then, the single-crystal Si substrate 10 is cut into a shape at least 0.3 μm, preferably 0.5 μm or more smaller than the concave portion 33 by dicing or anisotropic etching using KOH or the like.
[0155]
Subsequently, both the insulating substrate 1 in which the concave portion 33 is formed and the single-crystal Si substrate 10 are cleaned and activated with SC-1 to remove particles and activate the surface, and then the cut single-crystal Si substrate is cut. The surface on the side closer to the hydrogen ion implanted portion 12 is brought into close contact with the concave portion 33 at room temperature and joined (FIG. 2B).
[0156]
Thereafter, heat treatment is performed at a temperature of 300 ° C. to 600 ° C., about 550 ° C. in this case, and the temperature of the hydrogen ion implanted portion 12 of the single crystal Si substrate 10 is raised to a temperature at which hydrogen is released from Si or higher. As a result, the single crystal Si substrate 10 is cleaved off at the hydrogen ion implanted portion 12.
[0157]
Then, the damaged layer on the surface of the single crystal Si substrate that has been peeled off and remains on the insulating substrate 1 is lightly etched by about 10 nm by isotropic plasma etching or wet etching, here, isotropic plasma etching using buffered hydrofluoric acid. To remove. Thus, a single-crystal Si thin film 34 having a thickness of about 50 nm is obtained on the insulating substrate 1. (FIG. 2 (c)).
[0158]
Subsequently, over substantially the entire surface of the insulating substrate 1, then, ₄ And N ₂ Using a mixed gas of O and a P-CVD method, a SiO ₂ A film 35 is deposited, and over substantially the entire surface thereof, SiH ₄ An amorphous Si film 36 having a thickness of about 50 nm is deposited by a P-CVD method using a gas (FIG. 2D).
[0159]
Then, the amorphous Si film 36 is irradiated with an excimer laser and heated to crystallize the amorphous Si, and a polycrystalline Si layer is grown, thereby forming a polycrystalline Si thin film 37. By this heating, the bonding strength of the single crystal Si thin film 34 can be improved.
[0160]
Next, unnecessary portions of the polycrystalline Si thin film 37 and SiO 2 ₂ At least a portion of the film 35 on the single crystal Si thin film 34 is removed by etching. Thereafter, an unnecessary Si film is removed by etching, leaving a portion to be an active region of the device, thereby forming an island-like pattern (FIG. 2E).
[0161]
And TEOS and O ₂ Of about 350 nm in film thickness by a P-CVD method using a mixed gas of ₂ A film is deposited, and this is etched back by about 400 nm by RIE which is anisotropic etching. Then, SiH ₄ And N ₂ A gate oxide film 38 having a thickness of about 60 nm is formed by a P-CVD method using a mixed gas with O (FIG. 2F).
[0162]
At this time, when the space between the formed patterns of the polycrystalline Si thin film 34 and the single-crystal Si thin film 37 is small, the step is filled, and when it is large, the side wall is formed.
[0163]
Thereafter, as in the first embodiment, the gate electrode 21 and the interlayer insulating film (SiO ₂ After forming a film 22 and opening a contact hole 23 (FIG. 2G), a metal wiring 24 is formed in the contact hole 23 (FIG. 2H).
[0164]
Here, a conventional N-channel TFT formed in a polycrystalline silicon region has a mobility of about 100 cm. ² / V · sec, whereas in the active matrix substrate 30, the N-channel TFT formed in the single-crystal Si region is about 550 cm ² / V · sec.
[0165]
In the active matrix substrate 30, the device formed in the region of the polycrystalline Si thin film 37 as well as the driver requires a signal of 7 to 8 V and a power supply voltage, whereas the device formed in the region of the single crystal Si thin film 34 The timing controller, microprocessor, etc. operated stably at 3.3V.
[0166]
[Embodiment 3]
The following will describe another embodiment of the present invention with reference to FIG. In the present embodiment, components having the same functions as those in the second embodiment are denoted by the same reference numerals, and description thereof is omitted.
[0167]
FIG. 3 shows an example of a manufacturing process of the active matrix substrate (semiconductor device) according to the present embodiment. As shown in FIG. 3F, the present active matrix substrate includes an insulating substrate 1, SiO 2 ₂ (Silicon oxide) films 62, 11 and 35, a polycrystalline Si thin film 67, a single-crystal Si thin film 64, and a gate oxide film 68. The active matrix substrate includes a thin film transistor (TFT), a gate electrode, an interlayer insulating film, and metal wiring (not shown), as in the first and second embodiments.
[0168]
On the surface of the insulating substrate 1 similar to that of the second embodiment, SiO ₂ SiO consisting of ₂ Film (first SiO) ₂ A film 62 is formed. SiO ₂ The thickness of the film 62 is about 50 nm.
[0169]
SiO ₂ On the film 62, SiO ₂ Film (insulating film) 35 and SiO ₂ A film 11 is formed. SiO ₂ The thickness of the film 35 is about 100 nm. SiO ₂ The film 11 is made of SiO ₂ On the film 62, ₂ It is formed so as to form an island pattern in a region different from the film 35, and its film thickness is about 200 nm.
[0170]
SiO ₂ On the film 11, SiO ₂ A single-crystal Si thin film 64 having the same shape as the film 11 is formed in an island pattern. The thickness of the single-crystal Si thin film 64 is about 100 nm. In addition, SiO ₂ On the film 35, a polycrystalline Si thin film 67 is formed in an island pattern. The thickness of the polycrystalline Si thin film 67 is about 50 nm.
[0171]
SiO ₂ A gate oxide film 68 is formed over the entire surface of the film 62, the polycrystalline Si thin film 67, and the single-crystal Si thin film 64. The thickness of the gate oxide film 68 is about 60 nm.
[0172]
Further, a gate electrode (not shown) is formed on the gate oxide film 68 on the upper surface of each island pattern region in the polycrystalline Si thin film 67 and the single crystal Si thin film 64. The gate electrode is similar to the active matrix substrate 30 of the second embodiment, and is made of, for example, polycrystalline Si, silicide, polycide, or the like.
[0173]
Further, similarly to the active matrix substrate 30, an interlayer insulating film (not shown), a contact hole, and a metal wiring (not shown) are formed. Further, similarly, for liquid crystal display, SiNx (silicon nitride), a resin flattening film, a via hole, and a transparent electrode are formed, and a TFT for a driver and a display unit is formed in a polycrystalline Si region. A timing controller, a microprocessor and the like are formed in the crystalline Si region.
[0174]
Hereinafter, a method of manufacturing the active matrix substrate according to the above-described embodiment will be described with reference to FIGS.
[0175]
First, TEOS (Tetra Ethoxy Silane, that is, Si (OC) is formed on the entire surface of the insulating substrate 1 made of code 1737 (manufactured by Corning). ₂ H ₅ ) ₄ ) And O ₂ (Oxygen) and a 50-nm-thick SiO 2 film by a P-CVD method. ₂ A film 62 is deposited (FIG. 3A).
[0176]
On the other hand, a single-crystal Si substrate 10 that has been cut into an appropriate shape in advance is prepared. The single crystal Si substrate 10 has its surface oxidized in advance or an oxide film (SiO 2 ₂ Film) to form a SiO 2 film having a thickness of about 200 nm. ₂ A film 11 is formed. The single-crystal Si substrate 10 has a size of 5 × 10 ¹⁶ / Cm ² And a hydrogen ion implanted portion 12 in which hydrogen ions of a dose of about 3 × 10 ^Fifteen cm ^-3 Doped.
[0177]
Then, both the insulating substrate 1 and the single-crystal Si substrate 10 are cleaned and activated with SC-1 for particle removal and surface activation, and then the hydrogen ion implanted portion 12 of the cut single-crystal Si substrate 10 is cut. The surface on the side closer to is bonded to the insulating substrate 1 at room temperature and joined (FIG. 3B).
[0178]
Thereafter, heat treatment is performed at a temperature of 300 ° C. to 600 ° C., about 550 ° C. in this case, and the temperature of the hydrogen ion implanted portion 12 of the single crystal Si substrate 10 is raised to a temperature at which hydrogen is released from Si or higher. As a result, the single crystal Si substrate 10 is cleaved off at the hydrogen ion implanted portion 12.
[0179]
Then, the damaged layer on the surface of the single crystal Si substrate that has been peeled off and remains on the insulating substrate 1 is lightly etched by about 20 nm by isotropic plasma etching or wet etching, here, isotropic plasma etching using buffered hydrofluoric acid. To remove. Thus, a single-crystal Si thin film 64 having a thickness of about 80 nm is obtained on the insulating substrate 1 (FIG. 3C).
[0180]
Next, almost all of the surface of the insulating substrate 1 is covered with SiH ₄ And N ₂ Using a mixed gas of O and a P-CVD method, a SiO ₂ A film 35 is deposited, and over substantially the entire surface thereof, SiH ₄ Is used to form an amorphous Si film 66 having a thickness of about 50 nm by the P-CVD method (FIG. 3D).
[0181]
The amorphous Si film 66 is irradiated with an excimer laser and heated to crystallize the amorphous Si and grow a polycrystalline Si layer, thereby forming a polycrystalline Si thin film 67. By this heating, the bonding strength of the single crystal Si thin film 64 can be improved.
[0182]
Next, an island-shaped pattern is formed by removing at least a portion of the polycrystalline Si thin film 67 that becomes an active region of the device and an unnecessary portion including an unnecessary portion on the single crystal Si thin film 64 by etching. It is formed (FIG. 3E).
[0183]
Then, TEOS and O ₂ Of about 350 nm in film thickness by a P-CVD method using a mixed gas of ₂ After depositing a film and further applying a photoresist of about 350 nm as a resin flattening film over the entire surface, ₂ And CF ₄ RIE using a mixed gas containing ₂ A part of the film 35 is etched back.
[0184]
Then, SiH ₄ And N ₂ A gate oxide film 68 having a thickness of about 60 nm is formed by a P-CVD method using a mixed gas with O (FIG. 3F).
[0185]
Thereafter, similarly to the first and second embodiments, it may be formed by the same process as that for forming a well-known p-Si (polycrystalline silicon) TFT matrix substrate. That is, a gate electrode made of polycrystalline Si, silicide, polycide, or the like is formed. And P ⁺ And B ⁺ Is ion-implanted to form an interlayer insulating film (SiO 2). ₂ After a film is deposited and a contact hole is opened, a metal wiring is formed in the contact hole.
[0186]
Here, a conventional N-channel TFT formed in a polycrystalline silicon region has a mobility of about 100 cm. ² / V · sec, whereas in the active matrix substrate according to the present embodiment, the N-channel TFT formed in the single crystal Si region is about 550 cm. ² / V · sec.
[0187]
In this active matrix substrate, the device formed in the region of the polycrystalline Si thin film 67 as well as the driver requires a signal of 7 to 8 V and a power supply voltage, whereas the device formed in the region of the single crystal Si thin film 64. The devices such as the timing controller and the microprocessor operated stably at 3.3V.
[0188]
[Embodiment 4]
The following will describe another embodiment of the present invention with reference to FIG. Note that, in the present embodiment, components having the same functions as the components in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
[0189]
The active matrix substrate according to the present embodiment is obtained by forming a polycrystalline Si thin film 43 instead of the polycrystalline Si thin film 4 in the active matrix substrate 20 according to the above-described first embodiment. This is the same as the substrate 20. Hereinafter, only differences from the active matrix substrate 20 will be described.
[0190]
The polycrystalline Si thin film 43 is composed of polycrystalline Si whose crystal growth is promoted by metal assist, so-called continuous grain boundary silicon (Continuous Grain Silicon).
[0191]
Hereinafter, a method of manufacturing an active matrix substrate using the polycrystalline Si thin film 43 will be described with reference to FIGS. 4 (a) to 4 (e).
[0192]
First, TEOS (Tetra Ethoxy Silane, that is, Si (OC) is formed on the entire surface of the insulating substrate 1 made of the code 1737 (manufactured by Corning). ₂ H ₅ ) ₄ And O ₂ (Oxygen) and a P-CVD method to form a SiO 2 film having a thickness of about 100 nm. ₂ The film 2 is deposited.
[0193]
Subsequently, the SiO ₂ SiH on the film 2 ₄ An amorphous Si film 3 having a thickness of about 50 nm is deposited by a P-CVD method using a gas. After that, SiH is formed on substantially the entire surface of the insulating substrate 1. ₄ And N ₂ Approximately 200 nm of SiO by P-CVD using O mixed gas ₂ Film 41 (second SiO ₂ Film). (FIG. 4 (a)).
[0194]
And the upper layer SiO ₂ After an opening is formed in a predetermined region of the film 41 by etching, the surface of the amorphous Si film 3 is thinly oxidized in order to control the hydrophilicity of the surface of the amorphous Si film 3 in the opening. Then, an oxide film 42 is formed thereon, and an aqueous solution of Ni acetate is spin-coated thereon (FIG. 4B).
[0195]
Next, solid-phase growth is performed at a temperature of 600 ° C. for about 12 hours to grow polycrystalline Si in which crystal growth is promoted by metal assist, that is, so-called continuous grain boundary silicon (Continuous Grain Silicon). Forms a polycrystalline Si thin film 43 of about 50 nm. Further, SiO on the polycrystalline Si thin film 43 ₂ The film 41 and the oxide film 42 are removed. Thereafter, a predetermined region of the polycrystalline Si thin film 43 is removed by etching (FIG. 4C).
[0196]
On the other hand, a single crystal Si substrate 10 is prepared. The single crystal Si substrate 10 has its surface oxidized in advance or an oxide film (SiO 2 ₂ Film) to form a SiO 2 film having a thickness of about 200 nm. ₂ A film 11 is formed. In addition, the single-crystal Si substrate 10 ¹⁶ / Cm ² Above, here 5 × 10 ¹⁶ / Cm ² Of hydrogen ions at a predetermined energy (here, about 24 keV). ^Fifteen cm ^-3 Doped.
[0197]
Then, the polycrystalline Si thin film 43 is cut into a shape at least 0.3 μm, preferably 0.5 μm or more smaller than the shape of the predetermined region, which is removed by etching, by dicing or anisotropic etching using KOH or the like. The substrate 10 is cut. This prevents metal atoms such as Ni, Pt, Sn, and Pd used in the subsequent manufacturing process of the polycrystalline Si thin film 43 from diffusing into the single-crystal Si region, and stabilizes characteristics. Can be.
[0198]
Subsequently, both the substrate on which the polycrystalline Si thin film 43 is formed and the single-crystal Si substrate 10 are washed and activated with SC-1 for particle removal and surface activation, and then the cut single-crystal Si substrate is cut. The surface of the substrate 10 on the side close to the hydrogen ion implanted portion 12 is brought into close contact with the region removed by etching (refer to FIG. 4C) at room temperature (FIG. 4D).
[0199]
Thereafter, by using laser irradiation or lamp annealing including a peak temperature of about 700 ° C. or more, the temperature of the hydrogen ion implanted portion 12 of the single crystal Si substrate 10 is increased to a temperature at which hydrogen is released from Si or more. As a result, the single-crystal Si substrate 10 is cleaved off from the insulating substrate 1 at the hydrogen ion implanted portion 12.
[0200]
Subsequently, the damaged layer on the surface of the single-crystal Si substrate that has been peeled off and remains on the insulating substrate 1 is lightly etched by about 10 nm by isotropic plasma etching or wet etching, here, isotropic plasma etching using buffered hydrofluoric acid. To remove. Thus, a single-crystal Si thin film 5 having a thickness of about 50 nm is obtained on the insulating substrate 1 (FIG. 4E).
[0201]
Next, the SiO 2 near the active region of the device ₂ An opening is formed in the film and SiO ₂ A high concentration of P is used for gettering Ni added to promote crystal growth using the film as a mask. ⁺ Implant ions (15 keV, 5 × 10 ^Fifteen / Cm ² ), Heat treatment at RTA at a temperature of about 800 ° C. for 1 minute. Although a physical space is provided between the single-crystal Si thin film 5 and the polycrystalline Si thin film 43 so that Ni atoms do not diffuse into the single-crystal Si thin film 5, a very small amount of Ni atoms is removed from the process. The gettering is desirably performed also on the active region of single crystal Si, which may be mixed in the inside. If space is prioritized, gettering may be omitted as a design option.
[0202]
Next, an unnecessary portion of the polycrystalline Si thin film 43 and an unnecessary portion of the single crystal Si thin film 5 are removed by etching, leaving a portion to be an active region of the device, thereby obtaining an island-like pattern (FIG. 1E). Correspondence).
[0203]
Subsequent steps (corresponding to FIGS. 1 (f) to 1 (h)) are the same as in the first embodiment, and will not be described.
[0204]
Here, a conventional N-channel TFT formed in a continuous grain boundary Si region has a mobility of about 200 cm. ² / V · sec, whereas in the active matrix substrate according to the present embodiment, the N-channel TFT formed in the single crystal Si region is about 550 cm. ² / V · sec.
[0205]
In this active matrix substrate, the device formed in the region of the polycrystalline Si thin film 43 as well as the driver requires a signal and a power supply voltage of 7 to 8 V, while the device formed in the region of the single crystal Si thin film 5 The timing controller, microprocessor, etc. operated stably at 3.3V.
[0206]
In the step shown in FIG. 4B, spin coating is performed using an aqueous solution of Ni acetate. However, the present invention is not limited to this. For example, ethanol may be used.
[0207]
[Embodiment 5]
The following will describe another embodiment of the present invention with reference to FIG. Note that, in the present embodiment, components having the same functions as the components in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
[0208]
The active matrix substrate 50 according to the present embodiment is the same as the active matrix substrate 20 according to the first embodiment described above. ₂ An insulating film 52 and an amorphous Si film 53 are formed instead of the film 2 and the amorphous Si film 3, and the other structure is the same as that of the active matrix substrate 20. Hereinafter, only differences from the active matrix substrate 20 will be described.
[0209]
As shown in FIG. 5H, the active matrix substrate 50 has a concave portion 51 with a depth of about 150 nm on the insulating substrate 1 and has a SiO ₂ An insulating film 52 made of a film, a Si nitride film, or the like is formed.
[0210]
SiO ₂ On the film 2, a polycrystalline Si thin film 54 and SiO ₂ A film 11 is formed. Like the polycrystalline Si thin film 4, the polycrystalline Si thin film 54 is formed so as to have an island pattern, and has a thickness of about 50 nm. SiO ₂ The film 11 is made of SiO ₂ An island pattern is formed on the film 52 in a region different from the polycrystalline Si thin film 54, and its thickness is about 200 nm. SiO ₂ On the film 11, a single-crystal Si thin film 5 having the same shape is further formed so as to form an island pattern. The thickness of the single-crystal Si thin film 5 is about 50 nm.
[0211]
In the present embodiment, SiO 2 ₂ The thickness of the film 11 is 400 nm.
[0212]
Hereinafter, a method for manufacturing the active matrix substrate 50 will be described with reference to FIGS.
[0213]
First, SiH is coated on the entire surface of the insulating substrate 1 made of the code 1737 (manufactured by Corning). ₄ And N ₂ An insulating film 52 having a thickness of about 350 nm is deposited by a P-CVD method using a mixed gas with O. Subsequently, the entire surface is covered with SiH ₄ An amorphous Si film 53 having a thickness of about 50 nm is deposited by a P-CVD method using a gas (FIG. 5A).
[0214]
Then, the amorphous Si film 53 is irradiated with an excimer laser to be heated and crystallized to grow a polycrystalline Si layer, thereby forming a polycrystalline Si thin film 54.
[0215]
The concave portion 51 having a depth of about 200 nm is formed by removing the polycrystalline Si thin film 54 and a part of the insulating film 52 in a predetermined region by etching about 150 nm (FIG. 5B).
[0216]
On the other hand, a single crystal Si substrate 10 is prepared. The single crystal Si substrate 10 has its surface oxidized in advance or an oxide film (SiO 2 ₂ Film) to form a SiO 2 film having a thickness of about 400 nm. ₂ A film 11 is formed. In addition, the single-crystal Si substrate 10 ¹⁶ / Cm ² Above, here 5 × 10 ¹⁶ / Cm ² Of hydrogen ions at a predetermined energy (here, about 24 keV).
[0217]
Then, the single crystal Si substrate 10 is cut by dicing, anisotropic etching or the like into a shape smaller than the shape of the predetermined region where the polycrystalline Si thin film 54 is removed by etching by 0.5 μm or more.
[0218]
Subsequently, both the substrate on which the polycrystalline Si thin film 54 is formed and the single-crystal Si substrate 10 are cleaned and activated with SC-1 for particle removal and surface activation, and then the cut single-crystal Si substrate is cut. The surface of the substrate 10 on the side close to the hydrogen ion implanted portion 12 is brought into close contact with the concave portion 51 at room temperature and joined (FIG. 5C).
[0219]
Thereafter, heat treatment is performed at a temperature of 300 ° C. to 600 ° C., about 550 ° C. in this case, and the temperature of the hydrogen ion implanted portion 12 of the single crystal Si substrate 10 is raised to a temperature at which hydrogen is released from Si or higher. As a result, the single crystal Si substrate 10 is cleaved off at the hydrogen ion implanted portion 12.
[0220]
Then, the damaged layer on the surface of the single crystal Si substrate that has been peeled off and remains on the insulating substrate 1 is lightly etched by about 10 nm by isotropic plasma etching or wet etching, here, isotropic plasma etching using buffered hydrofluoric acid. To remove. Thus, a polycrystalline Si thin film 54 and a single-crystal Si thin film 5 each having a thickness of about 50 nm are obtained on the insulating substrate 1. (FIG. 5 (d)).
[0221]
Thereafter, lamp annealing is performed at about 800 ° C. for 1 minute.
[0222]
Next, an island-like pattern is obtained by removing unnecessary portions of the Si thin film 54.5 by etching while leaving a portion to be an active region of the device (FIG. 5E).
[0223]
Then, TEOS and O ₂ Using a mixed gas of (oxygen) and a P-CVD method, a SiO ₂ A film is deposited, and this is etched back by about 400 nm by RIE (reactive ion etching) which is anisotropic etching. Then, SiH ₄ And N ₂ A 60-nm-thick gate oxide film 6 (SiO 2) is formed by a P-CVD method using a mixed gas with O. ₂ (FIG. 5F).
[0224]
Subsequent steps (FIGS. 5 (g) and 5 (h) (corresponding to FIGS. 1 (g) and (h)) are the same as in the first embodiment, and will not be described.
[0225]
A conventional N-channel TFT formed in a polycrystalline silicon region has a mobility of about 100 cm. ² / V · sec, on the other hand, in the liquid crystal display active matrix substrate 60, the N-channel TFT formed in the single crystal Si region is about 550 cm. ² / V · sec.
[0226]
In this active matrix substrate 50, the device formed in the region of the polycrystalline Si thin film 54 as well as the driver requires a signal of 7 to 8 V and a power supply voltage, whereas the device formed in the region of the single crystal Si thin film 5 The devices such as the timing controller and the microprocessor operated stably at 3.3V.
[0227]
In the active matrix substrate 50, about 400 nm of SiO ₂ The single-crystal Si substrate 10 on which the film 11 was formed was used. ₂ Compared to 0.3 V (± σ) in the first embodiment using the single-crystal Si substrate 10 on which the film 11 is formed, the voltage is about 1/2, that is, 0.15 V (± σ). Operational stability has been improved.
[0228]
This is because the influence of fixed charges caused by contamination of the interface between the bonded single crystal Si substrate and the insulating substrate or distortion or imperfection of the lattice is reduced. About 400 nm of SiO ₂ As the thickness of the film 11 increases, the variation in the threshold value decreases. ₂ An appropriate value is approximately 200 nm to 400 nm due to the trade-off between the efficiency (time required for oxidation) of the formation process of the film 11 and the step. An appropriate value is approximately 400 nm when emphasizing variation, and approximately 200 nm when emphasizing steps and efficiency.
[0229]
Of course, if the step does not matter, it is needless to say that 400 nm or more is preferable.
[0230]
After forming the concave portion 51, TEOS and O ₂ Tens nm of SiO 2 by PECVD using a gas ₂ After depositing the film so as to cover the entire insulating substrate 1, the single crystal Si substrate 10 and the insulating substrate 1 may be joined. Thereby, the joining property is improved, and the joining can be more reliably performed with a high yield.
[0231]
Here, as the single crystal Si substrate 10 described above, 5 × 10 ¹⁶ / Cm ² A hydrogen ion implanted at a predetermined energy with a predetermined dose was used. ¹⁶ / Cm ² A description will be given of a case where a single crystal Si substrate into which hydrogen ions of a given dose are implanted at a predetermined energy is used.
[0232]
Single crystal Si substrate 10 (dose amount of hydrogen ions: 5 × 10 ¹⁶ / Cm ² In the case of (1), heat treatment was performed at a temperature of about 550 ° C. in order to obtain a single-crystal Si thin film 5, but the single-crystal Si substrate (dose amount of hydrogen ions: 3 × 10 ¹⁶ / Cm ² In the case of (1), heat treatment is performed by irradiating an excimer laser pulse with an energy of about 60 to 80% when forming the polycrystalline Si layer and irradiating the entire surface in the same manner as when growing the polycrystalline Si layer.
[0233]
In this case, the mobility of the conventional N-channel TFT formed in the polysilicon region is about 100 cm. ² / V · sec, whereas the N-channel TFT formed in the single crystal Si region is about 600 cm ² / V · sec.
[0234]
In the active matrix substrate 50 using the single crystal Si substrate 10 (see FIG. 5 (h)), the TFT formed in the conventional single crystal silicon region has a mobility of about 550 cm. ² / V · sec.
[0235]
This difference is due to the fact that the single crystal Si substrate (dose amount of hydrogen ions: 3 × 10 ¹⁶ / Cm ² This is because the amount of hydrogen ion implantation of the single crystal Si thin film obtained by using the method (1) is reduced, so that damage to single crystal Si due to hydrogen ion implantation can be reduced and TFT characteristics are improved.
[0236]
In addition, a single-crystal Si substrate (dose amount of hydrogen ions: 3 × 10 ¹⁶ / Cm ² )), The device formed in the region of the polycrystalline Si thin film requires a signal and a power supply voltage of 7 to 8 V, while the device formed in the region of the single crystal Si thin film, in addition to the driver. The timing controller, microprocessor and the like operated stably at 3.3V.
[0237]
It should be noted that the present invention is not limited to the embodiments described above, and various changes can be made within the scope shown in the claims, and the technical means disclosed in the different embodiments are appropriately combined. Embodiments obtained are also included in the technical scope of the present invention.
[0238]
The embodiments of the present invention are not limited to the present contents. For example, a polycrystalline Si formation method, or a material and a film thickness of an interlayer insulating film may be obtained by means that other engineers in the same field can know. Needless to say, this can also be realized. Also, it goes without saying that similar effects can be obtained with different materials as long as they are generally used for the same purpose.
[0239]
Further, in the first, second, fourth and fifth embodiments, the SiO 2 on the surface joined to the single-crystal Si thin film formed on insulating substrate 1 ₂ The film may be deposited after forming a concave portion by etching a part of the polycrystalline Si thin film or the insulating substrate 1.
[0240]
【The invention's effect】
A semiconductor device according to the present invention is a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed in different regions on an insulating substrate, wherein a standardized line between the insulating substrate and the single-crystal Si thin film is formed. The difference in expansion is approximately 250 ppm or less in a temperature range of approximately room temperature to 600 ° C.
[0241]
Thus, devices requiring higher performance, such as a timing controller and a microprocessor, can be formed in the single crystal Si thin film formation region, and the remaining devices can be formed in the polycrystalline Si thin film formation region. .
[0242]
In addition, the shape of the single crystal Si substrate is limited to a disk of 6, 8, or 12 inches, which is the wafer size of an LSI manufacturing apparatus. However, since a polycrystalline Si thin film is also formed on the substrate, It is also possible to manufacture liquid crystal display panels and organic EL panels.
[0243]
Further, it is not necessary to use crystallized glass whose composition has been adjusted in order to prevent destruction in the step of improving the heat bonding strength due to the difference in thermal expansion coefficient from the quartz substrate. Thus, the problem of alkali metal contamination caused by crystallized glass is eliminated, and destruction in the step of improving the heat bonding strength due to a difference in thermal expansion coefficient can be prevented.
[0244]
Further, the difference in the linear expansion coefficient between the insulating substrate and the single-crystal Si thin film becomes small. Therefore, in the process for forming a single-crystal Si thin film on an insulating substrate, it is necessary to surely prevent destruction, bonding interface separation, or generation of defects in the crystal in the cleavage separation process from the hydrogen implantation position due to the difference in thermal expansion coefficient. In addition, there is an effect that the heat bonding strength can be improved.
[0245]
The semiconductor device of the present invention is a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed in different regions on an insulating substrate, and the shift amount of the Raman peak in the single-crystal Si thin film is 519. 5cm ^-1 Above and 521.5cm ^-1 The configuration is as follows.
[0246]
Thus, devices requiring higher performance, such as a timing controller and a microprocessor, can be formed in the single crystal Si thin film formation region, and the remaining devices can be formed in the polycrystalline Si thin film formation region. .
[0247]
Further, the stress acting on the Si interface in the single-crystal Si thin film can be made substantially zero. Therefore, when a TFT is formed, a decrease or variation in mobility due to strain of the Si crystal due to unevenness or variation in stress acting on the Si interface, or a defect at the interface, an associated fixed charge, and a localized level at the interface. And the like, the threshold shift, the variation, the deterioration of the characteristic stability, and the like can be reliably prevented.
[0248]
In the semiconductor device of the present invention, the insulating substrate may be formed by forming SiO2 on at least the surface of the region where single-crystal Si exists. ₂ This is a structure composed of a high strain point glass composed of an alkaline earth-aluminoborosilicate glass having a layer formed thereon.
[0249]
This eliminates the need to use crystallized glass of which composition has been adjusted, so that the insulating substrate is made of a high strain point glass generally used for a liquid crystal display panel or the like driven by active matrix, so that the semiconductor device can be manufactured at low cost. Is produced.
[0250]
In the semiconductor device of the present invention, the insulating substrate is made of barium-aluminoborosilicate glass, alkaline earth-aluminoborosilicate glass, borosilicate glass, alkaline earth-zinc-lead-aluminoborosilicate glass, alkaline earth-zinc- It is a configuration made of any one of aluminoborosilicate glass.
[0251]
As a result, the insulating substrate is made of the above-mentioned glass which is a high strain point glass generally used for a liquid crystal display panel or the like driven by active matrix, so that a semiconductor device suitable for the active matrix substrate can be manufactured at low cost. This has the effect.
[0252]
The semiconductor device of the present invention is configured to be an active matrix substrate including an integrated circuit including a plurality of MOSFETs, bipolar transistors, or SITs on an insulating substrate.
[0253]
This produces an effect that an active matrix substrate having the above characteristics can be obtained.
[0254]
The semiconductor device of the present invention has a configuration in which a region of a single-crystal Si thin film and a region of a polycrystalline Si thin film formed on an insulating substrate are separated by 0.3 μm or more, and further, 0.5 μm or more.
[0255]
This prevents the diffusion of, for example, Ni, Pt, Sn, Pd, etc. from the polycrystalline Si into the single-crystal Si, and has the effect of stabilizing the characteristics of the semiconductor device.
[0256]
The semiconductor device of the present invention has a configuration in which at least one of the mobility, the sub-threshold coefficient, and the threshold value is different for each of the regions in transistors of the same conductivity type formed in different regions.
[0257]
Thus, in the one-conductivity-type transistors formed in different regions, at least one of the mobility, the sub-threshold coefficient, and the threshold is different, so that the transistor can be formed in an appropriate region in accordance with required characteristics. It has the effect of being able to.
[0258]
The semiconductor device of the present invention has a configuration in which at least one of a gate length, a thickness of a gate oxide film, a power supply voltage, and a logic level differs in each of the integrated circuits formed in different regions.
[0259]
Thus, at least one of the gate length, the thickness of the gate oxide film, the power supply voltage, and the logic level is different among the integrated circuits formed in different regions, so that the integrated circuit is suitable for the required configuration and characteristics. This has the effect of being able to be formed in a region that is not flat.
[0260]
The semiconductor device of the present invention has a configuration in which the processing rules are different for each of the integrated circuits formed in different regions.
[0261]
Thus, since the integrated circuits formed in different regions have different processing rules, an effect is obtained that the integrated circuit can be formed in an appropriate region in accordance with the processing rules.
[0262]
In the semiconductor device of the present invention, the thickness d of the single-crystal Si thin film is a small value including a variation margin with respect to the maximum depletion length Wm determined by the impurity Ni, that is, the impurity density is the practical lower limit. ^Fifteen cm ^-3 In this case, the upper limit of the film thickness d is about 600 nm or less.
[0263]
As a result, the S value (sub-threshold coefficient) of the semiconductor device is reduced and the off-state current is reduced.
[0264]
The semiconductor device of the present invention has a configuration in which the thickness of the single-crystal Si thin film is 100 nm or less.
[0265]
Thus, the S value of the semiconductor device is further reduced, and the off-current is further reduced.
[0266]
The method for manufacturing a semiconductor device according to the present invention comprises the steps of: ₂ A step of sequentially depositing a film and an amorphous Si film; a step of heating the amorphous Si film to grow a polycrystalline Si layer to form a polycrystalline Si thin film; Etching and removing the surface, and oxidizing the surface or depositing an oxide film in advance ₂ A single crystal Si substrate having a hydrogen ion implanted portion formed with a film and implanted with a predetermined concentration of hydrogen ions at a predetermined depth has a predetermined shape covering a part or substantially the entire region of the region removed by etching. A step of cutting, a step of cleaning the insulating substrate and the single-crystal Si substrate to activate the surfaces of the two substrates, and a step of etching the cut single-crystal Si substrate into a region where the surface on the side to which hydrogen ions have been implanted is removed by etching. The structure includes a step of bonding both substrates by bringing them into close contact at room temperature, and a step of forming a single-crystal Si thin film on an insulating substrate by performing heat treatment to cleave and separate at a hydrogen ion implanted portion.
[0267]
Thereby, the bonding strength can be increased, and a single-crystal Si thin film can be obtained by separating the single-crystal Si substrate at the hydrogen ion implanted portion. Therefore, localized levels in the gap, defects near the crystal grain boundaries, and localization in the gap due to crystal imperfections peculiar to polycrystalline Si, which are obstacles to forming a high-performance device Problems such as a decrease in mobility and an increase in S coefficient due to the presence of a level can be solved by single crystal Si. Therefore, a single-crystal Si thin film and a polycrystalline Si thin film can be formed on an insulating substrate, and the subsequent steps are formed by a common processing process. The device can be formed of polycrystalline Si. Accordingly, a semiconductor device such as a display device such as a liquid crystal panel or an organic EL panel in which a high-performance system is integrated can be manufactured at low cost.
[0268]
In addition, SiO ₂ Since a single-crystal Si substrate is bonded to an insulating substrate such as a glass substrate through the formation of a film in advance, a decrease in mobility due to strain of the Si crystal due to stress applied to the bonded Si interface, or defects at the interface, This can prevent the fixed charges at the interface, the threshold shift due to the localized level of the interface, the deterioration of the characteristic stability, and the like. This eliminates the need to use crystallized glass whose composition has been adjusted in order to improve the heat bonding strength due to the difference in thermal expansion coefficient from the quartz substrate and prevent destruction in the peeling step, and it is possible to use glass with a high strain point. Therefore, the problem of contamination by alkali metal due to crystallized glass is eliminated, and it is possible to improve the heat bonding strength due to a difference in thermal expansion coefficient and prevent breakage in the peeling step.
[0269]
Further, for example, a polycrystalline Si film is formed on a large-area high-strain-point glass substrate, and the polycrystalline Si thin film is etched and removed in advance so as to cover a region where a single-crystal Si substrate processed to an appropriate size is to be bonded. Then, a single crystal Si substrate is bonded to this region, and the single crystal Si thin film and SiO ₂ By leaving the film and exfoliating and removing the other single crystal Si, it is possible to eliminate the bias of the stress over the entire glass substrate. As a result, it is possible to obtain a substrate in which a partial region of the substrate is formed of a single-crystal Si thin film and the remaining region is formed of a polycrystalline Si thin film without peeling, cracking, or destruction of Si.
[0270]
Further, the shape of the single-crystal Si substrate is limited to a disk of 6, 8, or 12 inches, which is the wafer size of the LSI manufacturing apparatus. However, since a polycrystalline Si thin film is also formed on the insulating substrate, for example, Semiconductor devices such as large liquid crystal display panels and organic EL panels can be manufactured.
[0271]
The single-crystal Si substrate is made of SiO ₂ Since the substrate is bonded to the insulating substrate 1 at room temperature through the film, the stress acting on the bonded Si interface can be made substantially zero. Therefore, the mobility is reduced or varied due to the strain of the Si crystal due to the unevenness or variation of the stress applied to the interface, or the threshold shift or the variation due to the interface defect, the interface fixed charge, the localized level of the interface, and the characteristic. This has the effect that the stability can be prevented more reliably.
[0272]
The method for manufacturing a semiconductor device according to the present invention comprises the steps of: ₂ A step of sequentially depositing a film and an amorphous Si film; a step of heating the amorphous Si film to grow a polycrystalline Si layer to form a polycrystalline Si thin film; and a step of forming the polycrystalline Si thin film in a predetermined region. Is removed by etching and the SiO 2 in the same region is removed. ₂ A step of etching and removing a part of the film in the thickness direction; ₂ A single-crystal Si substrate having a hydrogen ion implanted portion formed with a film and implanted with a predetermined concentration of hydrogen ions at a predetermined depth is cut into a predetermined shape covering a part or substantially the entire region of the etched region. A step of cleaning the insulating substrate and the single-crystal Si substrate and activating the surfaces of the two substrates; and placing the cut single-crystal Si substrate in a region where the hydrogen ion-implanted surface has been etched away. The structure includes a step of bonding both substrates by bringing them into close contact at room temperature, and a step of forming a single-crystal Si thin film on an insulating substrate by performing heat treatment to cleave and separate at a hydrogen ion implanted portion.
[0273]
Thus, in addition to the advantages of the above-described manufacturing method, the polycrystalline Si layer in a predetermined region is further etched away, and the SiO 2 in the same region is removed. ₂ Since a part of the film in the thickness direction is removed by etching, the SiO 2 on the attachment surface side of the single crystal Si substrate is removed. ₂ The influence of the thickness of the film is cancelled, and a substrate can be obtained in which the regions of the single-crystal Si thin film and the polycrystalline Si thin film on the insulating substrate have substantially the same height. As a result, most of the subsequent steps including the island etching can be simultaneously performed. Thus, a transistor or a circuit having a small step is formed. Therefore, for example, in the case of a liquid crystal panel, there is an effect that the cell thickness control is superior.
[0274]
The method for manufacturing a semiconductor device according to the present invention comprises the steps of: ₂ A step of depositing a film and oxidizing the surface in advance or depositing an oxide film on the ₂ Forming a film and cutting a single-crystal Si substrate having a hydrogen ion implanted portion into which a predetermined concentration of hydrogen ions are implanted at a predetermined depth into a predetermined shape; Cleaning and activating the surfaces of the two substrates; and cutting the cut single-crystal Si substrate with the surface on the side on which hydrogen ions have been implanted as an insulating substrate. ₂ A step of bonding at a room temperature to a predetermined position on the film side surface and bonding; a step of heat treatment to cleave and separate at a hydrogen ion implanted portion to form a single crystal Si thin film on an insulating substrate; An insulating film (SiO ₂ And a step of sequentially depositing a film and an amorphous Si film, and a step of heating the amorphous Si film to grow a polycrystalline Si layer to form a polycrystalline Si thin film.
[0275]
According to the above method, there is an effect that the same advantages as those of each of the above manufacturing methods can be obtained.
[0276]
The method for manufacturing a semiconductor device according to the present invention comprises the steps of: ₂ A step of depositing a film, and a step of depositing SiO in a predetermined region. ₂ A step of etching and removing a part of the film in the thickness direction; ₂ A single-crystal Si substrate having a hydrogen ion implanted portion formed with a film and implanted with a predetermined concentration of hydrogen ions at a predetermined depth is cut into a predetermined shape covering a part or substantially the entire region of the etched region. A step of cleaning the insulating substrate and the single-crystal Si substrate to activate the surfaces of the two substrates; and a step of adding a hydrogen ion-implanted surface of the cut single-crystal Si substrate to a region, which has been etched and removed, at room temperature. A step of forming a single-crystal Si thin film by cleaving off at a hydrogen ion implanted portion by heat treatment, and a step of forming an insulating film (SiO ₂ And a step of sequentially depositing a film and an amorphous Si film, and a step of heating the amorphous Si film to grow a polycrystalline Si layer to form a polycrystalline Si thin film.
[0277]
Thereby, there is an effect that the same advantages as those of the respective manufacturing methods can be obtained.
[0278]
According to the method of manufacturing a semiconductor device of the present invention, the first SiO ₂ Film, amorphous Si film, and second SiO ₂ A step of sequentially depositing a film; ₂ A step of exposing a part of the amorphous Si film by etching and removing a predetermined region of the film; and forming an oxide film by oxidizing the exposed amorphous Si film, and forming Ni acetate on the oxide film. A step of spin-coating an aqueous solution, a step of heating the amorphous Si film, growing a polycrystalline Si layer whose crystal growth is promoted by metal assist, and forming a polycrystalline Si thin film, ₂ Removing the film and the oxide film, etching and removing a predetermined region of the polycrystalline Si layer, and oxidizing or depositing an oxide film on the surface in advance to form a SiO 2 film on the surface. ₂ A single-crystal Si substrate having a hydrogen ion implanted portion formed with a film and implanted with a predetermined concentration of hydrogen ions at a predetermined depth is cut into a predetermined shape covering a part or substantially the entire region of the etched region. A step of cleaning the insulating substrate and the single-crystal Si substrate and activating the surfaces of the two substrates; and placing the cut single-crystal Si substrate in a region where the hydrogen ion-implanted surface has been etched away. The structure includes a step of bonding both substrates by bringing them into close contact at room temperature, and a step of forming a single-crystal Si thin film on an insulating substrate by performing heat treatment to cleave and separate at a hydrogen ion implanted portion.
[0279]
Thereby, there is an effect that the same advantages as those of the respective manufacturing methods can be obtained.
[0280]
The method for manufacturing a semiconductor device according to the present invention is configured such that heat treatment is performed in one or multiple temperature steps of 300 ° C. or more and 650 ° C. or less.
[0281]
Thereby, there is an effect that the heat treatment can be performed in one temperature step, that is, in one process.
[0282]
The method of manufacturing a semiconductor device according to the present invention has a configuration in which at least one of Ni, Pt, Sn, and Pd is added to an amorphous Si film when growing a polycrystalline Si layer.
[0283]
Thereby, at the time of growing the polycrystalline Si layer, at least one of Ni, Pt, Sn, and Pd is added to the amorphous Si film, and thereafter, the crystal growth of the polycrystalline Si layer is promoted by heating. can do. Therefore, the mobility of the polycrystalline Si layer can be increased, which is advantageous in forming a driving circuit.
[0284]
In the method for manufacturing a semiconductor device according to the present invention, the temperature of the hydrogen ion implanted portion of the single crystal Si substrate is increased by laser irradiation to a temperature equal to or higher than the temperature at which hydrogen is released from Si. This is a configuration for performing a step of cleaving off at the boundary.
[0285]
Thereby, the temperature of the hydrogen ion implanted portion of the single crystal Si substrate is increased by the laser irradiation, so that the temperature can be increased only in a narrow area, and the effect of suppressing damage to the single crystal Si can be reduced. Play.
[0286]
The semiconductor device of the present invention has a configuration in which a single crystal Si substrate is separated from a hydrogen ion implanted portion by performing lamp annealing including a peak temperature of approximately 700 ° C. or higher.
[0287]
As a result, the junction strength is further improved, and the characteristics of the transistor can be improved by recovering the damage due to the hydrogen ion implantation in the peeling interface and the inside of the single-crystal Si thin film.
[0288]
According to the method of manufacturing a semiconductor device of the present invention, after a polycrystalline Si thin film and a single crystal Si thin film are formed on an insulating substrate, a damaged layer on the surface of the single crystal Si thin film is removed by isotropic plasma etching or wet etching. The polycrystalline Si thin film and the single-crystal Si thin film are patterned into islands by etching; ₂ After depositing the film, anisotropic etching is performed to etch back SiO ₂ Etching back all or part of the film while leaving a part of the film; ₂ Forming a gate insulating film by depositing a film.
[0289]
As a result, since a general polysilicon TFT forming step is performed, there is an effect that a TFT having the above characteristics can be manufactured using a conventional step.
[0290]
In the method for manufacturing a semiconductor device according to the present invention, the polycrystalline Si thin film and the single-crystal Si thin film are formed on an insulating substrate, and then a damaged layer on the surface of the single-crystal Si thin film isotropically etched or wet-etched. Etching the polycrystalline Si thin film and the single crystal Si thin film into an island pattern by etching; and etching the entire surface of the polycrystalline Si thin film and the single crystal Si thin film with SiO for etching back. ₂ After depositing the film, a step of further applying a resin flattening film on the entire surface, and anisotropic etching to completely cover the resin flattening film and the SiO for etching back ₂ Etching back a part of the film; ₂ Forming a gate insulating film by depositing a film.
[0291]
Thereby, an oxide film (SiO 2) is formed in a valley between the patterns of the polycrystalline Si thin film and the single crystal Si thin film. ₂ As a result, the film remains), and an effect is obtained that the entire substrate can be flattened.
[0292]
In the method of manufacturing a semiconductor device according to the present invention, the single crystal Si thin film and the polycrystalline Si thin film formed on an insulating substrate are patterned into an island shape by etching to form a MOS transistor. At least some of the source and drain regions of the transistor ^Fifteen / Cm ² 5 × 10 or more ^Fifteen / Cm ² The following P ⁺ And a step of implanting ions.
[0293]
This gives P ⁺ After ion implantation, heat treatment is performed by RTA, laser, furnace, etc., and metal atoms are simultaneously gettered not only in the polycrystalline Si thin film region but also in the single crystal Si thin film region, so that the characteristic variation is further reduced and the characteristics are stabilized. There is an effect that a TFT can be obtained.
[0294]
The method of manufacturing a semiconductor device according to the present invention has a configuration in which the thickness of the single-crystal Si thin film is substantially equal to the thickness of the polycrystalline Si thin film.
[0295]
Thus, most of the subsequent steps including the etching for forming the island pattern can be simultaneously performed, and a transistor or a circuit having a small step can be formed. Therefore, for example, in the case of a liquid crystal panel, there is an effect that the cell thickness control is superior.
[0296]
The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device, comprising: ₂ The film has a thickness of 200 nm or more, and more preferably 300 nm or more.
[0297]
As a result, variation in the threshold value and SiO 2 ₂ There is an effect that a semiconductor substrate suitable for balance with the efficiency of the film forming process and the step can be obtained.
[0298]
The method for manufacturing a semiconductor device according to the present invention is configured such that the maximum dimension of the single-crystal Si thin film is 10 cm or less.
[0299]
Accordingly, if the maximum dimension of the single crystal Si thin film is 10 cm or less, a high strain generally used for a liquid crystal display panel or the like generally driven by an active matrix, which has a larger difference in thermal expansion coefficient from single crystal Si than a quartz substrate. Even when the point glass is used, there is an effect that breakage such as cracks and peeling of Si can be prevented.
[0300]
The method of manufacturing a semiconductor device according to the present invention is configured such that the maximum dimension of the single crystal Si thin film is 5 cm or less.
[0301]
As a result, even if a high strain point glass having a larger difference in thermal expansion coefficient from single crystal Si than a quartz substrate and generally used for a liquid crystal display panel or the like generally driven by an active matrix is used, it is possible to further destroy cracks and the like and prevent Si This has the effect of preventing peeling off.
[0302]
The method for manufacturing a semiconductor device according to the present invention is configured such that a difference in standardized linear expansion between the single crystal Si thin film and the insulating substrate is approximately 250 ppm or less in a temperature range of approximately room temperature to 600 ° C.
[0303]
Thereby, in the process for forming the single-crystal Si thin film on the insulating substrate, it is possible to reliably prevent the destruction, the bonding interface separation, and the generation of defects in the crystal in the cleavage separation process from the hydrogen implantation position due to the difference in thermal expansion coefficient. In addition, there is an effect that the heat bonding strength can be improved.
[0304]
In the method of manufacturing a semiconductor device according to the present invention, the dose of hydrogen ions ¹⁶ / Cm ² Above, furthermore, approximately 3 × 10 ¹⁶ / Cm ² The configuration is as follows.
[0305]
Thereby, there is an effect that characteristics such as mobility of the TFT formed in the region of the single crystal Si thin film can be improved.
[Brief description of the drawings]
FIGS. 1A to 1H are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
FIGS. 2A to 2H are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to another embodiment of the present invention.
FIGS. 3A to 3F are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to still another embodiment of the present invention.
4A to 4E are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to still another embodiment of the present invention.
5A to 5H are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device according to still another embodiment of the present invention.
FIG. 6 is a graph showing linear expansion of Si as a material of a single crystal Si substrate, code 1737 as a material of an insulating substrate, and code 7059 made of barium-borosilicate glass.
[Explanation of symbols]
1 insulating substrate
2, 32, 52, 62 SiO ₂ Film (insulating film, first SiO ₂ film)
3,36,53 Amorphous Si thin film
4, 37, 43, 54 Polycrystalline Si thin film
5,34 Single-crystal Si thin film
6, 38 Gate insulating film (Si oxide film)
10 Single crystal Si substrate
11 SiO ₂ film
12 Hydrogen ion implanter
20, 30, 50 semiconductor device
33, 55 recess
35 SiO ₂ Film (insulating film)
41 SiO ₂ Film (second SiO) ₂ film)

Claims (32)

A semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed in different regions on an insulating substrate,
A semiconductor device, wherein a difference in normalized linear expansion between the insulating substrate and the single-crystal Si thin film is approximately 250 ppm or less in a temperature range of approximately room temperature to 600 ° C. A semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed in different regions on an insulating substrate,
A semiconductor device, wherein a shift amount of a Raman peak in the single-crystal Si thin film is 519.5 cm ⁻¹ or more and 521.5 cm ⁻¹ or less. 3. The insulating substrate according to claim 1, wherein the insulating substrate is made of a high strain point glass made of an alkaline earth-aluminoborosilicate glass having a SiO ₂ layer formed on at least a surface of a region where single crystal Si exists. 4. 13. The semiconductor device according to claim 1. The insulating substrate may be made of barium-aluminoborosilicate glass, alkaline earth-aluminoborosilicate glass, borosilicate glass, alkaline earth-zinc-lead-aluminoborosilicate glass, or alkaline earth-zinc-aluminoborosilicate glass. The semiconductor device according to claim 1, wherein the semiconductor device comprises any one of the semiconductor devices. 3. The semiconductor device according to claim 1, wherein the semiconductor device is an active matrix substrate including an integrated circuit including a plurality of MOSFETs, bipolar transistors, or SITs on the insulating substrate. 3. The semiconductor device according to claim 1, wherein a region of the single-crystal Si thin film formed on the insulating substrate and a region of the polycrystalline Si thin film are separated by 0.3 μm or more. 4. 3. The semiconductor device according to claim 1, wherein a region of the single-crystal Si thin film formed on the insulating substrate and a region of the polycrystalline Si thin film are separated by 0.5 μm or more. 3. The semiconductor device according to claim 1, wherein at least one of mobility, a sub-threshold coefficient, and a threshold value of each of the transistors of the same conductivity type formed in each of the different regions is different for each of the regions. 3. The integrated circuit formed in each of the different regions, wherein at least one of a gate length, a gate oxide film thickness, a power supply voltage, and a logic level is different for each of the regions. Semiconductor device. 3. The semiconductor device according to claim 1, wherein the integrated circuit formed in each of the different regions has a different processing rule for each of the regions. 3. The semiconductor device according to claim 1, wherein the single-crystal Si thin film has a thickness of about 600 nm or less. 3. The semiconductor device according to claim 1, wherein the single-crystal Si thin film has a thickness of 100 nm or less. In a method of manufacturing a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed on an insulating substrate,
Sequentially depositing a SiO ₂ film and an amorphous Si film on the surface of the insulating substrate;
Heating the amorphous Si film, growing a polycrystalline Si layer, and forming a polycrystalline Si thin film;
Etching and removing a predetermined region of the polycrystalline Si thin film;
The surface is oxidized or an oxide film is deposited in advance to form a SiO ₂ film on the surface, and a single crystal Si substrate having a hydrogen ion implanted portion implanted with hydrogen ions of a predetermined concentration at a predetermined depth is subjected to the above etching. A step of cutting into a predetermined shape covering a part or substantially the entire area of the removed area,
Washing the insulating substrate and the single-crystal Si substrate and activating the surfaces of both substrates;
A step of bonding the cut single-crystal Si substrate to the region on which hydrogen ions have been implanted at room temperature by bringing the surface on which hydrogen ions are implanted into contact with the etched region,
Forming a single-crystal Si thin film on the insulating substrate by heat treatment to cause cleavage at the hydrogen ion-implanted portion as a boundary. In a method of manufacturing a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed on an insulating substrate,
Sequentially depositing a SiO ₂ film and an amorphous Si film on the surface of the insulating substrate;
Heating the amorphous Si film, growing a polycrystalline Si layer, and forming a polycrystalline Si thin film;
Etching and removing a portion of the polycrystalline Si thin film in a predetermined region in a thickness direction of the SiO ₂ film in the same region;
The surface is oxidized or an oxide film is deposited in advance to form a SiO ₂ film on the surface, and a single crystal Si substrate having a hydrogen ion implanted portion implanted with hydrogen ions of a predetermined concentration at a predetermined depth is subjected to the above etching. A step of cutting into a predetermined shape covering a part or substantially the entire area of the removed area,
Washing the insulating substrate and the single-crystal Si substrate and activating the surfaces of both substrates;
A step of bonding the cut single-crystal Si substrate to the region on which hydrogen ions have been implanted at room temperature by bringing the surface on which hydrogen ions are implanted into contact with the etched region,
Forming a single-crystal Si thin film on the insulating substrate by heat treatment to cause cleavage at the hydrogen ion-implanted portion as a boundary. In a method of manufacturing a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed on an insulating substrate,
Depositing a SiO ₂ film on the surface of the insulating substrate;
A SiO ₂ film is formed on the surface by oxidizing the surface or depositing an oxide film in advance, and a single crystal Si substrate having a hydrogen ion implanted portion implanted with hydrogen ions of a predetermined concentration at a predetermined depth is mounted on a predetermined crystal. Cutting into a shape,
Washing the insulating substrate and the single-crystal Si substrate and activating the surfaces of both substrates;
Bonding the cut single-crystal Si substrate by bonding the surface of the side into which hydrogen ions have been implanted to a predetermined position on the SiO ₂ film-side surface of the insulating substrate at room temperature;
A step of forming a single-crystal Si thin film on the insulating substrate by performing a heat treatment so as to cleave and separate at the hydrogen ion implanted portion;
Sequentially depositing an insulating film and an amorphous Si film on the insulating substrate;
Heating the amorphous Si film, growing a polycrystalline Si layer, and forming a polycrystalline Si thin film. In a method of manufacturing a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed on an insulating substrate,
Depositing a SiO ₂ film on the surface of the insulating substrate;
Etching and removing a part of the predetermined region in the thickness direction of the SiO ₂ film;
The surface is oxidized or an oxide film is deposited in advance to form a SiO ₂ film on the surface, and a single crystal Si substrate having a hydrogen ion implanted portion implanted with hydrogen ions of a predetermined concentration at a predetermined depth is subjected to the above etching. A step of cutting into a predetermined shape covering a part or substantially the entire area of the removed area,
Washing the insulating substrate and the single-crystal Si substrate and activating the surfaces of both substrates;
Bonding the surface of the cut single-crystal Si substrate on the side where hydrogen ions have been implanted to the region where the etching has been removed at room temperature,
A step of forming a single-crystal Si thin film by performing a heat treatment to cleave and separate at the hydrogen ion implanted portion;
Sequentially depositing an insulating film and an amorphous Si film on the insulating substrate;
Heating the amorphous Si film, growing a polycrystalline Si layer, and forming a polycrystalline Si thin film. In a method of manufacturing a semiconductor device in which a polycrystalline Si thin film and a single-crystal Si thin film are formed on an insulating substrate,
The 1SiO ₂ film on the surface of the insulating substrate, an amorphous Si film, and a step of sequentially depositing a first 2SiO ₂ film,
Exposing a portion of the amorphous Si film by etching and removing a predetermined region of the _second SiO ₂ film;
Oxidizing the exposed amorphous Si film to form an oxide film, and spin coating an aqueous solution of Ni acetate on the oxide film;
Heating the amorphous Si film, growing a polycrystalline Si layer whose crystal growth is promoted by metal assist, and forming a polycrystalline Si thin film;
Removing the _second SiO ₂ film and the oxide film;
Etching and removing a predetermined region of the polycrystalline Si layer;
The surface is oxidized or an oxide film is deposited in advance to form a SiO ₂ film on the surface, and a single crystal Si substrate having a hydrogen ion implanted portion implanted with hydrogen ions of a predetermined concentration at a predetermined depth is subjected to the above etching. A step of cutting into a predetermined shape covering a part or substantially the entire area of the removed area,
Washing the insulating substrate and the single-crystal Si substrate and activating the surfaces of both substrates;
A step of bonding the cut single-crystal Si substrate to the region on which hydrogen ions have been implanted at room temperature by bringing the surface on which hydrogen ions are implanted into contact with the etched region,
Forming a single-crystal Si thin film on the insulating substrate by heat treatment to cause cleavage at the hydrogen ion-implanted portion as a boundary. 18. The method of manufacturing a semiconductor device according to claim 13, wherein the heat treatment is performed in one or multiple temperature steps of 300 ° C. or more and 650 ° C. or less. 18. The method according to claim 13, wherein when growing the polycrystalline Si layer, at least one of Ni, Pt, Sn, and Pd is added to the amorphous Si film. Manufacturing method of a semiconductor device. The step of cleaving the single crystal Si substrate at the hydrogen ion implanted portion by raising the temperature of the hydrogen ion implanted portion of the single crystal Si substrate to a temperature at which hydrogen is released from Si by laser irradiation or more. The method of manufacturing a semiconductor device according to claim 13, wherein the method is performed. The semiconductor according to any one of claims 13 to 17, wherein the single crystal Si substrate is separated at a hydrogen ion implanted portion by performing lamp annealing including a peak temperature of approximately 700 ° C or higher. Device manufacturing method After the polycrystalline Si thin film and the single crystal Si thin film are formed on the insulating substrate,
Etching and removing the damaged layer on the surface of the single crystal Si thin film by isotropic plasma etching or wet etching;
A step of patterning the polycrystalline Si thin film and the single crystal Si thin film in an island shape by etching;
After depositing an etch-back SiO ₂ film over the entire surface of the polycrystalline Si thin film and the single-crystal Si thin film, anisotropic etching is performed to etch a portion of the etch-back SiO ₂ film or to etch the entire film thickness. Backing up,
18. The method according to claim 13, further comprising: forming a gate insulating film by depositing an SiO ₂ film. After the polycrystalline Si thin film and the single crystal Si thin film are formed on the insulating substrate,
Etching and removing the damaged layer on the surface of the single crystal Si thin film by isotropic plasma etching or wet etching;
A step of patterning the polycrystalline Si thin film and the single crystal Si thin film in an island shape by etching;
Depositing an etch-back SiO ₂ film over the entire surface of the polycrystalline Si thin film and the single-crystal Si thin film, and further applying a resin planarization film over the entire surface;
Etching back all of the resin flattening film and part of the etch back SiO ₂ film by anisotropic etching;
18. The method according to claim 13, further comprising: forming a gate insulating film by depositing an SiO ₂ film. The single crystal Si thin film and the polycrystalline Si thin film formed on the insulating substrate are patterned into an island shape by etching to form a MOS transistor, and at least one of source and drain regions of an N-type MOS transistor and a P-type MOS transistor is formed. 18. The semiconductor device according to claim 13, further comprising a step of implanting P ⁺ ions of approximately 10 ¹⁵ / cm ² or more and 5 × 10 ¹⁵ / cm ² or less into the portion. Manufacturing method. 18. The method of manufacturing a semiconductor device according to claim 13, wherein the thickness of the single-crystal Si thin film is substantially equal to the thickness of the polycrystalline Si thin film. The method for manufacturing a semiconductor device according to any one of claims 13 to 17, wherein the thickness of the SiO ₂ film formed in advance on the surface of the single crystal Si substrate is 200 nm or more. 18. The method of manufacturing a semiconductor device according to claim 13, wherein the thickness of the SiO ₂ film formed on the surface of the single-crystal Si substrate in advance is 300 nm or more. 18. The method according to claim 13, wherein a maximum size of the single crystal Si thin film is 10 cm or less. 18. The method according to claim 13, wherein a maximum size of the single-crystal Si thin film is 5 cm or less. 18. The single-crystal Si thin film according to claim 13, wherein a difference in normalized linear expansion from the insulating substrate is about 250 ppm or less in a temperature range of about room temperature to 600 ° C. 9. The method for manufacturing a semiconductor device according to claim 1. 18. The method according to claim 13, wherein a dose of hydrogen ions implanted into the hydrogen ion implanted portion is 10 ¹⁶ / cm ² or more. Dose of hydrogen ions to be implanted into the hydrogen ion implantation section is generally a method of manufacturing a semiconductor device according to any one of claims 13 to 17, characterized in that a 3 × 10 16 ^/ cm ^2.

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