WO1996030946A1 - Dispositif semi-conducteur et son procede de fabrication - Google Patents

Dispositif semi-conducteur et son procede de fabrication Download PDF

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Publication number
WO1996030946A1
WO1996030946A1 PCT/JP1995/000592 JP9500592W WO9630946A1 WO 1996030946 A1 WO1996030946 A1 WO 1996030946A1 JP 9500592 W JP9500592 W JP 9500592W WO 9630946 A1 WO9630946 A1 WO 9630946A1
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WO
WIPO (PCT)
Prior art keywords
film
semiconductor
insulator
insulating film
substrate
Prior art date
Application number
PCT/JP1995/000592
Other languages
English (en)
Japanese (ja)
Inventor
Akihiro Miyauchi
Takeo Shiba
Takashi Uchino
Yukihiro Kiyota
Toshio Ando
Osamu Kasahara
Yosuke Inoue
Takaya Suzuki
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1995/000592 priority Critical patent/WO1996030946A1/fr
Publication of WO1996030946A1 publication Critical patent/WO1996030946A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled

Definitions

  • the present invention relates to a structure, a manufacturing method, and a computer system, an optical transmission system, and a signal transmission processing device of an M0SFET in which a silicon film is stacked on source and drain regions, and a silicon film is stacked on the source and drain regions.
  • M0SFETs with small facets of the silicon film deposited on the source and drain.
  • a method for selectively depositing a silicon film on the source and drain regions is a method for selectively depositing an extremely flat silicon film with a small facet in a region surrounded by an insulating film, which is required in the M0SFET manufacturing process. As described in Japanese Patent Application Laid-Open No. 60-60716, this has been realized by making the exposed area of the silicon substrate surface larger than the exposed area of the insulating film.
  • the silicon film stacked on the source and drain regions is an insulating film for element isolation. Facets are likely to occur in the silicon film due to contact with the insulator spacer of the film gate from the beginning of growth. As a result, a high melting point metal film such as a titanium film or a tungsten film is deposited on the silicon film in the wiring process. When stacked, these metal films penetrate deeper into the portion where the facet has occurred on the semiconductor substrate side, causing a problem that a leak current is generated.
  • a method of selectively embedding a silicon film having a small facet in a region surrounded by an insulating film is as follows: the exposed area of the silicon substrate surface is made larger than the exposed area of the insulating film. Therefore, the circuit design when integrating transistors, resistors, and capacitors was limited.
  • An object of the present invention is to provide a facet at a portion where an insulator spacer next to a gate electrode contacts a selectively grown silicon film or a portion where an insulating film for element isolation contacts a selectively grown silicon film. It is an object of the present invention to provide a MOSFET structure and a manufacturing method capable of depositing a selective silicon film having a small thickness irrespective of a silicon substrate surface or an area ratio of an insulating film. Disclosure of the invention
  • the selective silicon film In order to reduce the facet at the part where the insulator film next to the insulating film for element isolation and the gate and the selectively grown silicon film are small, the selective silicon film must be deposited on the silicon substrate surface. As shown in FIG. 1, the portion where the silicon substrate surface contacts the insulating film for element isolation and the portion where the silicon substrate surface contacts the insulating spacer are shown in FIG. This is achieved by forming a structure in which a part of the selective silicon film 111 can be cut under the insulator spacer 108.
  • the structure in which a part of the selective silicon film bites under the insulating film for element isolation or the insulator spacer is formed by heat-treating the silicon substrate in vacuum or a hydrogen atmosphere before depositing the selective silicon. it can.
  • the following method is used. As shown in the figure, before depositing the selective silicon film, the etching region 201 lowering the silicon substrate surface of the source and drain regions to the silicon substrate side with respect to the insulating film for element isolation and the insulator spacer. This is achieved by providing a structure that provides
  • the structure in which the silicon substrate surface in the source and drain regions is lowered to the silicon substrate side with respect to the insulating film for element isolation and the insulator spacer is that the silicon substrate is treated with hydrochloric acid gas or tri-metal before deposition of the selective silicon. It can be formed by etching with nitrogen fluoride gas or chlorine trifluoride gas. In addition, it can also be formed by wet etching using a mixed solution of hydrofluoric acid and nitric acid / hydrazine instead of gas phase etching using gas.
  • the source / drain regions come into contact with the oxide for element isolation, and the source / drain regions come into contact with the insulator spacer next to the gate electrode.
  • a plurality of crystal planes appear in the region where the portion of the selective silicon film cuts into the portion.
  • facets are less likely to be formed in the selective silicon film deposited in the biting region. Therefore, a selective silicon film with a small facet can be deposited regardless of the area ratio between the silicon surface and the insulating film.
  • FIG. 1 shows where the source and drain regions and the oxide for element isolation are in contact.
  • FIGS. 14 to 25 are cross-sectional views of main parts for explaining the second embodiment
  • FIG. FIG. 27 is a computer system configuration diagram for explaining Example 3
  • FIG. 27 is an optical transmission system configuration diagram for explaining Embodiment 4
  • FIG. 28 is a signal transmission processing device configuration for explaining Embodiment 5
  • FIG. 2 to FIG. 13 are cross-sectional views of essential parts for describing the present embodiment.
  • An oxide film 101 for element isolation is formed on one surface of the substrate 100, which is a part of the silicon wafer having a P-type crystal orientation (100) plane, by the well-known LOCOS method. Formed. The thickness of the oxide film is 350 nm.
  • an oxide film 102 having a thickness of 5 nm is formed by wet oxidation, and a polycrystalline silicon film 103 having a thickness of 200 nm is formed on the oxide film 102 by decompression chemical vapor deposition.
  • a polycrystalline silicon film 103 having a thickness of 200 nm is formed on the oxide film 102 by decompression chemical vapor deposition.
  • a polycrystalline silicon film 103 was added by a known photolithography technique.
  • the width of the polycrystalline silicon film 103 is 0.2 ⁇ .
  • phosphorus was implanted by an ion implantation method to form an ⁇ -type impurity region 106 in the source region 104 and the drain region 105.
  • the conditions for ion implantation are an acceleration voltage of 25 keV and a dose of 5 ⁇ 10 13 / cm 2 .
  • Oxide film 1 0 7 Has a thickness of 300 nm.
  • the oxide film 107 was etched by anisotropic etching to form an insulator spacer 108.
  • the structure shown in Fig. 6 was completed.
  • arsenic was implanted into the source region 104 and the drain region 105 by ion implantation to form an n-type impurity region 109.
  • the ion implantation conditions were an acceleration voltage of 40 keV and a dose of 2 ⁇ 10 le Zcm 2 c. The above process completed the structure shown in FIG.
  • the oxide film 102 on the source region 104 and the drain region 105 was removed by immersion in a hydrofluoric acid solution. Through the above process, the structure shown in Fig. 8 was completed.
  • the source region 104 and the drain region 105 become under-exposed at the portion where they contact the oxide film 101 and the oxide film 108.
  • a cut region 110 was formed.
  • the pressure during the heat treatment is 0.01 Pascal.
  • the silicon film 111 was selectively formed on the source region 104, the drain region 105, and the polycrystalline silicon film 103 in the same reduced pressure chemical vapor deposition apparatus.
  • the conditions for forming the silicon film 111 are as follows: growth temperature 750 ° C, growth pressure 100 Pascal, dichlorosilane gas flow 10 OccZ, hydrogen chloride gas flow l OccZ, hydrogen gas flow 1 It is Ritano minutes.
  • the thickness of the silicon film 111 is 100 nm.
  • a titanium film with a thickness of 1 0 0 nm is deposited on the entire surface by sputtering, and heat-treated in a nitrogen atmosphere 7 0 0 e C, 1 min. Then immerse in hydrogen peroxide solution As a result, the titanium film on the oxide film 101 and the insulator spacer 108 is removed, and the titanium silicide film 112 is replaced with the source region 104, the drain region 105 and the polycrystalline silicon film 1. 0 3 formed on. The sheet resistance of the titanium silicide film 112 was 25 ⁇ .
  • a contact hole is formed in the upper part of the titanium silicide film 112 by photolithography technology, a tungsten film is buried, and the source electrode 114, the gate electrode 115, and the gate electrode 115 are formed by photolithography technology. Drain electrodes 1 16 were formed.
  • the nMOSFET shown in Fig. 13 was completed.
  • a pMOSFET can be fabricated by changing the conductivity type of the substrate and the elements to be implanted.
  • CM0SFET can be fabricated by combining nMOSFET and pMOSFET.
  • a titanium film was used in the present invention, similar results were obtained by using tungsten, cobalt, molybdenum, tantalum, nickel, and platinum.
  • a silicon single crystal wafer is used as the substrate 100, but an SII wafer may be used.
  • the nMOSFET described in the present invention has a structure in which the silicon film 111 is stacked on the source region 104 and the drain region 105, whereby the sheet resistance of the titanium silicide film is reduced, and the gate width is 0.2 ⁇ .
  • the following worked properly.
  • the mutual inductance was 350 milli-Siemens / ⁇ at a power supply voltage of 2 V, and the CM0SFET The delay time of the barta was 4 Os.
  • a hydrogen gas was introduced into the decompression vapor phase growth apparatus at the time of forming the undercut region 110, and the undercut region 110 was formed by heat treatment in a hydrogen atmosphere. You may.
  • FIG. 14 to FIG. 25 are cross-sectional views of essential parts for explaining the present embodiment.
  • a substrate 100 which is a part of a silicon wafer having a P-type crystal orientation (100) plane
  • an oxide film 101 for element isolation is formed on a peripheral portion of an element formation region by a well-known LOCOS method.
  • the thickness of the oxide film is 350 nm.
  • an oxide film 102 having a thickness of 5 nm is formed by wet oxidation, and a polycrystalline silicon film 103 having a thickness of 200 nm is formed on the oxide film 102 by decompression chemical vapor deposition.
  • a polycrystalline silicon film 103 was added by a well-known photolithography technique.
  • the width of the polycrystalline silicon film 103 is 0.2 ⁇ .
  • phosphorus was implanted by an ion implantation method to form an ⁇ -type impurity region 106 in the source region 104 and the drain region 105.
  • Ion implantation conditions are an acceleration voltage 2 5 ke V, a dose of 5 X 1 0 '3 cm 2 .
  • an oxide film 107 was formed by low pressure chemical vapor deposition.
  • the thickness of the oxide film 107 is 300 nm.
  • the oxide film 107 was etched by anisotropic etching to form an insulator spacer 108.
  • the structure described in Fig. 18 was completed.
  • arsenic was implanted into the source region 104 and the drain region 105 by ion implantation to form an n-type impurity region 109.
  • Conditions of the ion hitting Chikomi acceleration voltage 4 0 ke V, a dose of 2 X 1 0 '6 Zcm 2 was completed.
  • the oxide film 102 on the source region 104 and the drain region 105 was removed by immersion in a hydrofluoric acid solution. In the above steps, the structure shown in FIG. 20 was completed.
  • the silicon substrate 100 and the polycrystalline silicon film 103 exposed to the source region 104 and the drain region 105 are etched by hydrogen chloride gas in a decompression chemical vapor deposition apparatus.
  • An etched area 201 was formed.
  • the etching conditions were a processing temperature of 900 ° C, a processing time of 2 minutes, a hydrogen chloride gas flow rate of 100 OccZ, a hydrogen gas flow rate of 1 litterano, and a processing pressure of 100 pass pressure.
  • a silicon film 111 was selectively formed on the source region 104, the drain region 105, and the polycrystalline silicon film 103 in the same low pressure chemical vapor deposition apparatus.
  • the conditions for forming the silicon film 111 are as follows: growth temperature 750 ° C, growth pressure 100 Pascal, dichlorosilane gas flow 10 OccZ, hydrogen chloride gas flow 1 OccZ, hydrogen gas flow 1 Litter minutes.
  • the thickness of the silicon film 111 is 100 nm.
  • a titanium film was deposited on the entire surface to a thickness of 100 O nm by a sputtering method, and was heat-treated at 700 ° C. for 1 minute in a nitrogen atmosphere. Then, the titanium film on the oxide film 101 and the insulator spacer 108 was removed by immersion in a hydrogen peroxide solution, and the titanium silicide film 112 was replaced with the source region 104 and the drain region 100. 5 and the polycrystalline silicon film 103. The sheet resistance of the titanium silicide film 112 was 25 ⁇ / port. Structure shown in Fig. 23 in the above process was completed.
  • an oxide film with a thickness of 1 ⁇ m was deposited on the entire surface by decompression chemical growth, an S0G (Spin On Glass) film was deposited, and the surface was flattened by a well-known etch-back method. An oxide film 113 was formed. Through the above steps, the structure shown in Fig. 24 was completed.
  • a contact hole is formed in the upper part of the titanium silicide film 112 by photolithography technology, a tungsten film is buried, and the source electrode 114, the gate electrode 115, and the drain electrode are formed by photolithography technology. A pole 1 1 6 was formed.
  • the nMOSFET shown in Fig. 25 was completed.
  • a pMOSFET can be fabricated by changing the conductivity type of the substrate and the elements to be implanted. Also, nMOSFET and pMOSFET can be made simultaneously to make CM0SFET. Furthermore, although a titanium film was used in the present invention, similar results were obtained when tungsten, cobalt, molybdenum, tantalum, niggel, and platinum were used. Further, in this embodiment, a silicon single crystal wafer is used as the substrate 100, but an SOI wafer may be used.
  • the nMOSFET described in the present invention has a structure in which the silicon film 111 is stacked on the source region 104 and the drain region 105, so that the sheet resistance of the titanium silicide film can be reduced and the gate width 0.2. It operated normally even under ⁇ .
  • the mutual inductance was 350 millimeters Zmm at a supply voltage of 2 V, and the delay time of the CM0SFET inverter at no load was 4 Ops.
  • the etching region 201 may be formed by introducing nitrogen trifluoride gas into the decompression vapor phase growth apparatus when the etching region 201 is formed. Similarly, the etched area 201 The etching region 201 may be formed by introducing chlorine trifluoride gas into the depressurized vapor phase epitaxy apparatus at the time of forming the etching.
  • the etching region 201 may be formed by using a mixed solution of hydrogen fluoride water and nitric acid when the etching region 201 is formed. Similarly, when the etching region 201 is formed, the etching region 201 may be formed with a hydrazine solution.
  • a third embodiment of the present invention will be described with reference to a computer system configuration diagram in FIG.
  • a high-speed silicon semiconductor integrated circuit constituted by the semiconductor device according to any one of the first and second embodiments is replaced by a high-speed processor 500 in which a plurality of processors 500 for processing instructions and operations are connected in parallel.
  • a processor 500 for processing instructions and arithmetic operations a system control device 501, a main storage device 502, and the like are provided. It could be composed of about 10 to 3 silicon semiconductor chips on one side.
  • a processor 503 for processing these instructions and operations, a system controller 501, and a data communication interface 503 composed of a compound semiconductor integrated circuit were mounted on the same ceramic substrate 506.
  • the data communication interface 503 and the data communication control device 504 were mounted on the same ceramic substrate 507.
  • These ceramic substrates 506 and 507, and the ceramic substrate on which the main memory device 502 is mounted, are mounted on a substrate with a side of about 5 Ocm or less, and the center of a large computer.
  • a processing unit 508 was formed. The data communication within the central processing unit 508, the data communication between a plurality of central processing units, or the data communication interface 503 and the board 509 on which the input / output processor 505 is mounted.
  • the data communication was performed via the optical fiber 510 indicated by the double-headed arrow lines in the figure.
  • Silicon semiconductor integrated circuits such as a processor 503 that processes commands and calculations, a system controller 501, and a main memory 502, operate at high speed in parallel, and use optical media to communicate data. As a result, the number of instructions processed per second was greatly increased.
  • FIG. 27 is an optical transmission system configuration diagram showing the fourth embodiment.
  • one of the semiconductor devices according to the first and second embodiments is applied to both the optical transmission module 613 for transmitting data at an extremely high speed and the optical receiving module 614 for receiving the data.
  • the semiconductor device manufactured according to any one of the first and second embodiments is used to drive the multiplex conversion digital circuit 6001 for processing the transmission-side electric signal 610 and the semiconductor laser 603.
  • An optical transmitter module 613 comprising a semiconductor laser-driven analog circuit 602 of the present invention, and a receiving-side electrical signal 612 obtained by converting the transmitted optical signal 611 by a photodiode 604.
  • the optical receiving module 6 1 4 was configured. Since the semiconductor device manufactured according to the above-described embodiment can operate at an ultra-high speed, a large-capacity signal of 10 Gbits per second can be transmitted and received at an ultra-high speed.
  • the fifth embodiment relates to a signal transmission processing device 700 constituted by a semiconductor device manufactured based on any one of the first and second embodiments, and particularly relates to an asynchronous transmission system (referred to as an ATM switch).
  • Signal transmission processing device 700 relating to In Fig. 28, the input optical signal transmitted in series at a very high speed by the optical fiber 70 1
  • Reference numeral 700 denotes an M0SFET manufactured based on any of the first and second embodiments of the present invention via a converter 703 for converting (0 / E conversion) and parallelizing (SZP conversion) an electric signal.
  • the electric signal subjected to address processing in the integrated circuit 704 is serialized (P / S conversion) and converted to an optical signal (E / 0 conversion) by the conversion device 705, and is output from the optical fiber 706.
  • the integrated circuit 704 includes a multiplexer 707, a buffer memory 708, and a separator 709.
  • the integrated circuit 704 is controlled by a memory control LSI 710 and an empty address distribution control LSI 711.
  • the signal transmission processing device 700 is a device having a function of a switch for transmitting an input optical signal 720 transmitted irrespective of an address to be transmitted to a desired address at a very high speed.
  • the converging circuit 704 is constituted by the M0SFET manufactured according to any one of the first and second embodiments, so that it operates compared to the conventional integrated circuit 704. Since the speed is three times as fast and inexpensive, it has become possible to reduce the storage capacity of the integrated circuit 704 to about one third of that of the conventional one. As a result, the manufacturing cost of ATM switches could be reduced.
  • the parts where the silicon substrate surface contacts the insulating film for element isolation and the parts where the silicon substrate surface contacts the insulator spacer are shown in FIG.
  • a facet generated in the selected silicon film is formed. Can be made smaller.
  • the silicon substrate is heat-treated in a vacuum or in a hydrogen atmosphere to form a structure in which a part of the selective silicon film bites under the insulating film for element isolation or the insulator spacer.
  • This step can be performed in an apparatus for forming a selective silicon film. As a result, there is an effect that the manufacturing process can be simplified.
  • a structure is provided in which an etching region 201 for lowering the silicon substrate surface of the source and drain regions to the silicon substrate side is provided for the insulating film for element isolation and the insulator spacer.
  • the facets generated in the selected silicon film can be reduced.
  • the silicide film it is possible to prevent the silicide film from penetrating deeply into the silicon substrate at a portion where the selective silicon film and the insulating film for element isolation or the insulator spacer are in contact with each other. This has the effect of suppressing leakage current.
  • the step of forming an etching region on the silicon substrate with a hydrochloric acid gas, a nitrogen trifluoride gas, or a chlorine trifluoride gas before the deposition of the selective silicon can be performed in a selective silicon film forming apparatus.
  • a hydrochloric acid gas, a nitrogen trifluoride gas, or a chlorine trifluoride gas before the deposition of the selective silicon can be performed in a selective silicon film forming apparatus.
  • wet etching using a mixture of hydrofluoric acid and nitric acid / hydrazine instead of gas phase etching using gas, has the effect of making the surface of the etching region flatter than gas phase etching.
  • the present invention is directed to a selective silicon having a small facet at a portion where an insulator spacer next to a gate electrode contacts a selectively grown silicon film or at a portion where an insulating film for element isolation contacts a selectively grown silicon film.
  • Put the film on the silicon substrate It provides a MOSFET structure and manufacturing method that can be deposited regardless of the area ratio of the insulating film. This is useful for circuit design when integrating transistors, resistors, and capacitors.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Structure MOS à effet de champ dans laquelle on utilise un film de silicium cultivé sélectivement et comprenant de petites facettes aux endroits qui sont au contact d'éléments d'écartement formés d'un isolant à proximité d'une électrode de grille et d'un film isolant l'élément, cette structure étant indépendante du rapport des surfaces du substrat de silicium et du film isolant. Etant donné que le silicium est attaqué chimiquement dans les régions de source et de drain, des faces cristallines apparaissent sous l'oxyde isolant l'élément et les éléments d'écartement isolants. Il en résulte que les facettes sont pratiquement absentes dans le film de silicium cultivé sélectivement, sous l'oxyde et les éléments d'écartement.
PCT/JP1995/000592 1995-03-29 1995-03-29 Dispositif semi-conducteur et son procede de fabrication WO1996030946A1 (fr)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2355583A (en) * 1999-06-29 2001-04-25 Hyundai Electronics Ind Method of forming a transistor having elevated source and drain regions
US6884669B2 (en) 2003-01-17 2005-04-26 Taiwan Semiconductor Manufacturing Co., Ltd. Hatted polysilicon gate structure for improving salicide performance and method of forming the same
US7015126B2 (en) 2004-06-03 2006-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming silicided gate structure
US7064085B2 (en) 2004-07-20 2006-06-20 Taiwan Semiconductor Manufacturing Company Feed forward spacer width control in semiconductor manufacturing
US7241674B2 (en) 2004-05-13 2007-07-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming silicided gate structure
US7396767B2 (en) 2004-07-16 2008-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure including silicide regions and method of making same
JPWO2007007375A1 (ja) * 2005-07-07 2009-01-29 富士通マイクロエレクトロニクス株式会社 半導体装置およびその製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6313379A (ja) * 1986-07-04 1988-01-20 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法
JPS63312679A (ja) * 1987-06-16 1988-12-21 Fujitsu Ltd 電界効果型半導体装置およびその製造方法
JPH01268061A (ja) * 1988-04-20 1989-10-25 Hitachi Ltd 半導体装置
JPH02174166A (ja) * 1988-12-26 1990-07-05 Sharp Corp 化合物半導体の製造方法
JPH0786586A (ja) * 1993-09-17 1995-03-31 Toshiba Corp 半導体装置及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6313379A (ja) * 1986-07-04 1988-01-20 Nippon Telegr & Teleph Corp <Ntt> 半導体装置およびその製造方法
JPS63312679A (ja) * 1987-06-16 1988-12-21 Fujitsu Ltd 電界効果型半導体装置およびその製造方法
JPH01268061A (ja) * 1988-04-20 1989-10-25 Hitachi Ltd 半導体装置
JPH02174166A (ja) * 1988-12-26 1990-07-05 Sharp Corp 化合物半導体の製造方法
JPH0786586A (ja) * 1993-09-17 1995-03-31 Toshiba Corp 半導体装置及びその製造方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2355583A (en) * 1999-06-29 2001-04-25 Hyundai Electronics Ind Method of forming a transistor having elevated source and drain regions
GB2355583B (en) * 1999-06-29 2004-04-14 Hyundai Electronics Ind Method of manufacturing a transistor having elevated source and drain regions
US6884669B2 (en) 2003-01-17 2005-04-26 Taiwan Semiconductor Manufacturing Co., Ltd. Hatted polysilicon gate structure for improving salicide performance and method of forming the same
US7241674B2 (en) 2004-05-13 2007-07-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming silicided gate structure
US7015126B2 (en) 2004-06-03 2006-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming silicided gate structure
US7396767B2 (en) 2004-07-16 2008-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure including silicide regions and method of making same
US7064085B2 (en) 2004-07-20 2006-06-20 Taiwan Semiconductor Manufacturing Company Feed forward spacer width control in semiconductor manufacturing
JPWO2007007375A1 (ja) * 2005-07-07 2009-01-29 富士通マイクロエレクトロニクス株式会社 半導体装置およびその製造方法

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