JPH10303385A - Hybrid element formed on simox or stuck soi substrate and method for producing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To highly integrally form high-performance hybrid elements. SOLUTION: A silicon substrate 3 is exposed by selectively removing a silicon layer 1 and an insulating layer 2 from a silicon-on-insulator(SOI) substrate, and desired semiconductor elements 11 are respectively formed on the exposed silicon substrate 3 and the silicon layer 1. It is preferable that a logic circuit 13 of DRAM is formed on the silicon layer 1 and a memory cell part 11 of DRAM is formed on the silicon substrate 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a SIMOX (Separ
ation by IMplanted OXgen) or SOI
(Silicon On Insulator) A semiconductor device using a substrate and a method of manufacturing the same, particularly, a dynamic random access memory (hereinafter, DRAM) on such a substrate
And a method of manufacturing a hybrid structure in which memory cells and logic circuits are mixed.

[0002]

2. Description of the Related Art Many semiconductor devices including DRAMs have realized high integration and high performance by reducing the element size. However, the increase in the electric field inside the device due to miniaturization makes it difficult to secure the reliability of the device for a long time. For this reason, it is necessary to reduce the power supply voltage as the elements are miniaturized. In addition, with the spread of portable devices that are expected to operate for a long time using a battery, it is important to lower the power supply voltage in order to reduce power consumption.

[0003]

However, when the power supply voltage is reduced, if the threshold voltage of the transistor is not scaled, the current driving capability is reduced and the performance of the device is deteriorated. Fully depleted SOI (hereinafter FDSO)
I) The threshold voltage of the device or element can be reduced by making the thickness of the silicon layer smaller than the maximum depletion layer width. For this reason, power consumption can be reduced without deteriorating the current driving capability of the device when the power supply voltage decreases. However, since the FDSOI device does not have a substrate terminal, it is difficult to increase the threshold value and reduce the cutoff current by applying a substrate bias as in a bulk device.

[0004] Therefore, it is not suitable for a device that stores information by retaining charges in a capacitor, such as a DRAM. On the other hand, for a bulk device, the cutoff current can be reduced by applying the substrate bias as described above, but the junction capacitance of the drain region increases with a decrease in the power supply voltage, and the short channel effect is suppressed. It is difficult to lower the threshold voltage while increasing the speed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has as its object to provide a semiconductor device and a method of manufacturing the same, which make use of the advantages of an SOI device and a bulk device.

Another object of the present invention is to provide a method capable of forming a dynamic memory on an SOI substrate and lowering a power supply voltage and a threshold value of a transistor while scaling elements.

[0007]

In a conventional hybrid device formed on a bulk substrate, it has been difficult to realize the charge retention of the DRAM and the high performance of the logic circuit. By forming a portion in a portion without a buried oxide film and forming a logic circuit of a DRAM composed of a transistor of a fully depleted SOI in a portion with a buried oxide film, the DRAM has better charge retention and a logic portion. Then, a high-speed circuit is realized.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1A to 1F are sectional views showing steps used in a first embodiment of the present invention.

In this embodiment, a method for manufacturing a DRAM using an SOI wafer will be described.

First, as shown in FIG. 1A, an SOI wafer having a single crystal silicon layer 1 formed on a single crystal silicon substrate 3 via a silicon oxide film 2 is prepared. Typical recent SOI wafers include a bonded silicon wafer and a SIMOX wafer.

The bonded silicon wafer is obtained by bonding two wafers. In this method, a single crystal silicon wafer and a silicon wafer on which an oxide film is formed are bonded by heat treatment, and then one of the silicon wafers is polished to form a thin silicon single crystal layer into an insulating film (SiO 2).
₂ ) Leave on top.

In the SIMOX wafer, oxygen ions are implanted at a predetermined depth from the surface of the silicon wafer and heat-treated to form an oxide film buried under the vicinity of the surface, thereby forming an oxide film on the buried oxide film. A silicon single crystal can be formed.

In this embodiment, for example, the silicon substrate 3
Is about 600 μm, the impurity concentration of boron (B) dopant is about 10 ¹⁵ cm ⁻³ , the thickness of the silicon oxide film 2 is about 1000 Å, and the thickness of the silicon layer 1 is about 2
An SOI having an impurity concentration of 2,000 angstroms and boron dopant of about 10 ¹⁵ cm ⁻³ is prepared.

The silicon layer 1 is a completely depleted SOIMO
Thereafter, the film is thinned by sacrificial oxidation to form an SFET. The final thickness of the silicon layer 1 is made smaller than the maximum depletion layer width. The maximum depletion layer width cannot be specified because it varies depending on the channel concentration, but the maximum depletion layer width W is approximated by the following equation when no substrate bias is applied.

[0015]

(Equation 1)

Here, if the channel concentration of the silicon layer 1 is 5 × 10 ¹⁷ cm ⁻³ , W becomes about 480 Å. Therefore, a fully depleted SOI MOSFET
Is required to make the thickness of the silicon layer 1 thinner than this.

Next, as shown in FIG. 1B, a resist mask layer 4 patterned by a general photolithography process is formed on the SOI substrate.

Next, as shown in FIG. 1C, using the mask layer 4 as a mask, the silicon layer 1 and the silicon oxide film 2 are removed by anisotropic dry etching.
To expose. As the etching gas, it is preferable to use a gas having selectivity to silicon and a silicon oxide film. In this case, since the laminated structure of silicon / silicon oxide film / silicon is used, the etching gas may be switched on the way. It is also preferable to perform etching for removing damage after the etching. For example, by adding hydrogen to a fluorine-based gas in order to obtain selectivity between an oxide film and silicon, selective etching of the oxide film and silicon can be performed. Fluorine (F) allows for less selective etching of both silicon and oxide films, while
Hydrogen fluoride (HF) enables highly selective etching that etches oxide films much more strongly than silicon. In other words, hydrogen consumes fluorine in the reaction system, so that silicon is hardly etched. Also,
In order to remove the damage caused by etching, CDE
(Chemical Dry Etching) may be used to remove the damaged layer with fluorine radicals (low energy).

Next, in order to form a well as an element formation region in the silicon substrate 3, BF ₂ is applied to the silicon substrate 3 via the mask layer 4 at a dose of 8 × 10 ¹² cm.
Ion implantation is performed at ^-2 (see FIG. 1D). After the mask layer 4 is removed by ashing, annealing is performed to diffuse impurities to form a P-type well 5 having an impurity concentration of 5 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ (see FIG. 1E). .

In this embodiment, in such an SOI substrate, a DRAM memory cell portion is formed in a well 5 of a silicon substrate 3 and a logic circuit (input / output buffer, input / output buffer, Address decoder, sense amplifier circuit, etc.).

As is well known, a memory cell includes one access transistor having a gate coupled to a word line and one capacitor for storing electric charge. As shown in FIG. 1F, an access n-type MOS transistor 11 and a capacitor 12 coupled to a source region which is a common node with the n-type MOS transistor 11 are formed in a P well 5 of a silicon substrate 3.

The MOS transistor 11 formed on the silicon substrate 3 operates in the same manner as a transistor formed on a normal bulk silicon substrate. On the other hand, when the MOS transistor 11 is a thin film such as the silicon layer 1, it is formed there. The depleted transistor operates as a fully depleted transistor because the width of the depletion layer is limited by the thickness of the silicon layer. Therefore, by applying a substrate bias to the well 5, the threshold value of the access MOS transistor 11 formed therein can be increased. Therefore, the cut-off current can be reduced and the charge retention characteristics of the memory cell can be improved while taking into account the short (short) channel effect of the access transistor which has been reduced for high integration.

The substrate bias generating circuit can be composed of an oscillating circuit and a pump circuit connected to the oscillating circuit. These circuits are formed on the silicon layer 1 as described later, and the output terminal thereof is connected to the well 5. To do it.

In the drawings, one transistor and one transistor
Although a memory cell including one capacitor is shown as an example, such a memory cell can be arranged in a matrix to form a memory array. In this case, the element region of each memory cell formed in the well is electrically insulated by a well-known field oxide film or trench.

In the silicon layer 1 on the buried oxide film 2,
Logic circuits such as a matrix address decoder, a sense amplifier, an input / output buffer, various driving circuits, and a control circuit are formed. FIG. 1F shows a MOS transistor 13 constituting such a logic circuit. Since the transistor formed in the silicon layer 1 is operated as a fully depleted type, its threshold can be lowered,
As a result, the speed can be increased.

In these transistors, a source / drain region 14 is formed in a self-aligned manner in the silicon layer 1 by ion-implanting a dopant of a predetermined conductivity type using, for example, a polysilicon gate as a mask. I do. Reference numeral 15 denotes a passivation film.

Further, since a step is generated between the silicon layer 1 and the silicon substrate 3 in advance, an electrical wiring connection between the logic circuit and the memory cell (for example, a wiring of the gate of the access transistor and a wiring of the word line driving circuit). It is desirable to have flatness so as not to hinder ()). In particular, since the capacitor has a three-dimensional structure in order to guarantee the charge capacity of the memory cell capacitor with high integration,
In such a case, the step may be adjusted according to the thickness of the silicon oxide film 2.

Next, a second embodiment of the present invention will be described with reference to process sectional views shown in FIGS.

First, as shown in FIG. 2A, a patterned mask layer 22 is formed on a P-type single crystal silicon substrate 21.

Next, as shown in FIG. 2B, oxygen ions are implanted into the silicon substrate 21 by ion implantation using the mask layer 22 as a mask.

Next, as shown in FIG. 2C, the mask layer 22 is removed, and then annealing is performed at about 1300 ° C. for about 6 hours.
An angstrom buried oxide film 23 is formed.

Next, as shown in FIG. 2D, an oxide film 24 for element isolation is formed. This is to pattern a general silicon nitride film and selectively oxidize the silicon substrate 21. In this case, since the silicon of the silicon substrate 21 is provided to the silicon oxide film, the oxide film 24 grows in the substrate so as to be connected to the buried oxide film 23. Thus, an SOI structure is obtained in which an element region 25 (thickness of about 400 Å) which is electrically insulated by the oxides 23 and 24 is formed.

Next, as shown in FIG. 2E, a mask layer 26 for masking the SOI portion is formed, and the silicon substrate 2
BF ₂ is ion-implanted into the entire surface of the substrate 1 to form impurity regions in the silicon substrate region other than the mask layer 26. Thereafter, annealing is performed to form a P-type well 27 in the silicon substrate.

Next, as shown in FIG. 2 (g), a logic circuit composed of a fully depleted transistor 28 is formed in the silicon layer where the buried oxide film 23 is located, and a DRAM is formed in the silicon substrate 21. Is formed, and a passivation film 30 is formed thereon.

In the case of the second embodiment, the region where the logic circuit is formed and the region where the memory cell is formed are on the same plane, while the thickness of the silicon layer where these depletion layers are to be formed is reduced. different.

[0036]

According to the present invention, using a SIMOX or a bonded SOI substrate, a DRAM memory cell is formed on a silicon substrate after a silicon layer and a buried oxide film are removed by etching, and a fully depleted SOI transistor is formed. By forming the logic circuit constituted by the silicon layer on the silicon layer, the cutoff current can be reduced, the charge retention can be improved, and the logic circuit can be operated at high speed on the same wafer.

[Brief description of the drawings]

FIGS. 1A to 1F are views showing a semiconductor manufacturing process according to a first embodiment of the present invention.

FIGS. 2A to 2G are diagrams showing a semiconductor manufacturing process according to a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 silicon layer 2 silicon oxide film 3 silicon substrate 11 access transistor 12 capacitor 13 transistor

Claims (6)

[Claims] 1. A method for manufacturing a semiconductor device on an SOI substrate including a silicon substrate, an insulating layer, and a silicon layer, comprising: preparing the SOI substrate; and selectively removing the silicon layer and the insulating layer from the SOI substrate. Exposing the silicon substrate, and forming a semiconductor element on each of the exposed silicon substrate and the silicon layer. 2. The semiconductor manufacturing method according to claim 1, wherein the semiconductor element formed on the silicon layer includes a logic circuit including a fully depleted transistor of a dynamic memory, and the element formed on the silicon substrate is a dynamic memory. A semiconductor manufacturing method comprising a memory cell portion of a memory. 3. A patterned mask layer is formed on a silicon substrate, oxygen ions are implanted into the silicon substrate including the mask layer, and the silicon substrate is annealed by burying an oxide film to a predetermined depth. A logic circuit including a fully depleted transistor is formed on a silicon portion on the buried oxide film, and a memory cell portion of the dynamic memory is formed on a silicon substrate portion on which the buried oxide film is not formed. A method for manufacturing a semiconductor device, comprising: 4. A semiconductor device formed on an SOI substrate including a silicon substrate, an insulating layer and a silicon layer, comprising: a semiconductor element formed on each of the silicon substrate and the silicon layer. . 5. The semiconductor device according to claim 4, wherein a logic circuit of a dynamic memory including a fully depleted transistor is formed in the silicon layer, and a memory cell portion of the dynamic memory is formed on the silicon substrate. A semiconductor device characterized by the above-mentioned. 6. The semiconductor device according to claim 5, wherein the memory cell unit includes a plurality of memory cell arrays each including an access transistor and a capacitor, and a substrate bias is applied to the memory cell unit. apparatus