JPH01286308A - Manufacture of gallium arsenide field effect transistor - Google Patents

Abstract

PURPOSE:To obtain a carrier concentration profile optimum as an n-type active area by implanting ions of V group element with implantation energy higher than that for Si<+> ions into an area intended for an active area before or after Si<+> ion implantation and then annealing them. CONSTITUTION:An n-type active area 3 is formed by annealing ions of group V elements P and Sn after implanting them with implantation energy higher than that for Si<+> ions into the area intend for an active area 3 before or after Si<+> ion implantation. Hereby, carrier concentration at a place deeper than the peak of element concentration of Si<+> implantation can be sharply increased and further the tail part of carrier concentration can be made not to change much as when there is no implantation of the group V elements P and Sn, therefore practically high carrier concentration as an FET conductive layer can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a GaAs semi-insulating substrate formed on a GaAs semi-insulating substrate.
The present invention relates to field effect transistors (FETs), particularly MESFETs with Schottky gates.

[Conventional technology]

Conventionally, this type of MES FET was made by injecting Si+ ions and enlarging them, and then depositing an insulating film as a protective film.
It was common to perform annealing at a high temperature of 7° C. or higher to electrically activate the implanted Si+ ions to form an n-type conductive layer and form an active region.

[Problem to be solved by the invention]

In forming the active region by Si + ion implantation, the Si element is an amphoteric impurity with respect to GaAs, so when substituted in the lattice position of As, it functions as a p-type impurity, and conversely, it acts as a p-type impurity with respect to GaAs.
When substituted at a lattice position, it functions as an n-type impurity.

By the way, during high-temperature annealing, As evaporates and A
Due to the generation of s-vacancies, the number of hole carriers increases and the effective electron carrier concentration significantly decreases. Therefore, in order to obtain the required electron concentration, it is necessary to increase the implantation dose, which results in a decrease in the mobility of the active region, which adversely affects the characteristics of the device. In addition, the implanted SI exhibits a Gaussian distribution determined by the implantation energy and dose, and combined with the narrow degree of freedom in selecting the carrier concentration profile, it is difficult to obtain an effectively high carrier density as a conductive layer of an FET. Ta.

The aim of the present invention is to eliminate the above-mentioned drawbacks and to improve GaA s F
An object of the present invention is to provide a manufacturing method that can obtain an optimal carrier concentration profile for an n-type active region of an ET.

[Means to solve the problem]

In forming an n-type active region of a GaAsFET, the present invention implants Group V element ions into at least the region intended as the active region before or after implanting St'' ions into a GaAs semi-insulating substrate. After the implantation is performed with a higher implantation energy than the implantation energy, annealing is performed.

[Effect]

By implanting the V group element before 7 anneals, As vacancies can be reduced, so that the ratio of substitution of St to Ga lattice rows by Si + ion implantation becomes relatively large. Furthermore, by making the implantation energy of the V group element higher than the Si+ ion implantation energy, the carrier concentration increases even when the carrier concentration profile of Si+ ion single implantation exceeds the peak, as shown in the example.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view of the embodiment.

Openings are made in the semi-insulating substrate l using photoresist 2, and 3+p+ is set at 140 keV and 1.5X 1013c.
After m-2 injection, 28Si+ was subsequently added? 0keV
, 5×10 12 cm −2 to obtain a multiple implant layer 3. Thereafter, the photoresist 2 was removed, and a SiO2 film 4 was deposited at 2000A by thermal CVD at 500°C or below, and annealed at 800"C for 20 minutes in H2 to electrically activate it. After obtaining the n-type active region 5, an AM gate electrode 6 is formed as a Schottky gate.
A uGe/Ni ohmic electrode 7 is formed.

FIG. 2 shows the ion implantation concentration and carrier concentration relative to the depth from the surface.

The profile of the implanted ions is a distribution according to the LSS theory, and the peak value of 31P+ occurs deeper than the peak value of 2aSi+.

It can be seen that the carrier concentration profile after annealing shows an increase in carriers after exceeding the peak of 283i+ compared to when only 283i+ is implanted, and approaches the carrier profile of only 283i+ implantation after passing the peak carrier concentration. .

Although 31p+ was implanted in the above example, 7SAS+ could be used as well. In this case, the atomic weight of As is 7
5, so in order to obtain the same carrier profile as in FIG. 2, it is necessary to significantly increase the energy of As+ ion implantation. However, if a double charge of As+10 is used, a similar carrier profile can be obtained with the same energy as when P10 is implanted.

〔Effect of the invention〕

As explained above, the present invention improves Si by implanting S1+ ions, which are impurity elements that form the active region of a GaAs FET, and implanting group V elements having a deeper peak depth of implanted ion concentration. It is possible to significantly increase the carrier concentration in a region deeper than the peak of the element concentration by implantation, and furthermore, the foot of the carrier concentration profile can be made not to change much from when no group V element is implanted.

This has the effect of significantly improving transconductance, which is a measure of the performance of FET characteristics.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view of an embodiment of the present invention, and FIG. 2 is an implanted ion profile and a carrier concentration profile in the depth direction of the active region. DESCRIPTION OF SYMBOLS 1... Semi-insulating substrate, 2... Photoresist, 3... Ion implantation region, 5... N-type active region, 6... A gate electrode, 7... A u G e / N i Ohmic electrode. Patent applicant: NEC Corporation Representative: Susumu Uchihara, patent attorney Figure 1

Claims (1)

[Claims] In a field effect transistor having an n-type active region formed by implanting Si^+ ions into a GaAs semi-insulating substrate, V
GaA, characterized in that an n-type active region is formed by implanting group element ions into at least the region intended as the active region at an implantation energy higher than Si+ ion implantation energy, and then annealing.
A method for manufacturing a field effect transistor.