JPH0226781B2 - - Google Patents

Info

Publication number
JPH0226781B2
JPH0226781B2 JP16204483A JP16204483A JPH0226781B2 JP H0226781 B2 JPH0226781 B2 JP H0226781B2 JP 16204483 A JP16204483 A JP 16204483A JP 16204483 A JP16204483 A JP 16204483A JP H0226781 B2 JPH0226781 B2 JP H0226781B2
Authority
JP
Japan
Prior art keywords
impurity
substrate
layer
implanted
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16204483A
Other languages
Japanese (ja)
Other versions
JPS6054479A (en
Inventor
Hiroshi Nakamura
Toshio Nonaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP16204483A priority Critical patent/JPS6054479A/en
Publication of JPS6054479A publication Critical patent/JPS6054479A/en
Publication of JPH0226781B2 publication Critical patent/JPH0226781B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 (技術分野) 本発明は化合物半導体を母材とした電界効果ト
ランジスタに関し、特にGaAsMESFETに関す
る。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a field effect transistor using a compound semiconductor as a base material, and particularly relates to a GaAs MESFET.

(従来技術) GaAsMESFETは、化合物半導体を母材とし
た電界効果トランジスタの最も代表的なものとし
て知られており、その基本的構成を第1図に示
す。
(Prior Art) GaAs MESFET is known as the most typical field effect transistor using a compound semiconductor as a base material, and its basic configuration is shown in FIG.

第1図において、1は半絶縁性のGaAs基板、
2はn+形のソース領域、3はn+形のドレイン領
域、4はn形の活性領域、5はソース電極、6は
ドレイン電極、7はシヨツトキ接合を形成するゲ
ート電極であり、各領域2,3,4は通常Siを不
純物として形成される。
In Figure 1, 1 is a semi-insulating GaAs substrate;
2 is an n + type source region, 3 is an n + type drain region, 4 is an n type active region, 5 is a source electrode, 6 is a drain electrode, and 7 is a gate electrode forming a Schottky junction. 2, 3, and 4 are usually formed using Si as an impurity.

このようなGaAsMESFETは、高純度基板を
用いてその表面層に形成することができ、また高
純度エピタキシヤル成長法によつて適当な基板上
に高純度エピタキシヤル成長層を形成し、その成
長層中に形成することもできる。
Such a GaAs MESFET can be formed on the surface layer of a high-purity substrate, or by forming a high-purity epitaxial growth layer on a suitable substrate by a high-purity epitaxial growth method, and then It can also be formed inside.

上述のような基板上に作成されたFETにおい
ては、基板内の残留不純物量は少ないので、注入
されたドナーの活性化率は安定し、FETのしき
い値電圧(以下VTという)の均一性は集積回路
の作製に十分なレベルまで向上する。しかし、そ
の際以下のような問題が生じる。
In FETs fabricated on the above-mentioned substrate, the amount of residual impurities in the substrate is small, so the activation rate of the implanted donors is stable and the threshold voltage (hereinafter referred to as V T ) of the FET is uniform. performance is improved to a level sufficient for the fabrication of integrated circuits. However, the following problems arise in this case.

それは、活性領域下のバンドの曲がり方が少な
くなるために、みかけ上チヤンネルが拡がり、
FETの飽和特性が弱くなり、三極管特性に近づ
くということである。三極管特性に近くなること
は、通常のGaAs論理回路の動作にとつては好ま
しくない。
This is because the band under the active region becomes less curved, causing the channel to apparently widen.
This means that the saturation characteristics of the FET become weaker, approaching the characteristics of a triode. Approaching triode characteristics is not desirable for normal GaAs logic circuit operation.

(発明の目的) 本発明の目的は、少なくとも表面層が高純度の
基板を出発材として、その表面に良好な飽和特性
と均一なVTとを有する電界効果トランジスタを
形成するにある。
(Objective of the Invention) An object of the present invention is to form a field effect transistor having good saturation characteristics and uniform V T on the surface of a substrate having at least a high purity surface layer as a starting material.

(発明の概要) 本発明では上記目的を達成するために電界効果
トランジスタ形成前に不純物をイオン注入してお
くことによつて、活性領域直下にアクセプタ不純
物を存在させ、これによつてチヤネルの拡がりを
抑制して飽和特性を向上させ、しかもその不純物
として深い準位のアクセプタ不純物を用いるか、
又は浅い準位のアクセプタ不純物と深い準位のド
ナ不純物を用いることによつて、ICなどで問題
となる基板リーク電流の増加を防止したものであ
り、また不純物のイオン打込を注意深く制御する
ことによつてVTの均一性を保つようにしたもの
である。
(Summary of the Invention) In order to achieve the above object, the present invention implants impurity ions before forming a field effect transistor so that acceptor impurities are present directly under the active region, thereby widening the channel. In order to improve the saturation characteristics by suppressing the
Alternatively, by using a shallow level acceptor impurity and a deep level donor impurity, an increase in substrate leakage current, which is a problem in ICs, is prevented, and the ion implantation of impurities is carefully controlled. The uniformity of V T is maintained by

(発明の実施例) 以下実施例について第1図を参照して説明す
る。
(Embodiments of the Invention) Examples will be described below with reference to FIG.

市販のGaAs基板(図示せず)上に、MOCVD
成長法(有機金属化学気相成長法)によつて厚さ
2.5μm〜3μm、残留不純物濃度は合計で1015cm-3
の高純度エピタキシヤル成長層1aを形成し、こ
れを基板1の表面から、浅い準位のアクセプタ不
純物として炭素のイオンを、深い準位のドナー不
純物として酸素のイオンをそれぞれ注入エネルギ
ー80KeV、100KeVで注入量は1×1012cm-2ずつ
注入し、炭素と酸素の共注入層である不純物層1
bを形成する。その不純物層1b内に、n形の活
性領域4並びにn+形のソース領域2およびn+
のドレイン領域3をSiイオンの注入により形成す
る。n形とn+形の注入エネルギーはそれぞれ
60KeV、100KeVであり、注入量はそれぞれ3×
1012cm-2、2×1013cm-2であり、アニールは800℃
20minである。なお、ゲート電極(W−Al合金
製)の寸法は1.7μm×10μmである。
MOCVD on a commercially available GaAs substrate (not shown)
Thickness determined by growth method (organometallic chemical vapor deposition)
2.5 μm to 3 μm, total residual impurity concentration 10 15 cm -3
A high purity epitaxial growth layer 1a of The implantation amount is 1×10 12 cm -2 , and the impurity layer 1 is a co-implanted layer of carbon and oxygen.
form b. In the impurity layer 1b, an n-type active region 4, an n + -type source region 2, and an n + -type drain region 3 are formed by implanting Si ions. The implantation energies of n-type and n + type are respectively
60KeV and 100KeV, and the injection amount is 3× each.
10 12 cm -2 , 2×10 13 cm -2 and annealing at 800℃
It is 20min. Note that the dimensions of the gate electrode (made of W-Al alloy) are 1.7 μm×10 μm.

第2図は炭素と酸素を各々1×1012cm-2ずつ注
入した高純度MOCVD基板上に作製したFETの
しきい値電圧近傍での静特性を示した図である。
FIG. 2 is a diagram showing the static characteristics near the threshold voltage of an FET fabricated on a high-purity MOCVD substrate into which carbon and oxygen were implanted at 1×10 12 cm −2 each.

第3図は、比較のために、炭素と酸素を注入し
ていない高純度MOCVD基板上に作成したFET
のしきい値電圧近傍での静特性を示した図であ
る。
For comparison, Figure 3 shows an FET fabricated on a high-purity MOCVD substrate without implanting carbon or oxygen.
FIG. 2 is a diagram showing static characteristics near the threshold voltage of .

第2図と第3図の対比から明らかなように、第
3図において見られたような三極管特性は第2図
において全く観測されていない。
As is clear from the comparison between FIG. 2 and FIG. 3, the triode characteristics seen in FIG. 3 are not observed at all in FIG.

これは活性領域下にイオン化したアクセプタが
多く存在するために活性領域下のバンドの曲がり
が大きくなり、活性領域下を通つて流れる電流が
減少したためであると考えることができる。
This can be considered to be because there are many ionized acceptors under the active region, which increases the bending of the band under the active region and reduces the current flowing under the active region.

以上のように浅い準位のアクセプタと深い準位
のドナーを共に注入した高純度基板を用いること
は、飽和特性の改善に非常に効果があると言え
る。又、浅い準位のアクセプタのみでは基板のリ
ーク電流が多くなるので、MESFET部分から十
分離れた部分では高抵抗となるように、共注入の
際深い準位のドナーの量は浅い準位のアクセプタ
の量と同等以上にすることが望ましい。
As described above, it can be said that using a high purity substrate into which both shallow level acceptors and deep level donors are implanted is very effective in improving saturation characteristics. Also, since substrate leakage current will increase if only shallow level acceptors are used, the amount of deep level donors during co-implantation should be increased by increasing the amount of deep level donors when co-implanting, so that the part far enough away from the MESFET part will have high resistance. It is desirable that the amount be equal to or higher than that of .

上記実施例においては炭素、酸素の注入量を1
×1012cm-2としたが、0.5×1012cm-2〜5×1012cm
-2程度の範囲では、同様の効果が期待できる。
In the above embodiment, the amount of carbon and oxygen implanted was 1
×10 12 cm -2 , but 0.5 × 10 12 cm -2 ~ 5 × 10 12 cm
Similar effects can be expected within the range of -2 .

また高純度エピタキシヤル成長法は、
MOCVD法に限る必要はなく、MBE(分子線エピ
タキシヤル成長法)、VPE法(気相エピタキシヤ
ル成長法)、その他の方法でもかまわない。
In addition, the high purity epitaxial growth method is
The method is not limited to MOCVD, and may be MBE (molecular beam epitaxial growth), VPE (vapor phase epitaxial growth), or other methods.

なお、上記実施例では、化合物半導体の高純度
エピタキシヤル成長層の表面から不純物イオンを
注入して不純物層を形成する際、不純物として浅
い準位のアクセプタと深いドナーの共注入の例を
述べたが、深いアクセプタのみの注入の場合にも
同様の効果が生じる。深い準位のアクセプタとし
てはバナジウム、クロム等がある。
In addition, in the above example, when forming an impurity layer by implanting impurity ions from the surface of a high-purity epitaxial growth layer of a compound semiconductor, an example was described in which a shallow level acceptor and a deep donor are co-implanted as impurities. However, a similar effect occurs with deep acceptor-only injection. Examples of deep level acceptors include vanadium and chromium.

(発明の効果) 上記のように本発明はFETのチヤネル下を流
れる電流を抑制して、高純度基板の使用時に問題
となる飽和特性の悪化を解決することができ高性
能のFETを高均一性で作製することができると
いう利点があり、GaAs集積回路に利用すること
ができる。
(Effects of the Invention) As described above, the present invention suppresses the current flowing under the FET channel and solves the deterioration of saturation characteristics, which is a problem when using a high-purity substrate. It has the advantage of being able to be fabricated in bulk, and can be used in GaAs integrated circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の断面構造図、第3
図は炭素と酸素を注入していないFETのしきい
値電圧近傍での静特性を示した図、第2図は、炭
素と酸素を注入したFETのしきい値電圧近傍で
の静特性を示した図である。 1……半絶縁性のGaAs基板、1a……高純度
エピタキシヤル成長層、1b……不純物層、2…
…n+形ソース領域、3……n+形のドレイン領域、
4……n形の活性層領域、5……ソース電極、6
……ドレイン電極、7……ゲート電極。
FIG. 1 is a cross-sectional structural diagram of one embodiment of the present invention, and FIG.
The figure shows the static characteristics near the threshold voltage of an FET without carbon and oxygen implanted, and Figure 2 shows the static characteristics near the threshold voltage of an FET with carbon and oxygen implanted. This is a diagram. 1... Semi-insulating GaAs substrate, 1a... High purity epitaxial growth layer, 1b... Impurity layer, 2...
...n + type source region, 3...n + type drain region,
4...n-type active layer region, 5...source electrode, 6
...Drain electrode, 7...Gate electrode.

Claims (1)

【特許請求の範囲】 1 少なくとも表面層が高純度の化合物半導体基
板を用意し、 その化合物半導体基板の表面から不純物イオン
を注入して不純物層を形成し、 その不純物層内にソース領域、ドレイン領域、
および活性領域を形成するようにした電界効果ト
ランジスタの製造方法において、 前記不純物が深い準位のアクセプタであるか、
又は浅い準位のアクセプタと深い準位のドナーと
の2種類であることを特徴とする電界効果トラン
ジスタの製造方法。
[Claims] 1. A compound semiconductor substrate with at least a high purity surface layer is prepared, impurity ions are implanted from the surface of the compound semiconductor substrate to form an impurity layer, and a source region and a drain region are formed in the impurity layer. ,
and a method for manufacturing a field effect transistor in which an active region is formed, wherein the impurity is a deep level acceptor;
Alternatively, a method for manufacturing a field effect transistor characterized in that there are two types: a shallow level acceptor and a deep level donor.
JP16204483A 1983-09-05 1983-09-05 Manufacture of field effect transistor Granted JPS6054479A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16204483A JPS6054479A (en) 1983-09-05 1983-09-05 Manufacture of field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16204483A JPS6054479A (en) 1983-09-05 1983-09-05 Manufacture of field effect transistor

Publications (2)

Publication Number Publication Date
JPS6054479A JPS6054479A (en) 1985-03-28
JPH0226781B2 true JPH0226781B2 (en) 1990-06-12

Family

ID=15747021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16204483A Granted JPS6054479A (en) 1983-09-05 1983-09-05 Manufacture of field effect transistor

Country Status (1)

Country Link
JP (1) JPS6054479A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229637A (en) * 1988-03-14 1993-07-20 Kabushiki Kaisha Toshiba Semiconductor device
US5153703A (en) * 1988-03-14 1992-10-06 Kabushiki Kaisha Toshiba Semiconductor device
JP2773425B2 (en) * 1990-11-21 1998-07-09 日本電気株式会社 Method for manufacturing field effect transistor

Also Published As

Publication number Publication date
JPS6054479A (en) 1985-03-28

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