JPH02229438A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To keep a high speed of electrons flowing in a channel layer by a method wherein a substance whose saturation speed of electrons is higher than that of a buffer layer and a cap layer is used for the very-thin-film channel layer. CONSTITUTION:A buffer layer 12 composed of GaAS, a channel layer 13 composed of InAs and a cap layer 14 composed of GaAs are laminated one after another on a semiinsulating substrate 11 composed of GaAs doped with chromic acid. The channel layer 13 is doped with silicon ions in such a way that its electron density is about 8X18<18>cm<-3>; the cap layer 14 is doped with Si ions in such a way that its electron density is about 2X10<16>cm<-3>. A Schottky gate metal 15 is composed of aluminum; a source electrode and a drain electrode 16, 17 are composed of an alloy of gold, germanium and nickel.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is applicable to integrated circuits (IC) and large-scale integrated circuits (LS).
The present invention relates to a metal-semiconductor field effect transistor (MESFET) used as a component of I).

[Conventional technology]

Conventionally, this type of ME using compound semiconductors such as GaAs
In SFETs, the channel layer is made extremely thin and its doping concentration is increased in order to suppress the short channel effect and improve the mutual conductance (g) and stage frequency (f). These include, for example, the IEDM conducted in 1986.
Technical Digest 8 3 2 pages (B.
J. Van Zeghbroecke
t. al. , Technical Digest 19
8B. International Electron
Devices Meeting,Los Ang
eles. 1986) or IEEE Transaction (JEEE Transaction or
Electron Dev1ces) ED-3
For details, see Vol. 3, No. 5, 1986, page 625.

[Problem to be solved by the invention]

However, when the channel layer is made extremely thin, the influence of ionized impurity scattering increases as the doping concentration of the channel increases, and as a result, the speed of electrons flowing through the channel layer is self-limited.

[Means to solve the problem]

The present invention provides a method for forming a channel layer using a semiconductor material having a high saturation velocity of electrons, which forms a buffer layer located between the channel layer and the substrate, and a cap layer located between the channel layer and the Schottky gate electrode. It is formed using a substance.

[Effect]

By using a semiconductor material with a high electron saturation velocity as the channel layer, the velocity of electrons flowing through the channel layer can be maintained high even when doped with a donor impurity at a high concentration.

Here, even if there is some lattice mismatch between the semiconductor material forming the channel layer and the semiconductor materials forming the buffer layer and cap layer, the lattice mismatch can be improved by making the thickness of the channel layer sufficiently thin. It is possible to prevent dislocations from occurring in the channel layer due to mismatch and deteriorating the crystallinity and electrical properties of the channel layer. Therefore, materials can be selected from a wide range.

Note that if the semiconductor material forming the channel layer has a lower electron affinity than the semiconductor material forming the buffer layer and cap layer, the potential well formed in the channel layer portion as a path for electrons may become shallow. Therefore, in order to maintain that depth, it is desirable to select a material that has a higher electron affinity than the semiconductor material forming the buffer layer and the cap layer.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to FIGS. 1 and 2 of the accompanying drawings.

FIG. 1 is a sectional view showing an embodiment of the present invention. Please note that the scale is not accurate.

In the figure, on a semi-insulating substrate 11 made of GaAs doped with chromic acid (CrO), a buffer layer (thickness approximately 5000 Å) 12 made of GaAs and a buffer layer made of InAs are formed by molecular beam epitaxial growth. A channel layer (2OA) 13 made of C;a and a cap layer (300A) 14 made of As are sequentially laminated. The channel layer 13 is doped with silicon (S1) ions so that its electron density is approximately 8×1818 CII1-3, and has the same "key?" The top layer 14 is 2×10
It is doped with 81 ions to about 16cm-3.

Schottky gate metal 15 is aluminum CAD)
The source/drain electrodes 16 and 17 are made of gold (Au
), germanium (Ge), nickel (Nl
) consists of an alloy.

Here, the buffer layer 12 is provided for the purpose of preventing the adverse effects from directly reaching the channel layer 13 even if the surface of the substrate 11 has poor crystallinity or contains many impurities. In addition, the cap layer 14 includes the channel layer 1
3 is InAs, and since the doping concentration is high, there is a sufficient barrier height (
The buffer layer 12, the cap layer 14, and the channel layer 13 are provided to ensure a sufficient barrier height in consideration of the fact that the barrier height cannot be removed.
Lattice mismatch problems generally arise due to the use of different semiconductor materials.

In this case, the degree of lattice mismatch that occurs is determined by the types of materials used in combination, but the electrical characteristics vary depending on the thickness of the channel layer 13. Figure 2 shows the maximum channel layer thickness (limit) that causes dislocations in the channel layer due to lattice mismatch with the materials forming the buffer layer and cap layer, and does not deteriorate the crystallinity and electrical properties of the channel layer. Film thickness) is as shown. In the combination of GaAs and InAs as in this embodiment, the lattice mismatch is about 7% and the critical film thickness is about 20A.

If the thickness of the channel layer 13 is set to less than this value, deterioration of characteristics due to lattice mismatch can be avoided, and therefore, in this embodiment, this thickness is set to 20A as described above.

Note that this invention is not limited to the above embodiments, and various modifications are possible. For example, a buffer layer, a cap layer and a channel layer. The combination of semiconductor materials forming the semiconductor material is not limited to Ga As and InAs, but may include Ga As and Ga In As (0≦
X≦1), AR, X l-X In As (0≦y≦1
) and G a I n t-,1-y
XAs (0≦X≦1
), AI2 Ga As (0≦y l−y y≦1) and Ga In As (0≦X≦1), etc.
X 1-X can be changed in various ways. As mentioned above, by setting the thickness of the channel layer below the critical thickness,
You get a wide range of choices.

Further, the epitaxial growth method is not limited to the molecular beam epitaxial growth method, and metal organic vapor phase epitaxy, vapor phase epitaxial growth, liquid phase epitaxial growth, etc. can be used. Furthermore, various changes can be made to the impurity concentration, film thickness, each electrode material, etc. without changing the gist of the present invention.

〔Effect of the invention〕

As described above, this invention uses a material with a higher electron saturation velocity than the buffer layer and the cap layer for the ultra-thin channel layer, so that even if the channel layer is doped with donor impurities at a high concentration, the channel layer can be It is possible to maintain a high velocity of flowing electrons, and M has good characteristics.
It has the effect of realizing an ESFET.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an embodiment of the present invention, and FIG. 2 is a diagram showing the relationship between the lattice mismatch between the buffer layer, the cap layer, and the channel layer and the critical thickness of the channel layer. DESCRIPTION OF SYMBOLS 11... Substrate, 12... Buffer layer, 13... Channel layer, 14... Cap layer, 15... Schottky gate electrode. Patent applicant: Sumitomo Electric Industries, Ltd.

Claims (1)

[Claims] 1. In a metal-semiconductor field effect transistor with an ultra-thin channel layer, a buffer layer located between the channel layer and the substrate and a cap located between the channel layer and the Schottky gate electrode. layer, a channel layer,
A field effect transistor characterized in that it is formed of a semiconductor material obtained by doping a donor impurity at a high concentration into a material having a higher electron saturation velocity than the semiconductor material forming the buffer layer and the cap layer. 2. The field effect transistor according to claim 1, wherein the thickness of the channel layer is reduced to such an extent that deterioration due to lattice mismatch with the buffer layer and the cap layer does not occur.