JPS63188972A - Field-effect transistor - Google Patents
Field-effect transistorInfo
- Publication number
- JPS63188972A JPS63188972A JP2092987A JP2092987A JPS63188972A JP S63188972 A JPS63188972 A JP S63188972A JP 2092987 A JP2092987 A JP 2092987A JP 2092987 A JP2092987 A JP 2092987A JP S63188972 A JPS63188972 A JP S63188972A
- Authority
- JP
- Japan
- Prior art keywords
- effect transistor
- gate
- xas
- inp
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 27
- 239000010408 film Substances 0.000 claims abstract description 13
- 150000001875 compounds Chemical class 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000010409 thin film Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000002349 favourable effect Effects 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910020489 SiO3 Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001693 membrane extraction with a sorbent interface Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、超高周波・、超高速な電界効果トランジスタ
、特にＩｎを含む化合物半導体を動作層とする電界効果
トランジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an ultra-high frequency and ultra-high speed field effect transistor, particularly to a field effect transistor whose active layer is a compound semiconductor containing In.
〈従来技術）
ＩｎＰ、 ＩｎＧａＡｓ等Ｉｎを含む化合物半導体は、
電子の飽和速度、ピーク速度が大きいなど、すぐれた性
質を有し、超高速・高周波素子材料として注目されこれ
を用いた電界効果トランジスタの検討がいくつか行なわ
れている。(Prior art) Compound semiconductors containing In, such as InP and InGaAs,
It has excellent properties such as high electron saturation velocity and high peak velocity, and has attracted attention as a material for ultrahigh-speed and high-frequency devices, and several studies have been conducted on field-effect transistors using it.
例えばＩｎＰを用いた従来技術としてはショットキーゲ
ートを用いた電界効果トランジスタ（ＭＥＳＦＥＴ）が
あり、例えばバレラ（Ｂｏｒｒｅｒａ）及びアーチャー
（Ａｒｃｈｅｒ）によりアイ・トリプルイー・Ｉ・ラン
ザクジョン・オン・エレクトロン・デバイスイズ（ＩＥ
ＥＥ Ｔｒａｎｓ、 ｏｎ Ｅｌｅｃｔｒｏｎ Ｄｅｖ
ｉｃｅｓ ｖｏｌＥＤ−２２Ｎｏ、１１ Ｎｏｖ、 １
９７５）に報告されている。第５図はこの基本構造を示
す断面図である。同図では、半絶縁性１ｎＰ基板１１上
に、 ＩｎＰ動作層１２を設け、さらにその上にドレイ
ン電極１４、ソース電極１５、ゲート電極１６を設けた
構造のＭＥＳＦＥＴである。For example, as a conventional technology using InP, there is a field effect transistor (MESFET) using a Schottky gate. (IE
EE Trans, on Electron Dev
ices volED-22No, 11 Nov, 1
975). FIG. 5 is a sectional view showing this basic structure. In the figure, the MESFET has a structure in which an InP active layer 12 is provided on a semi-insulating 1nP substrate 11, and a drain electrode 14, a source electrode 15, and a gate electrode 16 are further provided thereon.
また、５ｉ０２膜をゲート絶縁膜に用いた電界効果トラ
ンジスタ（ＭＩＳＦＥＴ）では、例えばライル（Ｌ目ｅ
）等によってエレクトロンクスレター（Ｅｌｅ（ｔｒｏ
ｎ。In addition, in a field effect transistor (MISFET) using a 5i02 film as a gate insulating film, for example, a Lyle (L-eye
) etc., the electronic letter (Ele(tro)
n.
ＬｅｔＬ、 ｖｏｌ、１４ Ｐ、６５７−６５９５ｅｐ
ｔ、 １９７Ｂ）に報告されている。この構造断面図を
第６図に示した。面図において６１はＳｉＯ３膜、６２
はＮ”ｌｎＰコンタクト層であり、第１図と同一部分は
同一番号をつけである。LetL, vol, 14 P, 657-6595ep
T, 197B). A sectional view of this structure is shown in FIG. In the plan view, 61 is a SiO3 film, 62
is an N''lnP contact layer, and the same parts as in FIG. 1 are given the same numbers.
（発明が解決しようとする問題点）
しかしながら従来の前記のようなゲート構造を用いたＩ
ｎＰ電界効果トランジスタではまずＭＥＳＩ造において
は、 ＩｎＰに対するショットキーのバリアハイドが０
．３〜０．４ｅＶ程度しかないため、逆方向リーク電流
が大きい、ゲート耐圧が小さいなどの問題がある。また
、Ｍｉｓ構造においては、 ＩｎＰ表面にｎチャネルは
容易に形成されるものの界面変成層の存在による電流等
のドリフトが生じること、また多数の界面順位の存在に
より表面ボランシャルの曲がりが小さく従ってＮチャネ
ルのディプレッションモードの素子には適応しにくい等
実用上天きな問題があった。これはＩｎを含む化合物半
導体についても同じように言える。(Problems to be Solved by the Invention) However, the conventional I
In nP field effect transistors, first of all, in the MESI structure, the Schottky barrier hide for InP is 0.
．． Since the voltage is only about 3 to 0.4 eV, there are problems such as a large reverse leakage current and a low gate breakdown voltage. In addition, in the Mis structure, although the n-channel is easily formed on the InP surface, drift of current occurs due to the presence of the interfacial metamorphic layer, and the bending of the surface voluntar is small due to the presence of a large number of interface orders, so the n-channel There were serious problems in practical use, such as difficulty in adapting to depletion mode devices. The same can be said of compound semiconductors containing In.
本発明は、上述の問題点を解消し良好な特性−を有する
超高周波、超高速電界効果トランジスタを提供すること
である。The object of the present invention is to solve the above-mentioned problems and provide an ultra-high frequency, ultra-high speed field effect transistor having good characteristics.
（問題点を解決するための手段）
本発明によればＩｎを含む化合物半導体層を電子チャネ
ルとする電界効果トランジスタにおいて、該チャネル層
の表面上にＩｎを含む化合物半導体に格子整合するＡ
Ｑ 、Ｉｎ１−ｘＡｓ薄膜を設け、さらにその上にＡ
Ｑ ｙＧａｌ−ｙＡｓ薄膜を設けた構造をｎ（ｎ層１）
回繰り返した（Ａ Ｑ ｙＧａｌ−ｙＡｓ／Ａ Ｑ Ｘ
Ｉｎ１−ｘＡｓ）ｎの多層膜を形成し該（Ａ Ｑ ｙＧ
ａｌ −ｙＡｓ／Ａ Ｑ 、Ｉｎ１−ｘＡｓ）ｎの多層
膜上に前記電子チャネル層を制御するゲート電極と前記
チャネル層にオム性接触するソース電極及びドレイン電
極を具備したことを特徴とする電界効果トランジスタが
得られる。(Means for Solving the Problems) According to the present invention, in a field effect transistor having an In-containing compound semiconductor layer as an electron channel, A lattice-matched to the In-containing compound semiconductor on the surface of the channel layer.
Q, In1-xAs thin film is provided, and A
Q The structure with yGal-yAs thin film is n (n layer 1)
Repeated times (A Q yGal-yAs/A Q
A multilayer film of In1-xAs)n is formed and the (A Q yG
A field effect characterized in that a gate electrode for controlling the electron channel layer and a source electrode and a drain electrode in ohmic contact with the channel layer are provided on a multilayer film of al-yAs/AQ, In1-xAs)n. A transistor is obtained.
（作用） 以下、本発明の詳細な説明する。(effect) The present invention will be explained in detail below.
第１図は動作層にＩｎＰを用いた本発明による電界効果
トランジスタの構造断面図である。第５図、第６図と同
一構成部分には、同じ番号を付しである。第２図は本発
明による電界効果トランジスタの熱平衡状態でのゲート
電極下のエネルギー帯図である。ここで、２１はゲート
電極領域、２２は（八Ｑ ｙＧａｌ−ｙＡｓ／Ａ Ｑ
ｘｌｎｌ−ｘＡｓ）ｎの多層構造領域、２３はＩｎＰ動
作層領域、２４は半絶縁性１ｎＰ基板領域である。第２
図に示すように〈＾Ｉｔ 、Ｇａ１−、八ｓ／Ａ Ｑ
ｘｌｎｌ−Ｊｓ）ｎ層とＩｎＰとの界面には、Ａ Ｑ
、ＩｎＡとＩｎＰとの間に［１，５ｅＶ程度の伝導帯不
連続が存在し、 ＩｎＰ中の電子は、この障壁によって
（Ａ Ｑ ｙＧａｌ−ｙＡｓ／Ａ Ｑ ｘｌｎｌ−ｇＡ
ｓ）ｎ層への拡散は少ない。一方（Ａ Ｑ ｙＧａｌ−
ｙＡｓ／Ａ Ｑ ＸＩｎ１−ｘＡｓ）ｎ層のゲートメタ
ルに対する障壁の高さは、Ａ Ｑ 、Ｇａ１−ｙＡｓが
高いバリアハイドをもつので０．８〜１．２ｅＶあり、
従ってゲートリーク電流についてもこの大きな障壁によ
って十分小さくすることができる。す−なわち上述のこ
とから明らかな様に本発明によりＩｎＰに対する実効的
なショットキーゲートの障壁の高さを高くすることがで
き、かつ、伝導帯不連続の存在により、ゲートをある程
度順方向にバイアスしてもゲートを流れる電流を十分小
さくすることができる。また（Ａ Ｑ ｙＧａ、−ｙＡ
ｓ／Ａ Ｑ ｘｌｎｌ−ｘＡｓ）ｎと ｌｎＰ界面は、
エピタキシャル成長された、格子整合したＡ Ｑ ＸＩ
ｎ１−ＸへｓとＩｎＰのへテロ接合とすることができ、
界面準位密度の小さい良好なものが得られる。さらに格
子不整による結晶の劣下を、超格子構造により緩和する
ことができるので、良質なゲート絶縁膜の形成が可能で
ある。これは、Ｉｎを含む化合物半導体についても適用
できる。以上より、界面特性の良好でゲートリーク電流
の小さい電界効果トランジスタが得られる。FIG. 1 is a structural sectional view of a field effect transistor according to the present invention using InP for the active layer. Components that are the same as those in FIGS. 5 and 6 are given the same numbers. FIG. 2 is an energy band diagram under the gate electrode of the field effect transistor according to the present invention in a thermal equilibrium state. Here, 21 is the gate electrode region, 22 is (8Q yGal-yAs/A Q
23 is an InP active layer region, and 24 is a semi-insulating 1nP substrate region. Second
As shown in the figure 〈^It , Ga1-, 8s/A Q
xlnl-Js) At the interface between the n layer and InP, AQ
, a conduction band discontinuity of about [1.5 eV exists between InA and InP, and the electrons in InP are separated by (A Q yGal-yAs/A Q xlnl-gA
s) Diffusion into the n layer is small. On the other hand (A Q yGal-
The height of the barrier of the yAs/A Q XIn1-xAs)n layer to the gate metal is 0.8 to 1.2 eV because A Q , Ga1-yAs has a high barrier hide.
Therefore, gate leakage current can also be sufficiently reduced by this large barrier. In other words, as is clear from the above, the present invention can increase the height of the effective Schottky gate barrier to InP, and due to the presence of the conduction band discontinuity, the gate can be moved in the forward direction to some extent. Even if biased to , the current flowing through the gate can be made sufficiently small. Also (A Q yGa, -yA
s/A Q xlnl-xAs)n and lnP interface are
Epitaxially grown lattice matched A Q
n1-X can be a heterojunction of s and InP,
A good product with low interface state density can be obtained. Furthermore, since crystal deterioration due to lattice misalignment can be alleviated by the superlattice structure, it is possible to form a high-quality gate insulating film. This can also be applied to compound semiconductors containing In. As described above, a field effect transistor with good interface characteristics and low gate leakage current can be obtained.
（実施例）
本実施例のＦＥＴの製造方法の１例を第１図を用いて説
明する。(Example) An example of a method for manufacturing the FET of this example will be explained using FIG. 1.
まず、半絶縁性１ｎＰ基板１１上にＶＰＥ法により不純
物濃度Ｉ Ｘ １０”ｃｍ−３のＮ形のＩｎＰ動作層１
２を２０００＾成長する。次にＭＢＥ法により、 Ｉｎ
Ｐに格子整合するノンドープＡ Ｑ ０．４ｇＩｎ０．
５２Ａｓを４０人っけ、さらにＡ Ｑ ｏ、 ４Ｇａ０
．６Ａｓを４０人つけ、これを１０回繰りしくＡ Ｑ
ｇ、４Ｇａｏ、６＾ｓ／Ａ Ｑ ０．４ｇｌｏｇ、 ５
２ＡＳ）１０多層構造膜１３を形成し、オーミックコン
タクト部のノンドープ（Ａ Ｑ ｏ、 ４ｃａ０．６Ａ
Ｓ／Ａ Ｑ ｏ、 ４ａＩｎ０．５２ＡＳ）Ｉｎ層をエ
ツチング除去する。最後に通常の方法でゲート電極及び
ソース・トレイン電極を形成して電界効果トランジスタ
を実現する。本実施例ではＡ Ｑ ｘｌｒｌｌ−ＸＡＳ
層と Ａ Ｑ ｙＧａｐ−ｙＡｓ層をともに４０λとし
たが、２つの膜厚を変化させたり、繰り返しの回数を変
えることも可能である。また、組成比を変化させてもよ
い。First, an N-type InP active layer 1 with an impurity concentration of I x 10"cm-3 is formed on a semi-insulating 1nP substrate 11 by the VPE method.
Grow 2 by 2000^. Next, by MBE method, In
Non-doped A Q 0.4gIn0. lattice matched to P.
52As, 40 people, and A Q o, 4Ga0
．． Add 6As to 40 people and repeat this 10 times.Q
g, 4Gao, 6^s/A Q 0.4glog, 5
2AS) 10 multilayer structure film 13 is formed, and the ohmic contact part is non-doped (A Q o, 4ca0.6A
S/A Qo, 4aIn0.52AS) Etch and remove the In layer. Finally, gate electrodes and source/train electrodes are formed using a conventional method to realize a field effect transistor. In this example, A Q xlrll-XAS
Although both the A Q yGap-yAs layer and the AQ yGap-yAs layer were set to have a thickness of 40λ, it is also possible to change the thickness of the two films or change the number of repetitions. Further, the composition ratio may be changed.
第３図は、本発明による電界効果トランジスタのゲート
・ソース間の電流−電圧特性を示したもので、図には従
来技術によるショットキゲートの電界効果トランジスタ
における電流−電圧特性も示しである。図に示すように
従来技術に比べて本発明による電界効果トランジスタの
ソース・ゲート間の電流−電圧特性は実効的な立上り電
圧が大きく、しかも逆方向のリーク電流も小さく耐圧も
きわめて大きく良好な特性が得られた。FIG. 3 shows the current-voltage characteristics between the gate and source of the field effect transistor according to the present invention, and also shows the current-voltage characteristics of the Schottky gate field effect transistor according to the prior art. As shown in the figure, compared to the conventional technology, the current-voltage characteristics between the source and gate of the field effect transistor according to the present invention have a large effective rise voltage, a small leakage current in the reverse direction, and a very high breakdown voltage, which is good. was gotten.
また、第４図は、本発明による電界効果トランジスタの
ゲーＩ・ソース間のＣ−■特性を示したもので、図にお
いて、従来の５ｉ０２絶縁膜を用いたＭｉｓ構造の電界
効果トランジスタのＣ−■特性も示しである。本発明に
よる電界効果トランジスタは、従来のものに比べ静特性
におけるヒステリシスが小さく電流のドリフトもない良
好な特性を示した。Furthermore, FIG. 4 shows the C-■ characteristics between the gate I and the source of the field effect transistor according to the present invention. ■Characteristics are also indicated. The field effect transistor according to the present invention exhibited good characteristics with less hysteresis in static characteristics and no current drift than conventional ones.
（発明の効果）
本発明（第１図に示すもの〉と従来のＭＥＳ横遣（第５
図に示すもの）のＩ−Ｖ特性を第３図に示す。図からも
明らかなように逆方向リーク電流は大きく減少し、高い
ゲート耐圧を得ることが可能となり、順方向バイアス時
のターンオン電圧も大きくなる。また本発明（第１図に
示すもの）と従来のＭｉｓ構造（第６図に示すもの）の
Ｃ−■特性を第４図に示す。ヒステリシスは小さくなり
界面特性の良好なものが得られる。(Effects of the invention) The present invention (shown in Figure 1) and the conventional MES sideways (as shown in Figure 5)
FIG. 3 shows the IV characteristics of the device shown in the figure. As is clear from the figure, the reverse leakage current is greatly reduced, it becomes possible to obtain a high gate breakdown voltage, and the turn-on voltage during forward bias is also increased. Further, FIG. 4 shows the C-■ characteristics of the present invention (shown in FIG. 1) and the conventional Mis structure (shown in FIG. 6). The hysteresis is reduced and good interfacial properties can be obtained.
以上より本発明によればゲートリークの小さい良好な界
面特性を有する、良好な超高周波特性を有するＩｎＰ
ＦＥＴが実現でき今後の通信情報技術に寄与するところ
が極めて大きい。As described above, according to the present invention, InP has good interfacial characteristics with small gate leakage and good ultra-high frequency characteristics.
The realization of FET will greatly contribute to future communications and information technology.
第１図は本発明による電界効果トランジスタの構造断面
図、第２図はゲート電極下のエネルギー帯図、第３図は
本発明及び従来ショットキー接合を用いた電界効果トラ
ンジスタのＩ−Ｖ特性、第４図は本発明及び従来５ｉ０
２絶縁膜を用いた電界効果トランジスタのＣ−■特性を
示す図である。第５図、第６図は従来技術によるＦＥＴ
の構造断面図である。
図において、
１１・・・半絶縁性１ｎＰ基板
１２・・・ＩｎＰ動作層
１３−−− （Ａ Ｑ ｙＧａｌ−ｙＡｓ／Ａ Ｑ ｘ
ｌｎｌ−ｘＡｓ）ｎ層１４・・・ドレイン電極
１５・・・ソース電極
１６・・・ゲート電極
２１・・・ゲート金属領域
２２− （Ａ Ｑ ｙＧａｌ−ｙへｓ／Ａ Ｑ 、Ｉｎ
１−ＸＡ５）ｎ層領域２３・・・ＩｎＰ動作層領域
２４・・・半絶縁性１ｎＰ基板領域
６１・・・ＳｉＯ□膜
６２・・・Ｎ”−１ｎＰコンタクト層
第１図
第 ２ 図 工ｎＰ基板
一２１→１−ｃ−２２キー−２３−一本−２４−第３図
第４図
電圧［Ｖ］FIG. 1 is a structural cross-sectional view of a field effect transistor according to the present invention, FIG. 2 is an energy band diagram under the gate electrode, and FIG. 3 is an IV characteristic of a field effect transistor using the present invention and a conventional Schottky junction. Figure 4 shows the present invention and conventional 5i0
2 is a diagram showing C-■ characteristics of a field effect transistor using two insulating films; FIG. Figures 5 and 6 show FETs according to conventional technology.
FIG. In the figure, 11... Semi-insulating 1nP substrate 12... InP active layer 13 --- (A Q yGal-yAs/A Q x
lnl-xAs) n layer 14...drain electrode 15...source electrode 16...gate electrode 21...gate metal region 22- (A
1-XA5) N layer region 23...InP active layer region 24...Semi-insulating 1nP substrate region 61...SiO□ film 62...N''-1nP contact layer Fig. 1 Fig. 2 Board 21→1-c-22 Key-23-One-24-Figure 3 Figure 4 Voltage [V]
Claims (1)
果トランジスタにおいて該チャネル層の表面上にＩｎを
含む化合物半導体に格子整合するＡｌ＿ｘＩｎ＿１＿−
＿ｘＡｓ薄膜を設け、さらにその上にＡｌ＿ｙＧａ＿１
＿−＿ｙＡｓ薄膜を設けた構造をｎ（ｎ≧１）回繰り返
した（Ａｌ＿ｙＧａ＿１＿−＿ｙＡｓ／Ａｌ＿ｘＩｎ＿
１＿−＿ｘＡｓ）＿ｎの多層膜を形成し該（Ａｌ＿ｙＧ
ａ＿１＿−＿ｙＡｓ／Ａｌ＿ｘＩｎ＿１＿−＿ｘＡｓ）
＿ｎの多層膜上に前記電子チャネル層を制御するゲート
電極と、前記チャネル層にオーム性接触するソース電極
及びドレイン電極を具備したことを特徴とする電界効果
トランジスタ。In a field effect transistor using a compound semiconductor layer containing In as an electron channel, Al_xIn_1_- is lattice-matched to the compound semiconductor containing In on the surface of the channel layer.
_xAs thin film is provided, and then Al_yGa_1
The structure with the ____yAs thin film was repeated n (n≧1) times (Al_yGa_1_-_yAs/Al_xIn_
A multilayer film of 1_-_xAs)_n is formed and the (Al_yG
a_1_-_yAs/Al_xIn_1_-_xAs)
A field effect transistor comprising: a gate electrode for controlling the electron channel layer; and a source electrode and a drain electrode that are in ohmic contact with the channel layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2092987A JPH0622248B2 (en) | 1987-01-30 | 1987-01-30 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2092987A JPH0622248B2 (en) | 1987-01-30 | 1987-01-30 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63188972A true JPS63188972A (en) | 1988-08-04 |
| JPH0622248B2 JPH0622248B2 (en) | 1994-03-23 |
Family
ID=12040903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2092987A Expired - Fee Related JPH0622248B2 (en) | 1987-01-30 | 1987-01-30 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0622248B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0349242A (en) * | 1989-07-17 | 1991-03-04 | Agency Of Ind Science & Technol | Field effect transistor and its manufacture |
| US5705827A (en) * | 1991-12-25 | 1998-01-06 | Nec Corporation | Tunnel transistor and method of manufacturing same |
-
1987
- 1987-01-30 JP JP2092987A patent/JPH0622248B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0349242A (en) * | 1989-07-17 | 1991-03-04 | Agency Of Ind Science & Technol | Field effect transistor and its manufacture |
| US5705827A (en) * | 1991-12-25 | 1998-01-06 | Nec Corporation | Tunnel transistor and method of manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0622248B2 (en) | 1994-03-23 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |