JPS6273675A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6273675A JPS6273675A JP60212373A JP21237385A JPS6273675A JP S6273675 A JPS6273675 A JP S6273675A JP 60212373 A JP60212373 A JP 60212373A JP 21237385 A JP21237385 A JP 21237385A JP S6273675 A JPS6273675 A JP S6273675A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- inp
- doped
- ingaas
- schottky
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title description 2
- 230000005669 field effect Effects 0.000 claims description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 235000011149 sulphuric acid Nutrition 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910021620 Indium(III) fluoride Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- JNLSTWIBJFIVHZ-UHFFFAOYSA-K trifluoroindigane Chemical compound F[In](F)F JNLSTWIBJFIVHZ-UHFFFAOYSA-K 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置に係り、特にショットキー型電界効
果トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a Schottky field effect transistor.
従来のＩｎＧａＡｓを能動層としたＭ Ｅ Ｓ Ｆ Ｆ
、Ｔの構造例を第１図に示す。このようなものとしては
、例えば物理学会（Ｔｈｅ Ｉｎ５ｔｉｔｕｔｅ ｏｆ
Ｐｈｙｓｉｃｓ）発行の［ガリウム ヒ素およびそれ
に関する化合物１９８０Ｊ［Ｇａｌｌｉｕｍ Ａｒ５ｅ
ｎｉｄｅａｎｄ Ｒｅ１ａｔｅｄ Ｃｏｍｐｏｕｎｄｓ
＋９８０］Ｐ４６５−４７３に記載のものがある。M E S F F with conventional InGaAs active layer
, T is shown in FIG. For example, the Institute of Physics (The Institute of Physics)
[Gallium Ar5e 1980J [Gallium Arsenic and Compounds Related Thereto] published by Physics)
nideand Re1ated Compounds
+980] P465-473.
）これは半絶縁性ＩｎＰ基板１にＩｎＡ Ｑ Ａｓのバ
ッファ層２゜ＩｎＧａＡｓの能動層３＊ＩｎＡＱＡｓの
ショットキー電極形成層４を順次成長し、その上にＡＱ
によるショットキー電極７を形成しそれをゲートとした
ＦＥＴである。尚、５．６はソース電極、ドレイン電極
である＊ ｒｎＧａＡｓの上に直接ＡＱを蒸着してもシ
ョットキー特性は示さないので、ＩｎＡ Ｑ Ａ！１を
利用しショットキー電極を形成している。しかしこのタ
イプのショットキーダイオードの逆方向耐圧は低いとい
う問題点がある。) This consists of sequentially growing an InAQ As buffer layer 2, an InGaAs active layer 3, and an InAQAs Schottky electrode formation layer 4 on a semi-insulating InP substrate 1.
This is an FET in which a Schottky electrode 7 is formed using the Schottky electrode 7 as a gate. Note that 5.6 is the source electrode and drain electrode.* Since AQ does not exhibit Schottky characteristics even if AQ is deposited directly on rnGaAs, InA Q A! 1 to form a Schottky electrode. However, this type of Schottky diode has a problem in that its reverse breakdown voltage is low.
本発明の目的は、能動層にＴｎｆｉａＡｓを用い、高ｇ
ｍで、ショットキーゲート形成用にＩ ｎ、 Ｐ 。The purpose of the present invention is to use TnfiaAs for the active layer and
m, I n, P for Schottky gate formation.
ＩｎＡ Ｑ Ａｓを用いた高耐圧のｌ” Ｅ Ｔを提供
することにある。The object of the present invention is to provide a high-voltage ET using InA QAs.
第２図は本発明の概念図である。ショットキー電極を形
成できないｆｉｎＧａＡｓ ａ上にＩ ｎ、 Ｐ層８゜
ＩｎＡ Ｑ Ａｓ層４を順次設はショットキー電極７を
形成したショットキーダイオードである。ここでＩｎＡ
Ｑ Ａｓ層４はＡＲとのショットキー電極を形成させ
るための層、ＩｎＰ層８は高耐圧化するために設けた層
であるにのようにすると高耐圧のＩｎＧａＡｓショット
キーダイオードを形成できる。そしてこのショットキー
特性を利用するとＭＥＳＦＥＴを形成できる。FIG. 2 is a conceptual diagram of the present invention. This is a Schottky diode in which a Schottky electrode 7 is formed by sequentially forming In, P layers, 8° InA Q As layer 4 on finGaAs a, which cannot form a Schottky electrode. Here InA
The Q As layer 4 is a layer provided to form a Schottky electrode with the AR, and the InP layer 8 is a layer provided to increase the breakdown voltage. By doing so, a high breakdown voltage InGaAs Schottky diode can be formed. By utilizing this Schottky characteristic, a MESFET can be formed.
以下、本発明の一実施例を第３図により説明する。第３
図はＩｎｏ、Ｉ！５Ｇａｏ、ａｙＡｓを能動層としたＭ
ＥＳＦＥＴの要部断面図である。まず、ＳＩ ＩｎＰ
基板上１にＯＭＶＰＥ法によりノンドープのＩｎＰバッ
ファ層１１を０．５〜３μｍの厚さに、Ｓ１ドープＩＸ
ｌＸ１０ｌ７δのＩｒ１ｏ、ａａＧａｏ、４７Ａｓ能動
層３を０．２ μｍの厚さにノンドープ若しくはライト
ドープのＩｎＰ層８を０．０５〜０．５ｖｍの厚さに、
ノンドープのＩ ｎ ｏ、ｓｚＧ ａ ０．４８Ａ Ｓ
ショットキー形成層４を０．０３〜０．１μｍの厚さに
それぞれ連続成長した。An embodiment of the present invention will be described below with reference to FIG. Third
The figure is Ino, I! 5M with Gao and ayAs as active layer
FIG. 2 is a sectional view of a main part of an ESFET. First, SI InP
A non-doped InP buffer layer 11 is formed on the substrate 1 by the OMVPE method to a thickness of 0.5 to 3 μm, and S1 doped IX is formed on the substrate 1.
An Ir1o, aaGao, 47As active layer 3 of lx10l7δ has a thickness of 0.2 μm, a non-doped or lightly doped InP layer 8 has a thickness of 0.05 to 0.5 vm,
Non-doped I no, szGa 0.48A S
Each Schottky forming layer 4 was continuously grown to a thickness of 0.03 to 0.1 μm.
メサエッチを行った後、フ第１・レジストをマスクにし
、ソース・ドレイン＠棒部分のＩｎｏ、ａｚＧａ ｏ、
ａｓＡ ｓ ４はＨａｓ Ｏａ ： Ｈ２Ｏ２： Ｈ２
Ｏ＝ ４８１＝１で、ＩｎＦ３はＨＣＱにより選択エツ
チングを行った。そのｍＡｕＧｅ／ Ｎ ｉ ／ Ａ
ｕを約０．６μｍ蒸着しリフトオフした後、４００℃で
３分間熱処理し、ソース、ドレイン電極５，６を形成し
た。After performing mesa etch, use the first resist as a mask to remove Ino, azGa o,
asA s 4 is Has Oa: H2O2: H2
At O=481=1, InF3 was selectively etched with HCQ. The mAuGe/Ni/A
After about 0.6 μm of u was deposited and lifted off, heat treatment was performed at 400° C. for 3 minutes to form source and drain electrodes 5 and 6.
その後リフトオフ法でＡＱを０゜１〜１ ｐ、 ｍ蒸着
することによりゲート電極７を形成した。Thereafter, a gate electrode 7 was formed by depositing AQ to a thickness of 0°1 to 1 m using a lift-off method.
このＦＥＴはゲート長が１−μｍの場合相互コンダクタ
ンスｇ ｍ ＝ ２００ ｍ ＦＮ／ ｍｓ 、トレイ
ン降伏電圧ＢＶｄｓ＝ ８ Ｖが得られた。In this FET, when the gate length was 1-μm, mutual conductance g m =200 mFN/ms and train breakdown voltage BVds = 8 V were obtained.
第４図はゲートをマスクにしてＩｎＡ ｒｌ Ａｓ層４
゜ＩｎＰ層８をサイドエツチングしたものである。Figure 4 shows an InA rl As layer 4 using the gate as a mask.
゜InP layer 8 is side-etched.
本実施例によればゲート長が短くなるのでより高周波化
に適する。According to this embodiment, since the gate length is shortened, it is suitable for higher frequencies.
第５図はＩｎＧａＡｓ能動層３ｖ Ｉ ｎ Ｇ ａ Ａ
ｓコンタク１一層１２を成長した後、エツチングによ
りグー１一部のみリセスし、そこへＩｎＰ層８．ＴｎＡ
ＱＡｓ層４を順次成長させたものである。FIG. 5 shows an InGaAs active layer 3v I n Ga A
After growing the contact layer 1 and 12, only a portion of the contact layer 12 is recessed by etching, and an InP layer 8 is deposited thereon. TnA
The QAs layer 4 is grown sequentially.
本実施例によりば、ソース抵抗が小さくなり、相互コン
ダクタンスｇｍが大きくなるという効果を有する。According to this embodiment, the source resistance is reduced and the mutual conductance gm is increased.
尚、以上の実施例では能動層としてＩｎＧａＡｓを用い
て説明したがＩ旧−ｘＧａｘＡｓｌ−アＰｙにおいても
同様の効果を奏することができる。また、ＩｎＰ層８の
かわりに丁ｎ１−ｘ’ Ｇａ＋ｔ’ ＡＳＩ−ｙ’ ｐ
ｙ′ を用いても同様の効果を奏する。但し、この場
合Ｉｎ１−ｘ’Ｇａｘ’ Ａｓｔ−ｙ’ Ｐｙ’の組成
比は能動層のエネルギーギャップよりも大きくなるよう
にすることが必要である。Although the above embodiments have been described using InGaAs as the active layer, the same effect can be achieved using InGaAs as the active layer. Also, instead of the InP layer 8, dn1-x'Ga+t'ASI-y'p
A similar effect can be obtained by using y'. However, in this case, the composition ratio of In1-x'Gax'Ast-y'Py' needs to be larger than the energy gap of the active layer.
本発明によれば、■ｎｏ、５ａＧａｏ、ａ７Ａｓを能動
層としたＦＥＴにおいて従来より１０〜５０％耐圧を上
げることができるのでマイクロ波用ＦＥＴとして低雑音
高出力のＦＥＴが出来る。According to the present invention, it is possible to increase the withstand voltage by 10 to 50% compared to the conventional FET in an FET having active layers of NO, 5aGao, and a7As, and thus a low-noise, high-output FET can be obtained as a microwave FET.
第１図は従来のＩｎＡ Ｑ Ａｓをショットキー形成層
として利用ＩｎＧａＡｓＭＥＳＦＥＴの断面図、第２図
は本発明の概念となるショットキーダイオードの断面図
、第３図は本発明によるＩｎＧａＡＳＭＥＳＦＥＴの断
面図、第４図、第５図は本発明の他の実施例を示す装置
の断面図である。FIG. 1 is a sectional view of a conventional InGaAs MESFET using InA Q As as a Schottky formation layer, FIG. 2 is a sectional view of a Schottky diode based on the concept of the present invention, and FIG. 3 is a sectional view of an InGaASMESFET according to the present invention. FIGS. 4 and 5 are cross-sectional views of an apparatus showing other embodiments of the present invention.
Claims (1)
能動層とし、その上にショットキー電極形成のためのＩ
ｎ＿１＿−＿ｘＡｌ＿ｘＡｓ層を設けた電界効果トラン
ジスタにおいて、前記能動層より低キャリア濃度でかつ
エネルギーギャップの大きいＩｎＰもしくは Ｉｎ＿１＿−＿ｘ′Ｇａ＿ｘ′Ａｓ＿１＿−＿ｙ′Ｐｙ
′をＩｎ＿１＿−＿ｘＧａ＿ｘＡｓ＿１＿−＿ｙＰｙ層
とＩｎ＿１＿−＿ｘＡｌ＿ｘＡｓ層との間に設けたこと
を特徴とする半導体装置。[Claims] 1. In_1_-_xGa_xAs_1_-_yPy is used as an active layer, and I for forming a Schottky electrode is formed on the active layer.
In a field effect transistor provided with an n_1_-_xAl_xAs layer, InP or In_1_-_x'Ga_x'As_1_-_y'Py has a lower carrier concentration and a larger energy gap than the active layer.
' is provided between an In_1_-_xGa_xAs_1_-_yPy layer and an In_1_-_xAl_xAs layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60212373A JPS6273675A (en) | 1985-09-27 | 1985-09-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60212373A JPS6273675A (en) | 1985-09-27 | 1985-09-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6273675A true JPS6273675A (en) | 1987-04-04 |
Family
ID=16621490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60212373A Pending JPS6273675A (en) | 1985-09-27 | 1985-09-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6273675A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2647597A1 (en) * | 1989-05-29 | 1990-11-30 | Mitsubishi Electric Corp | SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH JOINTED METAL INSULATOR AND METHOD FOR THE PRODUCTION THEREOF |
| US6144049A (en) * | 1997-02-05 | 2000-11-07 | Nec Corporation | Field effect transistor |
| JP2001068483A (en) * | 1999-08-30 | 2001-03-16 | Kyocera Corp | Semiconductor device |
-
1985
- 1985-09-27 JP JP60212373A patent/JPS6273675A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2647597A1 (en) * | 1989-05-29 | 1990-11-30 | Mitsubishi Electric Corp | SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH JOINTED METAL INSULATOR AND METHOD FOR THE PRODUCTION THEREOF |
| US6144049A (en) * | 1997-02-05 | 2000-11-07 | Nec Corporation | Field effect transistor |
| US6184547B1 (en) | 1997-02-05 | 2001-02-06 | Nec Corporation | Field effect transistor and method of fabricating the same |
| US6448119B1 (en) | 1997-02-05 | 2002-09-10 | Nec Corporation | Field effect transistor and method of fabricating the same |
| JP2001068483A (en) * | 1999-08-30 | 2001-03-16 | Kyocera Corp | Semiconductor device |
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